CN102135928A - Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware - Google Patents

Abstract

The invention relates to the technical field of evolvable hardware and fault tolerance, especially to an isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware. In the invention, basic logic units implemented based on LUT are constructed and constitute a virtual reconfigurable circuit; a software/hardware cooperative genetic algorithm is used for automatically searching for three configuration strings meeting conditions; data is continuously input to three target circuits through an excitation signal generated inside hardware so that an isomerous triple modular redundancy module is under the state of running inside hardware; and some faults are input to the virtual reconfigurable circuit in an analog manner in the form of key interruption in order to observe fault detection, fault tolerance and self-repairing procedure of the system. The method provided by the invention has excellent expandability, and can enrich the diversity of the target circuit and improve the fault-tolerant capability of the entire redundancy fault-tolerant system.

Description

Three-mode Heterogeneous Redundant Fault Tolerance Method Based on LUT-Level Evolutionary Hardware

technical field

The invention relates to the technical field of evolution hardware and fault tolerance, in particular to a three-mode heterogeneous redundancy fault tolerance method based on LUT-level evolution hardware.

Background technique

Evolvable Hardware (Evolvable Hardware, EHW) is a special hardware system that can change its structure or function according to environmental changes to adapt to the environment. Evolutionary algorithms and programmable devices provide theoretical support and material basis for it respectively. It is a biological , computer science and electronic engineering technology combined new interdisciplinary research field. Evolutionary hardware has shown great development potential in the fields of circuit design, pattern recognition, evolutionary robotics, adaptive control, fault-tolerant self-repair, and space technology, and has aroused the research interest of governments and scholars worldwide.

There are two views on evolutionary hardware: the first view is to use evolutionary hardware technology as a new circuit design methodology to replace traditional design techniques, in order to develop a new class of intelligent and automatic design technology for electronic systems. The second point of view understands and interprets evolutionary hardware from a broader perspective, thinking that it is an adaptive hardware that can change its behavior and structure through dynamic and autonomous reconfiguration. It emphasizes that evolutionary hardware itself is a self-reconfigurable system that incorporates evolutionary mechanisms, so it can make real-time adjustments to maintain the normal state of the system according to changes in the internal or external environment. Repairable electronic systems.

With the continuous increase of the scale of electronic systems, the failure of electronic systems becomes inevitable due to the environment and the aging of internal components of the system. Therefore, it is an important issue in the current commercial and military fields to study the reliability and availability of electronic systems. On the one hand, especially the harsh environment and other places that are inaccessible or inconvenient to repair, such as missiles, spacecraft, deep sea exploration, aircraft, etc. Once these failures occur, if they cannot be repaired or avoided in time, it will have disastrous consequences.

Fault tolerance means allowing errors, which means that when one or more key parts of the equipment fail, they can automatically detect and diagnose, and take corresponding measures to ensure that the equipment maintains its specified functions. Various techniques for designing and analyzing fault-tolerant systems are called fault-tolerant techniques. The characteristics of self-organization, self-adaptation and self-repair embodied by evolutionary hardware provide a new direction for improving the reliability of complex systems. The research on fault tolerance based on evolutionary hardware is of vital significance to establish new theories, new models and new methods of hardware fault tolerance based on biological evolution mechanism, and to improve the reliability of hardware systems.

Stoica et al. of JPL in the United States conducted EHW fault-tolerant research based on FPTA (Field Programmable Transistor Array, programmable transistor array) (see Document 1), and designed two fault-tolerant methods: ① Introduce faults into the evolution process to enhance evolution Robustness of the circuit to errors; ② Extract individuals from the population of evolutionary circuits that can fully handle the current fault task, and this evolution process continues until the obtained system function is the same as before the fault occurs. Mange's group at the Swiss Federal Institute of Technology and Tyrrel's group at York University in the United Kingdom are engaged in research on embryonic electronic systems (see Document 2). Professor Yang Mengfei of the China Academy of Space Technology and others have conducted research on SRAM-based FPGA, SEU (Single Event Upset, single event flip) mitigation technology in the space radiation environment (see Document 3), trying to combine evolutionary hardware with TMR (Triple Modular Redundancy, three-mode redundancy) combined with fault-tolerant technology, focusing on the optimization of the area and power consumption of fault-tolerant modules. Professor Wang Youren from Nanjing University of Aeronautics and Astronautics mainly researched the design of heterogeneous redundant fault-tolerant systems, proposed the concept of heterogeneous degree and its evaluation method, and introduced the multi-objective optimization algorithm into the design of heterogeneous redundant fault-tolerant systems ( See document 4).

Generally speaking, the current research on fault-tolerant methods based on EHW is still in its infancy, which are some basic models or algorithm research, lack of systematic research, and a fault-tolerant system based on EHW for practical applications has not yet been established.

Document 1:

D.Keymeulen and A.Stoica, Fault-Tolerant Evolvable Hardware Using Field Programmable Transistor Arrays. IEEE Transaction on Reliability, vol.49(3), PP. 305—316, 2000.

Document 2:

C.Ortega and A.Tyrrell, A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs. International Conference on Evolvable Systems 2000, PP. 155-164.

Document 3:

Gong Jian, Yang Mengfei, Evolvable hardware-based fault-tolerant technology and its principle, Aerospace Control, 2006, 24(6): 72-80.

Document 4:

Gao Guijun, Wang Youren, Yao Rui, Research on Heterogeneous Redundant Fault-Tolerant Design of Systems, Sensors and Microsystems, 2007, 26(10): 25-28.

Contents of the invention

In view of the above-mentioned technical problems, the purpose of the present invention is to provide a three-mode heterogeneous redundant fault-tolerant method based on LUT-level evolutionary hardware, to improve the fault-tolerant performance of traditional three-mode redundant fault-tolerant systems, and to adapt to evolutionary hardware Combining the characteristics of self-healing and self-healing, it solves key technical problems such as the robustness and self-healing of the fault-tolerant system.

To achieve the above object, the present invention adopts the following technical solutions:

1) Construct a basic logic unit based on LUT, and form a virtual reconfigurable circuit from these basic logic units. The connection mode between the basic logic units has an important impact on the characteristics of the virtual reconfigurable circuit and whether it can fully meet the needs of the target circuit. Therefore, the connection mode is different according to different practical applications. Finally, the virtual reconfigurable circuit is configured as the required target circuit through the configuration string.

2) Use the software-hardware coordinated genetic algorithm to automatically search for three configuration strings that meet the conditions. Generally speaking, these three configuration strings represent three target circuits with the same function but different structures. After they are respectively configured into three virtual reconfigurable circuits, a three-mode heterogeneous redundancy and voter circuit is formed. The error detection circuits are connected together to form a three-mode heterogeneous redundancy module.

3) Continuously input data to the three target circuits through the excitation signal generated inside the hardware, so that the three-mode heterogeneous redundant module is in a hardware internal operating state, and the voter circuit and error detection circuit are correct for the system Carry out real-time monitoring.

4) In the form of button interruption, simulate and inject some faults into the virtual reconfigurable circuit to observe the error detection, fault tolerance and self-repair process of the system.

A three-mode heterogeneous redundancy fault-tolerant method based on LUT-level evolutionary hardware, comprising:

(1) Realize the three-mode heterogeneous redundant fault-tolerant IP core on the FPGA. This step includes:

Through the LUT, the configuration string determines the wiring connection mode between the logic units and the specific functions to be realized by the logic units;

When configuring a configuration string to a virtual reconfigurable circuit, the virtual reconfigurable circuit represents a target circuit with a specific function;

Connect three virtual reconfigurable circuits in parallel, and connect their outputs through a voting circuit to form a three-mode heterogeneous redundancy;

Then connect the output of the three target circuits with the output of the voting circuit to form an error detection circuit;

(2) Based on the MicroBlaze soft-core CPU to realize the genetic algorithm of software and hardware collaboration, this step includes:

① Randomly generate an initialization population, and each individual in the population is for a configuration string of a circuit;

② Store the truth table of the target circuit in RAM;

③Download each individual in the population to the virtual reconfigurable circuit for online evaluation;

④After completing the evaluation of all individuals in step ③, find out whether there is an individual that meets the requirements, that is, the number of "1" in the final output corresponding to the individual is equal to the number of rows in the truth table of the target circuit;

⑤ If there is no individual that meets the requirements, a new population needs to be generated, otherwise go to step ⑥;

⑥ If an individual meeting the requirements is found, repeat step 1 until finally three individuals meeting the requirements are found, and end;

(3) The software and hardware cooperate to realize the initialization and subsequent repair of the three heterogeneous target circuits. This step includes:

① Write the three configuration strings into the three virtual reconfigurable circuits respectively;

② Part of the software running on the MicroBlaze soft-core CPU stops;

③ The input terminals of the three virtual reconfigurable circuits are connected to the excitation signal on the hardware. The excitation signal is a small piece of code written in the hardware description language, and its function is to continuously generate the input part of the truth table of the target circuit;

④ The data generated by the excitation signal is input into the virtual reconfigurable circuit, and then the result of the operation is output through the voting circuit;

⑤ If a bit in the output result of the error detection circuit is "1", it means that the target circuit on the virtual reconfigurable circuit corresponding to this position has a fault;

⑥ When a certain circuit module is detected to be faulty, the software part will be automatically started, and the operation process of method 2 will be carried out on the faulty virtual reconfigurable circuit. At this time, it is only necessary to find a suitable configuration string again. , and reconfigure the faulty virtual reconfigurable circuit, so as to realize the self-repair of the module;

(4) Simulate the injection of errors through hardware interrupts, and observe the operation and debugging of the system. This step includes:

① Realize the interrupt IP core of the button;

②When a button is pressed, a certain type of error will be randomly generated, and the error types are: constant 0, constant 1, unchanged, and flipped;

③Inject the above error codes into a random LUT of the virtual reconfigurable circuit to change the output value of the LUT, thereby affecting the output value of the entire circuit;

④ When a logic unit is configured to change its internal state, the output of the system may change.

The sub-step ③ of the step (2) further includes:

Write each individual, that is, a configuration string into the virtual reconfigurable circuit;

After the writing is completed, at the input end of the virtual reconfigurable circuit, the input part of the truth table input to the target circuit is continuously simulated;

Carry out an exclusive-or operation on the output of the virtual reconfigurable circuit and the output part of the truth table of the target circuit stored in the RAM, and output the result again;

Count the number of "1"s in the output of the previous step.

The sub-step ⑤ of the step (2) further includes:

Select the best individuals in the current population and directly enter the next generation population;

Randomly change a certain bit or bits of the configuration string of the best individual in the current population with a certain probability, and then put it into the next generation population;

Repeat the operation of the previous step several times until the number of individuals in the new generation population is the same as that of the previous generation.

The present invention has the following advantages and positive effects:

1) The present invention uses LUT-level virtual reconfigurable circuits as the hardware basis for circuit evolution, which has good scalability and can enrich the diversity of target circuits;

2) The present invention uses online evolution based on software and hardware collaborative work, which can make full use of the physical characteristics of the target device, evolve a target circuit suitable for the actual working environment, and provide guarantee for the correctness of the circuit in a specific environment;

3) The present invention adopts a three-mode heterogeneous redundancy mode, which reduces the error correlation between three different modules, that is, the possibility of simultaneous errors, thereby improving the fault tolerance of the entire redundant fault-tolerant system.

Description of drawings

Fig. 1 is the result diagram of the basic logic unit of the present invention.

Fig. 2 is a structural diagram of a virtual reconfigurable circuit in the present invention.

Fig. 3 is a structural diagram of the IP core of the three-mode heterogeneous redundant fault-tolerant system of the present invention.

Fig. 4 is a principle diagram of triple-mode redundancy in the present invention.

Fig. 5 is a flowchart of system initialization in the present invention.

Fig. 6 is a flow chart of system error detection and error tolerance in the present invention.

Fig. 7 is a general structure diagram of the system of the present invention.

Detailed ways

The three-mode heterogeneous redundant fault-tolerant method based on LUT level evolution hardware provided by the present invention comprises the following steps:

1. Realize three-mode heterogeneous redundant fault-tolerant IP core on FPGA;

The three-mode heterogeneous redundant fault-tolerant IP core includes three bases for constructing the target circuit, that is, the virtual reconfigurable circuit; the voting circuit, the error detection circuit and the RAM storing the truth table of the target circuit.

First of all, the basis of the entire IP core is the basic logic unit, which is implemented based on a LUT (Look-Up-Table, look-up table) and consists of multiple multiplexers and a LUT. LUT is essentially a RAM. Its principle is that after writing data into RAM in advance, whenever a signal is input, it is equivalent to inputting an address to look up the table, find out the content corresponding to the address, and then output it. Each combination logic in a digital circuit can be expressed as a LUT multiplexer to select a specific bit in the input signal of the logic unit as the input of the RAM, and its function is equivalent to determining the specific connection between this module and the previous module. Line mode; what is stored in the RAM is a binary string representing the specific function of the logic unit, which is equivalent to a truth table of a combinational logic circuit. Therefore, the configuration string of the module determines the wiring connection mode between the logic units and the specific functions to be realized by the logic units.

Then, the virtual reconfigurable circuit is composed of basic logic units with m rows and n columns. Each basic logic unit is a configurable circuit module with the same structure. The output of each logic unit may become the output of the next column of logic units. The input may also become part of the final output of the entire virtual reconfigurable circuit. When a configuration string is configured to a virtual reconfigurable circuit, the virtual reconfigurable circuit actually represents a target circuit with a specific function. This configuration string not only contains the functional configuration information of each basic logic unit, but also includes the interconnection information between logic units, and also determines which basic logic unit outputs jointly form the final circuit output result.

Then, the three virtual reconfigurable circuits are connected in parallel, and their outputs are connected through the voting circuit to form a three-mode heterogeneous redundancy. Its function is to make the final output of the entire module always take the output value of the three target circuits The majority value in , that is, when an error occurs in a certain target circuit module, the error output value of the module will be masked, without affecting the final correctness of the output of the entire module.

Finally, the output of the three target circuits is connected with the output of the voting circuit to form an error detection circuit. Its function is to compare the final output result with the output values of the three target circuits. As a result, it is judged which module has caused the error.

In addition, the IP core also includes a RAM circuit that stores the target truth table, and participates in the operation of the genetic algorithm coordinated by software and hardware.

2. Based on the MicroBlaze soft-core CPU to realize the genetic algorithm of software and hardware collaboration;

The target circuit with the same function but different structure is searched through the genetic algorithm. The main part of the algorithm runs on the MicroBlaze soft-core CPU, and the fitness value evaluation part needs to rely on the virtual reconfigurable in the three-mode heterogeneous redundant fault-tolerant IP core. The circuit is evaluated online with the RAM circuit, and then the fitness value is calculated.

The algorithm steps are described as follows:

Step 1 Randomly generate an initialization population, and each individual in the population is for a configuration string of a circuit.

Step 2 Store the truth table of the target circuit in RAM.

Step 3 Download each individual in the population to the virtual reconfigurable circuit for online evaluation.

Step 3.1 Write each individual, that is, a configuration string into the virtual reconfigurable circuit.

Step 3.2 After the writing is completed, at the input end of the virtual reconfigurable circuit, continuously simulate the input part of the truth table of the input target circuit.

Step 3.3 Perform an exclusive OR operation on the output of the virtual reconfigurable circuit and the output part of the truth table of the target circuit stored in RAM, and output the result again.

Step 3.4 Calculate the number of "1" in the output result of the previous step.

Step 4 After completing the evaluation of all individuals in step 3, find out whether there is an individual that meets the requirements, that is, the number of "1" in the final output corresponding to this individual is equal to the number of rows in the truth table of the target circuit.

Step 5 If there are no individuals that meet the requirements, a new population needs to be generated. Otherwise go to step 6.

Step 5.1 Select the best individuals in the current population and directly enter the next generation population.

Step 5.2 Randomly change a certain bit or some bits of the optimal individual in the current population with a certain probability, and then put it into the next generation population.

Step 5.2 Repeat the operation of 5.2 several times until the number of individuals in the new generation population is the same as that of the previous generation.

In step 6, if an individual meeting the requirements is found, repeat step 1 until finally three individuals meeting the requirements are found, and the algorithm stops.

3. The software and hardware cooperate to realize the initialization and subsequent repair of three heterogeneous target circuits;

In the previous step, through the genetic algorithm, three configuration strings are found, and at this time they can be configured for the three virtual reconfigurable circuits.

Step 1 Write three configuration strings into three virtual reconfigurable circuits respectively.

Step 2 The software running on the MicroBlaze soft-core CPU is partially stopped.

Step 3 The input terminals of the three virtual reconfigurable circuits are connected to the excitation signal on the hardware. The excitation signal is a small piece of code written in the hardware description language, and its function is to continuously generate the input part of the truth table of the target circuit.

Step 4 The data generated by the excitation signal is input into the virtual reconfigurable circuit, and then the result of the operation is output through the voting circuit.

Step 5 Monitor the output result of the error detection circuit mentioned in method 1. If a bit in the output result of the error detection circuit is "1", it means that the target circuit on the virtual reconfigurable circuit corresponding to this position has a fault .

Step 6: When a certain circuit module is detected to be faulty, the software part will be started automatically, and the operation process of method 2 will be performed on the faulty virtual reconfigurable circuit. At this time, it is only necessary to find a suitable configuration again string, and reconfigure the faulty virtual reconfigurable circuit, so as to realize the self-healing of the module.

4. Simulate the injection of errors through hardware interrupts, and observe the operation and debugging of the system.

Through the hardware excitation signal, a special configuration string is injected into the basic logic unit to change the normal output of the unit, which is used to simulate an error in a node in the virtual reconfigurable circuit, and then observe the fault-tolerant process of the system and Debug system performance.

The hardware excitation signal is generated by a button. After pressing the button, a configuration string is randomly generated and downloaded to a logic unit of the virtual reconfigurable circuit.

Step 1 Realize the interrupt IP core of the button. The definition of the IP core is usually as follows:

entity ButtonFilter is

Generic(CLK_FREQ : integer;

NUM_SWITCHES : integer);

port ( clk : in std_logic;

reset : in std_logic;

Buttonarray: in std_logic_vector (num_switches-1 downloado 0);

Pressarray: Out STD_LOGIC_VECTOR (NUM_SWITCHES-DOWNTO 0));

end entity ButtonFilter;

Three buttons are defined here to form a button group, and these three buttons respectively control three virtual reconfigurable circuits for fault injection.

Step 2 When a button is pressed, a certain type of error will be randomly generated. The error types are: constant 0, constant 1, unchanged, and flipped. Corresponding to the codes ""10, "11", "00" and "01" respectively.

Step 3 Inject the above error codes into a random LUT of the virtual reconfigurable circuit to change the output value of the LUT, thereby affecting the output value of the entire circuit.

Step 4 When a logic unit is configured to change its internal state, the output of the system may change. At this time, if the error detection circuit detects that the target circuit on a certain virtual reconfigurable circuit is faulty, then transfer to method 3 for self-repair.

Below in conjunction with accompanying drawing, the present invention will be further described with specific embodiment:

This example is implemented on the XC2VP30 FPGA development board, using the MicroBlaze soft core as the processor, the on-chip memory as the memory, and the four-bit parity circuit as the target circuit. In addition, the present invention provides an error injection mechanism to simulate errors that may occur in reality, and artificially inject it into the IP core at a certain moment in order to observe the fault-tolerant process and effect of the entire system. Therefore, The design of the basic logic unit adopts the LUT method with error injection.

As shown in Figure 1, the specific structure diagram of a basic logic unit is followed by an error injection module for testing the entire system. The error injection method is to simulate different errors by inputting an additional set of excitation signals. type, causing an error to occur in a basic logical unit. This set of additional excitation signals does not belong to the configuration string of the target circuit and does not participate in the evolution, so it does not increase the length of the configuration string, and by default, the excitation signal is "00", which does not change the correctness of the basic logic unit. Equivalent to no error occurring.

As shown in Figure 2, the virtual reconfigurable circuit is constructed of basic logic units with 8 rows and 4 columns, and the input of each column of logic units comes from the output of the previous column of logic units and the original input signal of the system; The output of the reconstructed circuit is selected from the output values of all the basic logic units. For each virtual reconfigurable circuit, there is a final configuration string to indicate the target circuit realized by the virtual reconfigurable circuit. For the configuration string, we define it through a structure, which is defined as follows:

typedef struct

{

Xuint32 cellConfigs[NUM_CELLS];

Xuint32 outputSel0;

Xuint32 outputSel1;

Xuint32 fitness;

} ArrayConfig;

Among them, Xuint32 is a 32-bit unsigned integer, cellConfigs[NUM_CELLS] is an array storing configuration strings of each basic logic unit, where the value of NUM_CELLS is 32; outputSel0 and outputSel1 are selection signals for circuit output nodes, determined by Which two nodes constitute the output node of the final target circuit; fitness represents the fitness value of the virtual reconfigurable circuit configuration string.

As shown in Figure 3, the IP core of the three-mode heterogeneous redundant fault-tolerant system is mainly composed of a virtual reconfigurable circuit, a voting circuit, an error detection circuit and a RAM storing the truth table of the target circuit. The IP core can work in conjunction with the software part, or directly in conjunction with other hardware logic. When the system is initialized and the system is in the stage of fault-tolerant repair, the IP core and the software part operate in cooperation. When the three virtual reconfigurable circuits are initialized and there is no error injection, or when the error has been fixed, the software part will be closed and enter the internal operation stage of the hardware. The purpose of this stage is to provide conditions for error simulation injection. At this time, the Input signal will continuously input data to stimulate the normal operation of the three fault-tolerant modules, voting circuits and error detection circuits until a certain error is injected. On a certain module, simulate the occurrence of a certain type of error in order to observe the fault-tolerant process and effect of the entire system.

As shown in Figure 4, the implementation principle of the voting circuit is a combinational logic circuit, and the expression is: OUT=AB+BC+AC. When an error occurs in one of the three input signals of ABC, that is, when the input value of the other two is different, the value of OUT remains unchanged, not the original value, which is the majority value in ABC. Therefore, the fault tolerance to a faulty module can be realized and the repair program for the module can be started at the same time when the OUT value remains unchanged, that is, without affecting the system performance.

As shown in Figure 5, in the system initialization stage, through software and hardware coordination, the genetic algorithm is used to search for the configuration strings of three target circuits with the same function but different structures, and configure them into three virtual reconfigurable circuit structures. Complete the initialization of the entire fault-tolerant system. Firstly, the truth table of the target circuit is written into RAM, its function is to calculate the individual fitness value in the evolution process, until the fitness value meets the needs of the target circuit, the configuration string representing the target circuit is found. The search process is repeated three times, and three target circuit configuration strings with the same function but different structures are found. After completion, the software part will stop running, and the system will switch to the internal running state of the hardware part.

As shown in Figure 6, in the fault-tolerant stage of the system, the entire circuit will be in the internal operating state of pure hardware, and the Input input signal will be continuously input into the input part of the truth table to motivate the entire fault-tolerant module to be in the running state. At this time, the voting Both the circuit and the error detection circuit are working normally. The system will not perform fault-tolerant processing until a certain error state occurs. In the present invention, three buttons are used to simulate and inject errors. The injection uses the system interrupt method, because the MicroBlaze processor is used, so the interrupt function is defined as:

void setupInterrupts(void)

{

// Register Button Interrupt Handler

XIntc_RegisterHandler( XPAR_XPS_INTC_0_BASEADDR,

XPAR_XPS_INTC_0_PLB_IFCE_FTSYSTEM_0_BUTTONIRQ_INTR,

(XInterruptHandler)buttonPressISR, (void *)0);

// Enable the Interrupt Controller

XIntc_mMasterEnable(XPAR_XPS_INTC_0_BASEADDR);

// Set Interrupt Controller Enable for the buttons

XIntc_mEnableIntr(XPAR_XPS_INTC_0_BASEADDR, XPAR_PLB_IFCE_FTSYSTEM_0_BUTTONIRQ_MASK);

// Enable Microblaze Interrupts

microblaze_enable_interrupts();

}

When a circuit module fails, the error detection circuit will detect the faulty module, and then start the software part, together with the virtual reconfigurable circuit where the faulty module is located, perform a search process similar to the system initialization stage again to find a new configuration String, and configure the system, and then restore the correct function of the wrong module. Once repaired, the system software will stop again, and the entire system will run internally again.

As shown in Figure 7, the overall structure of the system mainly includes the PLBv46 bus and the SPLB bus. The PLBv46 bus is a common channel for data exchange between the processor and all external devices. Each external device is mounted on the PLBv46 bus through the SPLB bus. In this example, there are three IP cores that come with the system: XPS BRAM on-chip memory, XPS INTC interrupt, and UART Lite serial communication, and FTBlock user-defined IP core, that is, the three-mode heterogeneous redundancy in the present invention. I fault-tolerant IP core. Each IP core has an independent start address and offset address assigned by the system. There are defined registers in the IP core, which are used to store the data that needs to be exchanged with the processor.

The above embodiments are only for the purpose of illustrating the present invention, rather than limiting the present invention. Those skilled in the relevant technical fields can also make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent All technical solutions fall within the protection scope of the present invention.

Claims (3)

1. A three-mode heterogeneous redundant fault-tolerant method based on LUT level evolution hardware, characterized in that: (1) Realize the three-mode heterogeneous redundant fault-tolerant IP core on the FPGA. This step includes: Through the LUT, the configuration string determines the wiring connection mode between the logic units and the specific functions to be realized by the logic units; When configuring a configuration string to a virtual reconfigurable circuit, the virtual reconfigurable circuit represents a target circuit with a specific function; Connect three virtual reconfigurable circuits in parallel, and connect their outputs through a voting circuit to form a three-mode heterogeneous redundancy; Then connect the output of the three target circuits with the output of the voting circuit to form an error detection circuit; (2) Based on the MicroBlaze soft-core CPU to realize the genetic algorithm of software and hardware collaboration, this step includes: ① Randomly generate an initialization population, and each individual in the population is for a configuration string of a circuit; ② Store the truth table of the target circuit in RAM; ③Download each individual in the population to the virtual reconfigurable circuit for online evaluation; ④After completing the evaluation of all individuals in step ③, find out whether there is an individual that meets the requirements, that is, the number of "1" in the final output corresponding to the individual is equal to the number of rows in the truth table of the target circuit; ⑤ If there is no individual that meets the requirements, a new population needs to be generated, otherwise go to step ⑥; ⑥ If an individual meeting the requirements is found, repeat step 1 until finally three individuals meeting the requirements are found, and end; (3) The software and hardware cooperate to realize the initialization and subsequent repair of the three heterogeneous target circuits. This step includes: ① Write the three configuration strings into the three virtual reconfigurable circuits respectively; ② Part of the software running on the MicroBlaze soft-core CPU stops; ③ The input terminals of the three virtual reconfigurable circuits are connected to the excitation signal on the hardware. The excitation signal is a small piece of code written in the hardware description language, and its function is to continuously generate the input part of the truth table of the target circuit; ④ The data generated by the excitation signal is input into the virtual reconfigurable circuit, and then the result of the operation is output through the voting circuit; ⑤ If a bit in the output result of the error detection circuit is "1", it means that the target circuit on the virtual reconfigurable circuit corresponding to this position has a fault; ⑥ When a certain circuit module is detected to be faulty, the software part will be automatically started, and the operation process of method 2 will be carried out on the faulty virtual reconfigurable circuit. At this time, it is only necessary to find a suitable configuration string again. , and reconfigure the faulty virtual reconfigurable circuit, so as to realize the self-repair of the module; (4) Simulate the injection of errors through hardware interrupts, and observe the operation and debugging of the system. This step includes: ① Realize the interrupt IP core of the button; ②When a button is pressed, a certain type of error will be randomly generated, and the error types are: constant 0, constant 1, unchanged, and flipped; ③Inject the above error codes into a random LUT of the virtual reconfigurable circuit to change the output value of the LUT, thereby affecting the output value of the entire circuit; ④ When a logic unit is configured to change its internal state, the output of the system may change. 2. the three-mode heterogeneous redundant fault-tolerant method based on LUT level evolution hardware according to claim 1, is characterized in that: The sub-step ③ of the step (2) further includes: Write each individual, that is, a configuration string into the virtual reconfigurable circuit; After the writing is completed, at the input end of the virtual reconfigurable circuit, the input part of the truth table input to the target circuit is continuously simulated; Carry out an exclusive-or operation on the output of the virtual reconfigurable circuit and the output part of the truth table of the target circuit stored in the RAM, and output the result again; Count the number of "1"s in the output of the previous step. 3. the three-mode heterogeneous redundant fault-tolerant method based on LUT level evolution hardware according to claim 1 or 2, is characterized in that: The sub-step ⑤ of the step (2) further includes: Select the best individuals in the current population and directly enter the next generation population; Randomly change a certain bit or bits of the configuration string of the best individual in the current population with a certain probability, and then put it into the next generation population; Repeat the operation of the previous step several times until the number of individuals in the new generation population is the same as that of the previous generation.

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