CN102135928A - Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware - Google Patents
Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware Download PDFInfo
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Abstract
The invention relates to the technical field of evolvable hardware and fault tolerance, especially to an isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware. In the invention, basic logic units implemented based on LUT are constructed and constitute a virtual reconfigurable circuit; a software/hardware cooperative genetic algorithm is used for automatically searching for three configuration strings meeting conditions; data is continuously input to three target circuits through an excitation signal generated inside hardware so that an isomerous triple modular redundancy module is under the state of running inside hardware; and some faults are input to the virtual reconfigurable circuit in an analog manner in the form of key interruption in order to observe fault detection, fault tolerance and self-repairing procedure of the system. The method provided by the invention has excellent expandability, and can enrich the diversity of the target circuit and improve the fault-tolerant capability of the entire redundancy fault-tolerant system.
Description
Technical field
The present invention relates to develop hardware and fault-tolerant technique field relate in particular to a kind of three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware.
Background technology
Evolution hardware (Evolvable Hardware, EHW) be a kind ofly can change self structure or the special hardware system of function according to environmental change to conform, evolution algorithmic and programming device provide theoretical support and material base respectively for it, and it is the novel crossed research field that biology, computer science and electronic engineering technology combine.Evolution hardware has shown huge development potentiality in fields such as circuit design, pattern-recognition, evolution robot, adaptive control, fault-tolerant selfreparing and space technologies, has worldwide evoked national governments and scholar's research interest.
About evolution hardware two kinds of viewpoints are arranged: first kind of viewpoint is with a kind of novel circuit design method of traditional design technology as an alternative of evolution hardware technology, in the hope of intellectuality, the The Automation Design technology that develops the brand-new electronic system of a class.Second kind of viewpoint then understood and annotated evolution hardware from a more wide angle, think it be a kind of can be by dynamically independently reshuffling the self-adaptation hardware that changes self behavior and structure.It emphasize to develop hardware itself be exactly merged the mechanism that develops from reconfigurable system, thereby can be according to the variation of inside or external environment condition, adjust in real time to keep the normal condition of system, its target is the electronic system that development one class possesses self-adaptation and self-reparing capability.
Continuous increase along with the electronic system scale, because problems such as environment and internal system component aging make the fault of electronic system become inevitable, therefore study the reliability of electronic system and the importance that availability issue is current commerce, military field, especially environment badly waits the place of artificial unreachable or inconvenient reparation, for example guided missile, spaceship, deep-sea detecting, aircraft etc., and these faults are in case take place if can not in time repair or avoid the catastrophic consequence of generation.
Fault-tolerant is exactly to allow mistake, when the one or more key components that are meant equipment break down, can automatically detect and diagnose, and take appropriate measures, and the equipment of assurance is kept the function of its regulation.The various technology of design and analysis tolerant system are called fault-tolerant technique.The characteristics of the self-organization that evolution hardware is embodied, self-adaptation, selfreparing provide brand-new direction for the reliability that improves complication system.To setting up hardware fault-tolerant new theory, new model and the new method of using for reference biological evolution mechanism, the reliability that improves hardware system has great important based on the fault-tolerant research of evolution hardware.
The people such as Stoica of U.S. JPL are based on FPTA(Field Programmable Transistor Array, programmable transistor array) carried out the fault-tolerant research of EHW (referring to document 1), designed two kinds of fault-tolerance approaches: 1. fault has been incorporated into and goes in the process of evolution to strengthen the circuit that develops robustness to mistake; 2. extract the individuality that can fully handle when the prior fault task from the colony of evolution circuit, this evolutionary process lasts till the systemic-function and the preceding identical state that breaks down of acquisition always.The group of the Mange group of technical college of Swiss Confederation and the Tyrrel of Britain York university is engaged in the research (referring to document 2) about embryo's electronic system.People such as professor Yang Mengfei of the Chinese Academy of Space Technology are to the FPGA based on SRAM, SEU(Single Event Upset in space radiation environment, single-particle inversion) slows down technology and carried out studying (referring to document 3), trial is with evolution hardware and TMR(Triple Modular Redundancy, triplication redundancy) fault-tolerant technique combines, and pays close attention in the area of fault-tolerant module and the optimization of power consumption.People such as professor Wang Youren of Nanjing Aero-Space University mainly study the design of isomery redundancy fault-tolerant system, have proposed the notion and the evaluation method thereof of isomery degree, and multi-objective optimization algorithm are incorporated into (referring to document 4) in the middle of the design of isomery redundancy fault-tolerant system.
Generally speaking, the fault-tolerance approach research based on EHW at present also is in the starting stage, is some basic model or algorithm researches, lacks systematic research, does not also set up a tolerant system based on the practical application of EHW as yet.
Document 1:
D.Keymeulen?and?A.Stoica,?Fault-Tolerant?Evolvable?Hardware?Using?Field?Programmable?Transistor?Arrays.?IEEE?Transaction?on?Reliability,?vol.49(3),?PP.?305—316,?2000.
Document 2:
C.Ortega?and?A.Tyrrell,?A?Hardware?Implementation?of?an?Embryonic?Architecture?Using?Virtex?FPGAs.?International?Conference?on?Evolvable?Systems?2000,?PP.?155-164.
Document 3:
Gong Jian, Yang Mengfei is based on the fault-tolerant technique and the principle thereof of the hardware of can evolving, Aerospace Control, 2006,24 (6): 72-80.
Document 4:
Gao Guijun, Wang Youren, Yao Rui, system's isomery redundancy fault-tolerant design studies, sensor and micro-system, 2007,26 (10): 25-28.
Summary of the invention
Technical matters at above-mentioned existence, the purpose of this invention is to provide a kind of three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware, to improve the fault freedom of traditional triplication redundancy tolerant system, and combine with the self-adaptation of evolution hardware, the characteristics of selfreparing, solve the key technical problems such as robustness, self-repairability of tolerant system.
For achieving the above object, the present invention adopts following technical scheme:
1) constructs a kind of basic logic unit of realizing based on LUT, and form virtual reconfigurable circuit by these basic logic units.Mode of communicating between the basic logic unit, to the characteristic of virtual reconfigurable circuit, and the needs important influence that whether fully satisfies objective circuit, therefore according to the difference of practical application, mode of communicating is also inequality.By the configuration string this virtual reconfigurable circuit is configured to needed objective circuit at last.
2) use the genetic algorithm of software-hardware synergism to search for three configuration strings that satisfy condition automatically.In general, but these three configuration strings have been represented three different objective circuits of the identical structure of function, after they are configured to three virtual reconfigurable circuits respectively, just formed that three mould isomeries are redundant to be connected with voting machine circuit and error detection circuit, formed three mould isomery redundant modules jointly.
3) by the inner pumping signal that produces of hardware, to the input data constantly of three objective circuits, thereby make three mould isomery redundant modules be in a kind of hardware internal operation state, voting machine circuit and error detection circuit carry out real-time monitoring to the correctness of system.
4) form of interrupting with button, some faults of injection of simulating in the virtual reconfigurable circuit are used for the error detection of recording geometry, fault-tolerant and selfreparing flow process.
A kind of three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware comprise:
(1) IP kernel of realization three mould isomery redundancy fault-tolerants on FPGA, this step comprises:
By LUT, the concrete function that will realize by wiring connected mode between the configuration string decision logic unit and logical block;
When some configuration strings were configured to virtual reconfigurable circuit, this virtual reconfigurable circuit had been represented the objective circuit of some specific functions;
With three virtual reconfigurable circuit parallel connections, and its output terminal connected by voting circuit, thereby form three mould isomery redundancies;
Again the output of three objective circuits and the output of voting circuit are connected to form error detection circuit;
(2) based on the genetic algorithm of MicroBlaze soft nucleus CPU realization software-hardware synergism, this step comprises:
1. produce the initialization population at random, each individuality in the population is all for the configuration string of a circuit;
2. the truth table with objective circuit is stored among the RAM;
3. each individuality in the population is downloaded to virtual reconfigurable circuit and carry out online evaluation;
4. after 3. step has finished assessment to all individualities, find out whether the individuality that meets the demands is arranged, promptly should the pairing final output result of individuality in the number of " 1 " equal the line number of objective circuit truth table;
If the individuality that does not 5. meet the demands then needs to produce new population, otherwise to the 6. step;
If 6. found the individuality that meets the demands, then carry out step 1 again, until finally having found three individualities that meet the demands, finish;
(3) software-hardware synergism realizes that this step comprises to the initialization of three isomery objective circuits and later repair:
1. with three configuration strings, be written to respectively among three virtual reconfigurable circuits;
2. run on that software section stops on the MicroBlaze soft nucleus CPU;
3. the input end of three virtual reconfigurable circuits has been connected to the pumping signal on the hardware, and this pumping signal is a bit of code of writing with hardware description language, and its effect is the importation that constantly produces the truth table of objective circuit;
4. the data of pumping signal generation are imported among the virtual reconfigurable circuit, and the result with computing exports by voting circuit then;
If 5. a certain position fault occurred for " 1 " then represent objective circuit on the pairing virtual reconfigurable circuit in this position among the error detection circuit output result;
6. when detecting after some circuit modules break down, to start software section automatically, the operational scheme that occurs the wrong enterprising row method 2 of virtual reconfigurable circuit at that piece, and only need find out a suitable configuration string again this moment, and that virtual reconfigurable circuit of makeing mistakes reshuffled, thereby realize the selfreparing of this module;
(4) simulate wrong injection by hardware interrupts, the operation of recording geometry and debugging, this step comprises:
1. realize the interruption IP kernel of button;
2. when when the next button, just produce the mistake of a certain type at random, type of error is respectively: normal 0, normal 1, constant, upset;
3. with above error code, be injected into respectively on LUT at random of virtual reconfigurable circuit, be used for changing the output valve of this LUT, thereby influence the output valve of entire circuit;
4. after some logical blocks were configured falsification and have become its internal state, the output result of system just might change.
The substep of described step (2) 3. further comprises:
With each individuality, promptly a configuration string writes virtual reconfigurable circuit;
Write finish after, at the input end of virtual reconfigurable circuit, the importation of the truth table of analog input objective circuit constantly;
The output of the truth table of the objective circuit deposited among the output of virtual reconfigurable circuit and the RAM is carried out same exclusive disjunction, once more the result is exported;
The number of " 1 " among the output result of calculating previous step.
The substep of described step (2) 5. further comprises:
Optimum individual in the present population is selected, directly entered population of future generation;
With the optimum individual in the present population,, put into population of future generation then with a certain position or some position of its configuration string of a certain probability change at random;
The operation that previous step is rapid repeats repeatedly, and number individual in population of new generation is identical with previous generation.
The present invention has the following advantages and good effect:
1) the present invention's employing, is with good expansibility as the hardware foundation that circuit develops based on the virtual reconfigurable circuit of LUT level, can enrich the diversity of objective circuit;
2) online evolution that is based on the cooperative work of software and hardware mode that uses of the present invention can make full use of the physical characteristics of target devices, and developing to be fit to the objective circuit of actual working environment, for the correctness of circuit in specific environment provides safeguard;
3) the present invention adopts three mould isomery redundant fashions, has reduced the false correlations between three disparate modules, the possibility of promptly makeing mistakes simultaneously, thus improved whole redundancy fault-tolerant system survivability.
Description of drawings
Fig. 1 is basic logic unit of the present invention figure as a result.
Fig. 2 is a virtual reconfigurable circuit structural drawing among the present invention.
Fig. 3 is the present invention's three mould isomery redundancy fault-tolerant system IP kernel structural drawing.
Fig. 4 is a triplication redundancy schematic diagram among the present invention.
Fig. 5 is a system initialization process flow diagram among the present invention.
Fig. 6 is system's error detection among the present invention, fault-tolerant process flow diagram.
Fig. 7 is system global structure figure of the present invention.
Embodiment
Three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware provided by the invention may further comprise the steps:
1, on FPGA, realizes the IP kernel of three mould isomery redundancy fault-tolerants;
The IP kernel of three mould isomery redundancy fault-tolerants has comprised three bases that are used to construct objective circuit, promptly virtual reconfigurable circuit; Voting circuit, the RAM of error detection circuit and stored target circuit truth table.
At first, the basis of entire I P nuclear is a basic logic unit, with based on LUT(Look-Up-Table, look-up table) mode realize, form jointly by a plurality of MUX and a LUT.LUT is exactly a RAM in essence, and its principle is after data are write RAM in advance, whenever signal of input, just equals to have imported an address and tables look-up, and finds out the content of this address correspondence, then output.Each combinational logic in the digital circuit can be expressed as the concrete a certain position of input signal that a LUT MUX is used for selecting logical block as the input of RAM, and its effect is equal to the concrete connection mode of this module of decision and prior module; What deposit among the RAM is the binary string of representing this logical block concrete function, is equivalent to the truth table of a combinational logic circuit.Therefore, the concrete function that will realize by wiring connected mode between this modules configured string decision logic unit and logical block.
Then, virtual reconfigurable circuit is made of the basic logic unit of the capable n row of m, each basic logic unit all is identical in structure configurable circuit modules, the output of each logical block all might become the input of a row logic unit thereafter, also all might become the part that whole virtual reconfigurable circuit is finally exported the result.When some configuration strings were configured to virtual reconfigurable circuit, this virtual reconfigurable circuit had in fact just been represented the objective circuit of some specific functions so.This configuration string the inside had both comprised the functional configuration information of each basic logic unit, had also comprised the information that interconnects between the logical block, had also determined to form jointly final circuit output result by the output of which basic logic unit.
Then, with three virtual reconfigurable circuit parallel connections, and its output terminal is connected by voting circuit, thereby form three mould isomery redundancies, its effect is to make the final output of whole module get the value that occupies the majority in the output valve of three objective circuits all the time, promptly when mistake appearred in some objective circuit modules, the wrong output valve meeting conductively-closed of this module did not influence the correctness that final whole module is exported.
At last again the output of three objective circuits and the output of voting circuit are connected to form error detection circuit, its effect is that the output valve with final output result and three objective circuits compares, essence is carried out XOR exactly one time, according to the result of computing, judging is that mistake has appearred in which module.
In addition, this IP kernel also comprises the RAM circuit of stored target truth table, participates in the operation of the genetic algorithm of software-hardware synergism.
2, realize the genetic algorithm of software-hardware synergism based on the MicroBlaze soft nucleus CPU;
By the genetic algorithm function of search is identical but the objective circuit that structure is different, the main part of this algorithm runs on the MicroBlaze soft nucleus CPU, adaptive value evaluation portion wherein need carry out online evaluation with the RAM circuit by means of the virtual reconfigurable circuit in the three mould isomery redundancy fault-tolerant IP kernels, calculates adaptive value then.
Algorithm steps is described below:
Step 1 produces the initialization population at random, and each individuality in the population is all for the configuration string of a circuit.
Step 2 is stored in the truth table of objective circuit among the RAM.
Step 3 downloads to virtual reconfigurable circuit with each individuality in the population and carries out online evaluation.
Step 3.1 is with each individuality, and promptly a configuration string writes virtual reconfigurable circuit.
After step 3.2 writes and finishes, at the input end of virtual reconfigurable circuit, the importation of the truth table of analog input objective circuit constantly.
Step 3.3 is carried out same exclusive disjunction with the output of the truth table of the objective circuit deposited among the output of virtual reconfigurable circuit and the RAM, once more the result is exported.
The number of " 1 " among the output result of step 3.4 calculating previous step.
Step 4 finds out whether the individuality that meets the demands is arranged after step 3 has been finished assessment to all individualities, promptly should the pairing final output result of individuality in the number of " 1 " equal the line number of objective circuit truth table.
If the individuality that step 5 does not meet the demands then needs to produce new population.Otherwise to the 6th step.
Step 5.1 is selected the optimum individual in the present population, directly enters population of future generation.
Step 5.2 with a certain position or some position of its configuration string of a certain probability change at random, is put into population of future generation with the optimum individual in the present population then.
Step 5.2 repeats 5.2 operation repeatedly, and number individual in population of new generation is identical with previous generation.
If step 6 has found the individuality that meets the demands, then carry out step 1 again, until finally having found three individualities that meet the demands, this algorithm stops.
3, software-hardware synergism is realized the initialization of three isomery objective circuits and later repair;
In previous step, by genetic algorithm, searched out three configuration strings, just can be configured it this moment to three virtual reconfigurable circuits.
Step 1 is written to three configuration strings respectively among three virtual reconfigurable circuits.
Step 2 runs on that software section stops on the MicroBlaze soft nucleus CPU.
The input end of three virtual reconfigurable circuits of step 3 has been connected to the pumping signal on the hardware, and this pumping signal is a bit of code of writing with hardware description language, and its effect is the importation that constantly produces the truth table of objective circuit.
The data that step 4 pumping signal produces are imported among the virtual reconfigurable circuit, and the result with computing exports by voting circuit then.
The output result of the error detection circuit of mentioning in step 5 method for supervising 1 if a certain position is for " 1 " then represent objective circuit on the pairing virtual reconfigurable circuit in this position among the error detection circuit output result, fault occurred.
Step 6 is when detecting after some circuit modules break down, to start software section automatically, the operational scheme that occurs the wrong enterprising row method 2 of virtual reconfigurable circuit at that piece, and only need find out a suitable configuration string again this moment, and that virtual reconfigurable circuit of makeing mistakes reshuffled, thereby realize the selfreparing of this module.
4, simulate wrong injection, the operation of recording geometry and debugging by hardware interrupts.
By the hardware pumping signal, in basic logic unit, inject a certain section special configurations string, to change the normal output result of this unit, be used for simulating certain node of virtual reconfigurable circuit mistake has taken place, and then the fault-tolerant flow process of observing system and system performance debugged.
The hardware pumping signal produces by button, after pressing the button, and configuration string of generation at random, and download in some logical blocks of virtual reconfigurable circuit.
Step 1 realizes the interruption IP kernel of button, and the definition of this IP kernel is as follows usually:
entity?ButtonFilter?is
generic(CLK_FREQ :?integer;
NUM_SWITCHES :?integer);
port?( clk :?in std_logic;
reset :?in std_logic;
buttonArray :?in std_logic_vector(NUM_SWITCHES-1?downto?0);
pressArray :?out std_logic_vector(NUM_SWITCHES-1?downto?0));
end?entity?ButtonFilter;
Here defined three buttons, formed a button groups, these three buttons are controlled three virtual reconfigurable circuits respectively, are used for that it is carried out mistake and inject.
Step 2 just produces the mistake of a certain type at random when when the next button, and type of error is respectively: normal 0, normal 1, constant, upset.The corresponding code of difference " " 10, " 11 ", " 00 ", " 01 ".
Step 3 is above error code, is injected into respectively on LUT at random of virtual reconfigurable circuit, is used for changing the output valve of this LUT, thereby influences the output valve of entire circuit.
Step 4 when some logical blocks are configured falsification become its internal state after, the output result of system just might change.At this moment, if fault has appearred in the objective circuit that error detection circuit detects on some virtual reconfigurable circuits, then change method 3 over to and carry out selfreparing.
The invention will be further described in conjunction with the accompanying drawings with specific embodiment below:
This example is to realize on XC2VP30 FPGA development board, uses the soft nuclear of MicroBlaze as processor, uses on the sheet internal memory as storer, with four bit parity check circuit as objective circuit.In addition, a kind of wrong mechanism of injecting is provided among the present invention, come contingent mistake in the simulating reality with this, with its at a time the people for being injected in the IP kernel, so that observe the fault-tolerant flow process and the effect of total system, therefore, the design of basic logic unit, the LUT mode that has adopted tape error to inject.
As shown in Figure 1, the concrete structure figure of a basic logic unit, a wrong injection module has been appended in the back, be used for total system is tested, the mode that mistake is injected is by one group of pumping signal of extra input, to simulate different type of errors, make some basic logic units make a mistake.The extra pumping signal of this group does not belong to the configuration string of objective circuit, does not participate in developing, and therefore do not increase the length of configuration string, and under default situations, pumping signal is " 00 ", does not change the correctness of basic logic unit, and being equal to does not have wrong the generation.
As shown in Figure 2, virtual reconfigurable circuit is to be constructed by the basic logic unit of 8 row, 4 row to form, and the input of each row logic unit comes from the output of its previous column logical block and the original input signal of system; The output of whole virtual reconfigurable circuit is to select certain several composition from the output valve of all basic logic units.To each virtual reconfigurable circuit, a final configuration string is all arranged, show the objective circuit that this virtual reconfigurable circuit is realized.To the configuration string, we define by a structure, and its definition mode is as follows:
typedef?struct
{
Xuint32?cellConfigs[NUM_CELLS];
Xuint32?outputSel0;
Xuint32?outputSel1;
Xuint32?fitness;
}?ArrayConfig;
Wherein, Xuint32 is 32 unsigned ints, cellConfigs[NUM_CELLS] be the array that has each basic logic unit configuration string, the value of NUM_CELLS is 32 herein; OutputSel0 and outputSel1 are the selection signal of circuit output node, and decision is made of the output node of final goal circuit which two node; Fitness has represented the adaptive value of this virtual reconfigurable circuit configuration string.
As shown in Figure 3, three mould isomery redundancy fault-tolerant system IP kernels are mainly by virtual reconfigurable circuit, voting circuit, and the RAM of error detection circuit and stored target circuit truth table forms.This IP kernel can with the software section collaborative work, also can be directly and other hardware logic cooperation.When system during in initialization, and system is when being in fault-tolerant repairing phase, this IP kernel and software section synthetic operation.Finish when three virtual reconfigurable circuits are initialised, and do not have under the wrong situation about injecting, or repaired under the situation about finishing in mistake, software section will be closed, then enter into the hardware internal operation stage.The purpose in this stage is to inject the condition that provides for the simulation of mistake, at this moment, the Input signal will constantly carry out the input of data, to encourage the normal operation of three fault-tolerant modules, voting circuit and error detection circuits, be injected on a certain module up to a certain mistake, simulate the generation of a certain class mistake, so that observe the fault-tolerant flow process and the effect of total system.
As shown in Figure 4, combinational logic circuit of the realization principle of voting circuit, expression formula is: OUT=AB+BC+AC.In three input signals of ABC, some making a mistake, promptly with two other input value when inequality, the value of OUT is still constant, not yet initial value, the just value that occupies the majority among the ABC.Therefore, can be constant all the time in the OUT value, promptly do not influence under the situation of system performance, realization is fault-tolerant to a certain error module, can start the repair procedure to this module simultaneously.
As shown in Figure 5, in system initialisation phase,, adopt three of genetic algorithm search function is identical but the configuration string of the objective circuit that structure is different by the mode of software-hardware synergism, and be configured among three virtual reconfigurable circuit structures, finish the initial work of whole tolerant system.At first, the truth table of objective circuit is write RAM, its effect is the calculating of carrying out individual fitness in evolutionary process, satisfies the needs of objective circuit up to adaptive value, has then found the configuration string of representing objective circuit.Repeat search procedure three times, then found three function is identical but objective circuit configuration string that structure is different.After finishing, software section is with out of service, and system switches to hardware components internal operation state.
As shown in Figure 6, in the System Fault Tolerance stage, entire circuit will be in the internal operation state of pure hardware, the Input input signal, with the importation of constantly importing in the truth table, be in running status to encourage whole fault-tolerant module, this moment, voting circuit and error detection circuit were all in normal work.Need wait until when a certain error condition occurs that system just can carry out fault-tolerant processing.Come mistake is simulated injection by three buttons among the present invention.What inject employing is the system break mode, because use is the MicroBlaze processor, so interrupt function is defined as:
void?setupInterrupts(void)
{
//?Register?Button?Interrupt?Handler
XIntc_RegisterHandler( XPAR_XPS_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_PLB_IFCE_FTSYSTEM_0_BUTTONIRQ_INTR,
(XInterruptHandler)buttonPressISR,?(void?*)0);
//?Enable?the?Interrupt?Controller
XIntc_mMasterEnable(XPAR_XPS_INTC_0_BASEADDR);
//?Set?Interrupt?Controller?Enable?for?the?buttons
XIntc_mEnableIntr(XPAR_XPS_INTC_0_BASEADDR,?XPAR_PLB_IFCE_FTSYSTEM_0_BUTTONIRQ_MASK);
//?Enable?Microblaze?Interrupts
microblaze_enable_interrupts();
}
When a certain circuit module is made mistakes, error detection circuit can detect the module of makeing mistakes, to begin to start software section then, virtual reconfigurable circuit together with the module place of makeing mistakes, carry out the search procedure of similar system initial phase once more, find a new configuration string, and system is configured, and then recover the correct function of that module make mistakes.Reparation finishes, and system software will stop once more, and total system is in the internal operation state once more.
As shown in Figure 7, the general structure of system mainly comprises PLBv46 bus and SPLB bus, and the PLBv46 bus is the public passage that processor and all external units carry out exchanges data, and each external unit is mounted on the PLBv46 bus by the SPLB bus respectively.In this example, be mounted with internal memory on the XPS BRAM sheet, XPS INTC interruption, these three IP kernels that system carries of UART Lite serial communication altogether, and FTBlock User Defined IP kernel, the i.e. IP kernel of three mould isomery redundancy fault-tolerants among the present invention.Each IP kernel all has independently start address and the offset address by system assignment.The register that defines is arranged in the IP kernel, be used for storing and processor between need the data that exchange.
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique; under the situation that does not break away from the spirit and scope of the present invention; can also make various conversion or modification, so all technical schemes that are equal to, all fall into protection scope of the present invention.
Claims (3)
1. three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware is characterized in that:
(1) IP kernel of realization three mould isomery redundancy fault-tolerants on FPGA, this step comprises:
By LUT, the concrete function that will realize by wiring connected mode between the configuration string decision logic unit and logical block;
When some configuration strings were configured to virtual reconfigurable circuit, this virtual reconfigurable circuit had been represented the objective circuit of some specific functions;
With three virtual reconfigurable circuit parallel connections, and its output terminal connected by voting circuit, thereby form three mould isomery redundancies;
Again the output of three objective circuits and the output of voting circuit are connected to form error detection circuit;
(2) based on the genetic algorithm of MicroBlaze soft nucleus CPU realization software-hardware synergism, this step comprises:
1. produce the initialization population at random, each individuality in the population is all for the configuration string of a circuit;
2. the truth table with objective circuit is stored among the RAM;
3. each individuality in the population is downloaded to virtual reconfigurable circuit and carry out online evaluation;
4. after 3. step has finished assessment to all individualities, find out whether the individuality that meets the demands is arranged, promptly should the pairing final output result of individuality in the number of " 1 " equal the line number of objective circuit truth table;
If the individuality that does not 5. meet the demands then needs to produce new population, otherwise to the 6. step;
If 6. found the individuality that meets the demands, then carry out step 1 again, until finally having found three individualities that meet the demands, finish;
(3) software-hardware synergism realizes that this step comprises to the initialization of three isomery objective circuits and later repair:
1. with three configuration strings, be written to respectively among three virtual reconfigurable circuits;
2. run on that software section stops on the MicroBlaze soft nucleus CPU;
3. the input end of three virtual reconfigurable circuits has been connected to the pumping signal on the hardware, and this pumping signal is a bit of code of writing with hardware description language, and its effect is the importation that constantly produces the truth table of objective circuit;
4. the data of pumping signal generation are imported among the virtual reconfigurable circuit, and the result with computing exports by voting circuit then;
If 5. a certain position fault occurred for " 1 " then represent objective circuit on the pairing virtual reconfigurable circuit in this position among the error detection circuit output result;
6. when detecting after some circuit modules break down, to start software section automatically, the operational scheme that occurs the wrong enterprising row method 2 of virtual reconfigurable circuit at that piece, and only need find out a suitable configuration string again this moment, and that virtual reconfigurable circuit of makeing mistakes reshuffled, thereby realize the selfreparing of this module;
(4) simulate wrong injection by hardware interrupts, the operation of recording geometry and debugging, this step comprises:
1. realize the interruption IP kernel of button;
2. when when the next button, just produce the mistake of a certain type at random, type of error is respectively: normal 0, normal 1, constant, upset;
3. with above error code, be injected into respectively on LUT at random of virtual reconfigurable circuit, be used for changing the output valve of this LUT, thereby influence the output valve of entire circuit;
4. after some logical blocks were configured falsification and have become its internal state, the output result of system just might change.
2. three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware according to claim 1 is characterized in that:
The substep of described step (2) 3. further comprises:
With each individuality, promptly a configuration string writes virtual reconfigurable circuit;
Write finish after, at the input end of virtual reconfigurable circuit, the importation of the truth table of analog input objective circuit constantly;
The output of the truth table of the objective circuit deposited among the output of virtual reconfigurable circuit and the RAM is carried out same exclusive disjunction, once more the result is exported;
The number of " 1 " among the output result of calculating previous step.
3. three mould isomery redundancy fault-tolerant methods based on LUT level evolution hardware according to claim 1 and 2 is characterized in that:
The substep of described step (2) 5. further comprises:
Optimum individual in the present population is selected, directly entered population of future generation;
With the optimum individual in the present population,, put into population of future generation then with a certain position or some position of its configuration string of a certain probability change at random;
The operation that previous step is rapid repeats repeatedly, and number individual in population of new generation is identical with previous generation.
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