CN108345250B - An Evolving Hardware Delay-Free Control Device - Google Patents

An Evolving Hardware Delay-Free Control Device Download PDF

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CN108345250B
CN108345250B CN201810189804.9A CN201810189804A CN108345250B CN 108345250 B CN108345250 B CN 108345250B CN 201810189804 A CN201810189804 A CN 201810189804A CN 108345250 B CN108345250 B CN 108345250B
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programmable logic
logic unit
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CN108345250A (en
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杨宪园
常玲玲
李志刚
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Henan University of Science and Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller

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Abstract

The invention discloses an evolution hardware non-delay control device, which comprises an embedded module (1) and a programmable logic unit (2), and is characterized in that: the embedded module (1) is connected with the programmable logic unit (2) and the switching module (3), the programmable logic unit (2) is connected with the switching module (3), and the switching module (3) is used for switching the output of the embedded module (1) and the programmable logic unit (2). The invention can switch the output of the programmable device to the signal output of the embedded module when the output of the programmable device is in an abnormal working state, thereby improving the stability of the system and realizing the delay-free control of the evolvable hardware.

Description

Evolvable hardware non-delay control device
Technical Field
The invention belongs to the technical field of evolution hardware control, and particularly relates to a control device for evolution hardware without delay.
Background
Evolution Hardware (evolution Hardware), EHW or E-Hard for short. The self-adaptive self-repairing hardware circuit can change the self structure according to the change of the environment like organisms so as to adapt to the living environment, and has the functions of self-organization, self-adaptation and self-repairing. At present, the implementation modes of evolving hardware mainly include two types: one is the external evolution (explicit EHW), also known as Off-line evolution; the other is the internal evolution (Intrasic EHW), also known as the On-line evolution. External evolution refers to modeling an electronic device through a Hardware Description Language (HDL), evaluating chromosomes generated by genetic algorithms on the model, and downloading corresponding chromosomes to a programmable logic device when a desired goal is achieved. Unlike external evolution, internal evolution is the actual downloading of each chromosome produced by each generation of the genetic algorithm into the programmable logic device and the direct evaluation of the output of each circuit structure generated.
Prior art 1, as filed under the number CN02809754.8, discloses a hardware design using an evolution algorithm, and fig. 1 shows the main steps in the EHW evolution cycle. An initial population of architectural bits encoded as chromosomes 10 is randomly or heuristically generated. They are then downloaded 12 into the FPGA 14 for fitness evaluation. To cut costs and save space, an EHW has only one set of FPGA hardware to evaluate fitness of each chromosome in turn. The fitness of an FPGA, generally equivalent to the fitness of its chromosomes, is estimated through the interaction of the FPGA with the environment 16. This fitness is then used to select parent chromosomes 18 for further replication and genetic manipulation. Crossover and mutation 20 is typically used to generate offspring chromosomes 22 from parents. These offspring then replace their parents according to some replacement strategy. Some replacement strategies may retain parents and discard their offspring. After the substitution step, a new generation of chromosomes is formed.
Prior art 2, having application number CN201110148507.8, discloses an evolutionary hardware implementation method based on a trend-oriented compact genetic algorithm, and an evolutionary hardware implementation method based on a trend-oriented compact genetic algorithm, the method comprising: 1) acquiring configuration parameters of an actual programmable logic device; 2) mapping the configuration parameters of the actual programmable logic device and forming a chromosome individual; 3) calculating the fitness value fitness of the current chromosome individual; 4) and judging whether the evolution is terminated according to the condition of the fitness value fitness, which is shown in detail in the attached figure 2.
Programmable devices are typically based on SRAM architecture, and because of the volatility of SRAM, configuration data must be streamed (Bitstream) into the programmable device each time it is powered up. In the existing evolving hardware device, before the programmable device is restarted after the configuration data stream of the programmable device is updated, the output of the programmable device is in an abnormal working state, and particularly in a real-time control or high-speed monitoring system, the defect cannot be tolerated. In addition, in the prior art, a computer is usually adopted to run a genetic algorithm or generate a data stream to a configurable unit, so that the application range of an evolved hardware system is limited, and the method cannot be applied to an actual control system.
Disclosure of Invention
Therefore, in order to overcome the technical problems, the invention provides an evolutionary hardware delay-free control device, which has the advantages of no delay in system control, wide application field and the like, and can be popularized and applied in the fields of automatic control, fault-tolerant systems, mode identification and artificial intelligence, robots, aviation detection and the like.
In order to achieve the purpose, the invention provides the following technical scheme:
an evolution hardware non-delay control device comprises an embedded module, a programmable logic unit and a switching module;
the embedded module is connected with the programmable logic unit and the switching module, and the programmable logic unit is connected with the switching unit;
the embedded module is provided with an evolution algorithm module, a parameter configuration module and a signal pre-output module, wherein the evolution algorithm module is used for evolving hardware configuration parameters according to environmental changes, and the parameter configuration module is used for generating data streams for configuring the programmable unit according to the hardware configuration parameters; the signal pre-output module evolves embedded system output according to an evolution algorithm in the evolution algorithm module, and the embedded system output is connected with the switching module and can be used for temporarily replacing the output of the programmable logic unit;
the switching module is used for switching the output of the embedded module and the programmable logic unit.
Preferably, the embedded module is an ARM system module, and can be used for executing an evolution algorithm.
Preferably, the evolutionary algorithm module may run one or more of a standard genetic algorithm, a trend-based compact genetic algorithm, a co-evolutionary genetic algorithm, or a collaborative co-evolutionary genetic algorithm.
Preferably, the programmable logic unit adopts an FPGA, and the FPGA adopts an Altera Cyclone series chip. And a parameter configuration module in the embedded module is used for simulating the configuration time sequence of the FPGA to configure the FPGA, and the FPGA device is configured in a Passive Serial (PS) mode.
The invention also discloses a delay-free control method for evolving hardware, which can complete the delay-free control of system output by combining the device, and concretely comprises the following steps:
the embedded module runs an evolution algorithm, and when the external environment of the system changes, the evolution algorithm evolves a new optimal solution according to the change of the external environment;
the embedded module generates hardware configuration parameters and embedded system output according to the evolved new optimal solution;
the embedded module controls the switching module to switch the output of the original programmable logic unit into the output of the embedded system;
the parameter configuration module in the embedded module simulates the configuration time sequence of the programmable logic unit, configures the hardware configuration parameters into the programmable logic unit, restarts the programmable logic unit after receiving a signal that the programmable logic unit is successfully configured, and notifies the embedded module after the programmable logic unit is started;
after the embedded module obtains the starting completion signal sent by the programmable logic unit, the embedded module controls the switching module to switch the output of the embedded system back to the output of the programmable logic unit, and the embedded module continues to run the evolution algorithm.
Preferably, the evolutionary algorithm may be one or more of a standard genetic algorithm, a trend-type compact genetic algorithm, a co-evolutionary genetic algorithm, or a cooperative co-evolutionary genetic algorithm.
Preferably, the programmable logic unit is an FPGA, and the embedded module is an ARM system module.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the embedded module is used for operating the evolution algorithm to output signals in advance before the programmable logic unit is configured, so that the output of the programmable device can be switched to the signal output of the embedded module when the output is in an abnormal working state, the system stability is improved, and the delay-free control of the evolution hardware is realized;
2. the invention uses the embedded module to run the evolution algorithm, so that the application range of the hardware evolution device is wider.
Drawings
Fig. 1 is a diagram of main steps in an EHW evolution cycle in prior art 1;
FIG. 2 is a flow diagram of prior art 2 evolution hardware implementation based on a trend-based compact genetic algorithm;
FIG. 3 is a block diagram of an evolving hardware system of embodiment 1;
FIG. 4 is a block diagram of an evolved hardware system in embodiment 2;
FIG. 5 is a block diagram of an evolved hardware system in embodiment 3;
FIG. 6 shows the PS configuration mode of the FPGA.
In fig. 1-6: the system comprises an embedded module 1, a programmable logic unit 2, a switching unit 3, an evolution algorithm module 4, a parameter configuration module 5, a signal pre-output module 6 and a sensor module 7.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 3, an evolved hardware delay-free control apparatus includes an embedded module 1, a programmable logic unit 2, and a switching module 3;
the embedded module 1 is connected with the programmable logic unit 2 and the switching module 3, and the programmable logic unit 2 is connected with the switching unit 3;
the embedded module 1 is provided with an evolution algorithm module 4, a parameter configuration module 5 and a signal pre-output module 6, wherein the evolution algorithm module 4 is used for evolving a hardware configuration parameter according to an environmental change, and the parameter configuration module 5 is used for generating a data stream for configuring the programmable unit according to the hardware configuration parameter; the signal pre-output module 6 evolves an embedded system output according to an evolution algorithm in the evolution algorithm module 4, and the embedded system output is connected with the switching module 3 and can be used for temporarily replacing the output of the programmable logic unit 2;
the switching module 3 is used for switching the outputs of the embedded module 1 and the programmable logic unit 2. The embedded module 1 is an ARM system module and can be used for executing an evolution algorithm. The evolution algorithm module 4 can run one or more of a standard genetic algorithm, a trend compact genetic algorithm, a co-evolution genetic algorithm or a cooperative co-evolution genetic algorithm.
The programmable logic unit 2 adopts an FPGA, and the FPGA adopts an Altera Cyclone series chip. The parameter configuration module 5 in the embedded module 1 is used for simulating the configuration timing sequence of the FPGA to configure the FPGA, and the FPGA device is configured in a Passive Serial (PS) mode, as shown in fig. 6, and is a common interface circuit configured in a PS mode.
The invention also discloses a delay-free control method for evolving hardware, which can complete the delay-free control of system output by combining the device, and concretely comprises the following steps:
the embedded module 1 runs an evolution algorithm, and when the external environment of the system changes, the evolution algorithm evolves a new optimal solution according to the change of the external environment;
the embedded module 1 generates hardware configuration parameters and embedded system output according to the evolved new optimal solution;
the embedded module 1 controls the switching module 3 to switch the output of the original programmable logic unit 2 into the output of the embedded system;
the parameter configuration module 5 in the embedded module 1 simulates the configuration time sequence of the programmable logic unit 2, configures the hardware configuration parameters into the programmable logic unit 2, restarts the programmable logic unit 2 after receiving a signal that the programmable logic unit 2 is successfully configured, and notifies the embedded module 1 after the programmable logic unit 2 is started;
after the embedded module 1 obtains the start completion signal sent by the programmable logic unit 2, the switching module 3 is controlled to switch the output of the embedded system back to the output of the programmable logic unit 2, and the embedded module 1 continues to run the evolution algorithm.
Example 2
Referring to fig. 4, an evolved hardware delay-free control apparatus includes an embedded module 1, a programmable logic unit 2, and a switching module 3;
the embedded module 1 is connected with the programmable logic unit 2 and the switching module 3, and the programmable logic unit 2 is connected with the switching unit 3; the embedded module 1 is also connected with a sensor module 7, the sensor module 7 is used for collecting external environment parameters, and an evolution algorithm operated in the evolution algorithm module 4 carries out evolution according to the external environment parameters and signals fed back by control output;
the embedded module 1 is provided with an evolution algorithm module 4, a parameter configuration module 5 and a signal pre-output module 6, wherein the evolution algorithm module 4 is used for evolving a hardware configuration parameter according to an environmental change, and the parameter configuration module 5 is used for generating a data stream for configuring the programmable unit according to the hardware configuration parameter; the signal pre-output module 6 evolves an embedded system output according to an evolution algorithm in the evolution algorithm module 4, and the embedded system output is connected with the switching module 3 and can be used for temporarily replacing the output of the programmable logic unit 2;
the switching module 3 is used for switching the outputs of the embedded module 1 and the programmable logic unit 2. The embedded module 1 is an ARM system module and can be used for executing an evolution algorithm. The evolution algorithm module 4 can run one or more of a standard genetic algorithm, a trend compact genetic algorithm, a co-evolution genetic algorithm or a cooperative co-evolution genetic algorithm.
The programmable logic unit 2 adopts an FPGA, and the FPGA adopts an Altera Cyclone series chip. The parameter configuration module 5 in the embedded module 1 is used for simulating the configuration time sequence of the FPGA to configure the FPGA, and the FPGA device is configured in a Passive Serial (PS) mode.
The invention also discloses a delay-free control method for evolving hardware, which can complete the delay-free control of system output by combining the device, and concretely comprises the following steps:
the embedded module 1 runs an evolution algorithm, and when the external environment collected by the system changes, the evolution algorithm evolves a new optimal solution according to the external environment change and a signal fed back by the system control output;
the embedded module 1 generates hardware configuration parameters and embedded system output according to the evolved new optimal solution;
the embedded module 1 controls the switching module 3 to switch the output of the original programmable logic unit 2 into the output of the embedded system;
the parameter configuration module 5 in the embedded module 1 simulates the configuration time sequence of the programmable logic unit 2, configures the hardware configuration parameters into the programmable logic unit 2, restarts the programmable logic unit 2 after receiving a signal that the programmable logic unit 2 is successfully configured, and notifies the embedded module 1 after the programmable logic unit 2 is started;
after the embedded module 1 obtains the start completion signal sent by the programmable logic unit 2, the switching module 3 is controlled to switch the output of the embedded system back to the output of the programmable logic unit 2, and the embedded module 1 continues to run the evolution algorithm.
Example 3
Referring to fig. 5, an evolved hardware delay-free control device includes an embedded module 1, a programmable logic unit 2, a switching module 3, and a signal pre-output module 6;
the embedded module 1 is connected with the programmable logic unit 2 and the switching module 3, the programmable logic unit 2 is connected with the switching unit 3, and the signal pre-output module 6 is positioned between the switching module 3 and the embedded module 1 and is respectively connected with the switching module 3 and the embedded module 1; the embedded module 1 is also connected with a sensor module 7, the sensor module 7 is used for collecting external environment parameters, and an evolution algorithm operated in the evolution algorithm module 4 carries out evolution according to the external environment parameters and signals fed back by control output;
the embedded module 1 is provided with an evolution algorithm module 4 and a parameter configuration module 5, wherein the evolution algorithm module 4 is used for evolving hardware configuration parameters according to environmental changes, and the parameter configuration module 5 is used for generating data streams for configuring the programmable unit according to the hardware configuration parameters; the signal pre-output module 6 evolves an embedded system output according to an evolution algorithm in the evolution algorithm module 4, and the embedded system output is connected with the switching module 3 and can be used for temporarily replacing the output of the programmable logic unit 2;
the switching module 3 is used for switching the outputs of the embedded module 1 and the programmable logic unit 2. The embedded module 1 is an ARM system module and can be used for executing an evolution algorithm. The evolution algorithm module 4 can run one or more of a standard genetic algorithm, a trend compact genetic algorithm, a co-evolution genetic algorithm or a cooperative co-evolution genetic algorithm.
The programmable logic unit 2 adopts an FPGA, and the FPGA adopts an Altera Cyclone series chip. The parameter configuration module 5 in the embedded module 1 is used for simulating the configuration time sequence of the FPGA to configure the FPGA, and the FPGA device is configured in a Passive Serial (PS) mode.
The invention also discloses a delay-free control method for evolving hardware, which can complete the delay-free control of system output by combining the device, and concretely comprises the following steps:
the embedded module 1 runs an evolution algorithm, and when the external environment collected by the system changes, the evolution algorithm evolves a new optimal solution according to the external environment change and a signal fed back by the system control output;
the embedded module 1 generates hardware configuration parameters and embedded system output according to the evolved new optimal solution;
the embedded module 1 controls the switching module 3 to switch the output of the original programmable logic unit 2 into the output of the embedded system;
the parameter configuration module 5 in the embedded module 1 simulates the configuration time sequence of the programmable logic unit 2, configures the hardware configuration parameters into the programmable logic unit 2, restarts the programmable logic unit 2 after receiving a signal that the programmable logic unit 2 is successfully configured, and notifies the embedded module 1 after the programmable logic unit 2 is started;
after the embedded module 1 obtains the start completion signal sent by the programmable logic unit 2, the switching module 3 is controlled to switch the output of the embedded system back to the output of the programmable logic unit 2, and the embedded module 1 continues to run the evolution algorithm.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (3)

1.一种演化硬件无延迟控制装置，所述的控制装置包括嵌入式模块（1）、可编程逻辑单元（2），其特征在于：所述的控制装置还包括切换模块（3），所述嵌入式模块（1）与可编程逻辑单元（2）以及切换模块（3）连接，所述可编程逻辑单元（2）与切换模块（3）连接，切换模块（3）用于切换嵌入式模块（1）和可编程逻辑单元（2）的输出；1. An evolutionary hardware delay-free control device, the control device comprising an embedded module (1) and a programmable logic unit (2), characterized in that: the control device further comprises a switching module (3), the The embedded module (1) is connected to the programmable logic unit (2) and the switching module (3), the programmable logic unit (2) is connected to the switching module (3), and the switching module (3) is used to switch the embedded module (3). the outputs of the module (1) and the programmable logic unit (2); 所述嵌入式模块（1）中具有演化算法模块（4）、参数配置模块（5）以及信号预输出模块（6），所述演化算法模块（4）用于根据环境变化使得演化算法进化出硬件配置参数，所述参数配置模块（5）用于根据所述硬件配置参数产生用于配置可编程逻辑单元（2）的数据流；所述信号预输出模块（6）根据演化算法模块（4）中的演化算法进化出嵌入式模块输出，所述嵌入式模块与切换模块（3）连接，用于暂时替换所述可编程逻辑单元（2）的输出；The embedded module (1) has an evolutionary algorithm module (4), a parameter configuration module (5) and a signal pre-output module (6), and the evolutionary algorithm module (4) is used to make the evolutionary algorithm evolve according to environmental changes. hardware configuration parameters, the parameter configuration module (5) is configured to generate a data stream for configuring the programmable logic unit (2) according to the hardware configuration parameters; the signal pre-output module (6) is configured according to the evolutionary algorithm module (4) The evolution algorithm in ) evolves the embedded module output, the embedded module is connected with the switching module (3), and is used to temporarily replace the output of the programmable logic unit (2); 所述嵌入式模块（1）控制切换模块（3）将可编程逻辑单元（2）的输出切换为所述嵌入式模块输出；The embedded module (1) controls the switching module (3) to switch the output of the programmable logic unit (2) to the output of the embedded module; 所述参数配置模块（5）模拟可编程逻辑单元（2）的配置时序，并将硬件配置参数配置到可编程逻辑单元（2）中，在接收到可编程逻辑单元（2）配置成功的信号后，重启可编程逻辑单元（2），在可编程逻辑单元（2）启动完成后，通知嵌入式模块（1）；The parameter configuration module (5) simulates the configuration sequence of the programmable logic unit (2), and configures the hardware configuration parameters into the programmable logic unit (2), and receives a signal that the programmable logic unit (2) is successfully configured After that, restart the programmable logic unit (2), and notify the embedded module (1) after the programmable logic unit (2) is started up; 所述嵌入式模块（1）在得到可编程逻辑单元（2）发来的启动完成信号后，控制切换模块（3）将嵌入式模块输出切换回可编程逻辑单元的输出。The embedded module (1) controls the switching module (3) to switch the output of the embedded module back to the output of the programmable logic unit after obtaining the start-up completion signal sent by the programmable logic unit (2). 2.根据权利要求1所述的一种演化硬件无延迟控制装置，其特征在于：所述嵌入式模块（1）为ARM系统模块，可用于执行演化算法。2 . The device for controlling evolutionary hardware without delay according to claim 1 , wherein the embedded module ( 1 ) is an ARM system module, which can be used to execute an evolutionary algorithm. 3 . 3.根据权利要求1所述的一种演化硬件无延迟控制装置，其特征在于：所述演化算法为标准遗传算法、趋向型紧凑遗传算法、协同进化遗传算法中的一种或几种。3 . An evolutionary hardware-free delay control device according to claim 1 , wherein the evolutionary algorithm is one or more of a standard genetic algorithm, a trend-type compact genetic algorithm, and a co-evolutionary genetic algorithm. 4 .
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1529873A (en) * 2001-03-15 2004-09-15 �����Ӣ��֪ʶ��Ȩ���޹�˾ Hardware Design Using Evolutionary Algorithms
CN101609443A (en) * 2009-07-31 2009-12-23 中国人民解放军总参谋部第六十一研究所 Evolvable hardware controller and control method thereof
CN102135928A (en) * 2011-03-30 2011-07-27 武汉大学 Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware
US7991712B1 (en) * 2003-08-20 2011-08-02 Xilinx, Inc. Consensus as an evaluation function for evolvable hardware
CN102156408A (en) * 2011-04-13 2011-08-17 武汉大学 System and method for tracking and controlling maximum power point in dynamically self-adaptive evolvement process
CN102254225A (en) * 2011-06-03 2011-11-23 中国科学院西安光学精密机械研究所 Evolutionary Hardware Implementation Method Based on Tendency-Type Compact Genetic Algorithm
CN107145944A (en) * 2017-03-29 2017-09-08 浙江大学 Genetic Algorithm and System Based on FPGA Efficient Training

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8041654B2 (en) * 2007-06-01 2011-10-18 Neal Solomon System for hybridized efficient genetic algorithms to solve bi-objective optimization problems with application to network computing
US9305257B2 (en) * 2013-05-20 2016-04-05 International Business Machines Corporation Adaptive cataclysms in genetic algorithms

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1529873A (en) * 2001-03-15 2004-09-15 �����Ӣ��֪ʶ��Ȩ���޹�˾ Hardware Design Using Evolutionary Algorithms
US7991712B1 (en) * 2003-08-20 2011-08-02 Xilinx, Inc. Consensus as an evaluation function for evolvable hardware
CN101609443A (en) * 2009-07-31 2009-12-23 中国人民解放军总参谋部第六十一研究所 Evolvable hardware controller and control method thereof
CN102135928A (en) * 2011-03-30 2011-07-27 武汉大学 Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware
CN102156408A (en) * 2011-04-13 2011-08-17 武汉大学 System and method for tracking and controlling maximum power point in dynamically self-adaptive evolvement process
CN102254225A (en) * 2011-06-03 2011-11-23 中国科学院西安光学精密机械研究所 Evolutionary Hardware Implementation Method Based on Tendency-Type Compact Genetic Algorithm
CN107145944A (en) * 2017-03-29 2017-09-08 浙江大学 Genetic Algorithm and System Based on FPGA Efficient Training

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
动态可重构计算及演化硬件的研究与应用;魏云龙;《中国优秀硕士学位论文全文数据库（电子期刊）信息科技辑》;20050615(第2期);全文 *
自适应演化硬件及其容错技术研究;朱继祥;《中国博士学位论文全文数据库（电子期刊）信息科技辑》;20150515(第5期);全文 *

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