CN114647541A - Circuit self-repairing method based on improved evolution hardware - Google Patents
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Abstract
The invention discloses a circuit self-repairing method based on improved evolution hardware, which adopts the evolution hardware to realize a self-repairing circuit; and a compensation circuit is additionally arranged on the circuit system to repair the error output, the target output and the error output are subjected to XOR operation by utilizing the characteristic of reverse calculation of XOR operation to obtain a truth table of the compensation system, and the compensation system is realized and then subjected to XOR operation to complete the function of repairing the error output. The invention uses the self-repairing circuit of the evolving hardware to repair the error part, thereby reducing the circuit resource and improving the reliability.
Description
Technical Field
The invention belongs to the technical field of reliability embedded system design, and particularly relates to a circuit self-repairing method based on improved evolvable hardware.
Background
For application scenes of aviation, aerospace, navigation, weaponry and the like, the operation of the circuit is difficult to be manually intervened. The circuit needs the self-repairing ability once the circuit is out of order. The traditional restoration method adopts triple modular redundancy backup, and directly switches to a brand new circuit when a fault occurs; this sub-method, while effective, may use too much circuit resources because a minor error has initiated the entire backup system.
Due to the characteristics of application scenes such as aviation, aerospace, navigation, weaponry and the like, all possible error information cannot be manually input in advance. The self-evolution characteristic of the evolution hardware perfectly fits the application scene, only a truth table of the evolution hardware needs to be given, and the evolution hardware utilizes a genetic algorithm to optimize and find the configuration information of the evolution circuit of the target so as to complete the evolution of the circuit. The evolvable hardware characteristic can well realize the compensation system, and different compensation systems are evolved according to different errors to repair.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a circuit self-repairing method based on improved evolvable hardware, which utilizes the improved evolvable hardware to realize the self-repairing circuit and improve the evolvable speed of the evolvable hardware.
The invention adopts the following technical scheme:
a circuit self-repairing method based on improved evolution hardware is characterized by comprising the following steps:
s1, when the circuit is in fault, carrying out bit XOR operation on the error output column of the fault circuit and the output column in the truth table of the correct circuit, and when the return value is 1, determining a repair section for the fault circuit; injecting an input column of a correct circuit truth table into a fault circuit to obtain an error output column;
s2, the compensation system respectively carries out XOR calculation according to the real output column in the correct circuit truth table of the step S1 and the error output column of the fault circuit to obtain a target output column of the evolution hardware;
s3, after the target output column of the evolved hardware in the step S2 is inverted, bit XOR calculation is respectively carried out on the target output column of the evolved hardware and the target output column of the evolved hardware stored in the static configuration library, then each bit of the calculation result is added to obtain a sum value, and the sum value is used as the similarity value of the evolved hardware stored in the target evolved hardware and the static configuration library; taking the chromosome corresponding to the maximum value in the plurality of sum values in the static configuration library as a high-similarity individual chromosome;
s4, dividing the evolvable hardware which is not evolved into a plurality of blocks by using a block evolution mechanism, and dividing a target output column and a target input column of the evolvable hardware according to the same number of blocks according to the number of the divided blocks;
s5, respectively transmitting the evolution hardware target input column and the evolution hardware target output column which are divided in the step S4 and the high-similarity individual chromosomes obtained in the step S3 into non-evolution hardware which is divided into corresponding blocks, realizing a self-adaptive genetic algorithm of the self-adaptive evolution hardware in an ARM (advanced RISC machine) computing core of the evolution hardware, and completing evolution of the non-evolution hardware;
and S6, performing exclusive OR operation by using the evolved hardware and fault circuit corresponding error bit in the step S5 to complete repair.
Specifically, in step S5, the evolving hardware includes an FPGA logic array and an ARM computing core, and a VRC virtual reconfigurable circuit is constructed in the FPGA logic array; configuring a VRC virtual reconfigurable circuit by utilizing a chromosome, inputting the configured VRC virtual reconfigurable circuit into an evolving hardware target input column to generate an output column, comparing hamming distances of the output column and the evolving hardware target output column, and summing comparison values to serve as fitness values of corresponding chromosomes; and programming in an ARM computing core to realize a genetic method.
Furthermore, the VRC virtual reconfigurable circuit comprises input nodes, PE nodes and output nodes, wherein the PE nodes are arranged in a matrix form, the link degree L is set, and the middle PE node in the same column is connected with the front L-1 column;
the PE node comprises two input circuits and an output circuit and has a unique number; the two input circuits are respectively connected with an output circuit for selecting the PE node by using a multi-path selector, and the number of the selected PE node is used as the gene position of the PE node;
selecting a logic operation for two input values selected by two input circuits by using a multiplexer in each PE node, and using the selected logic operation number as the gene position of the PE node; taking the serial numbers and the logic calculation serial numbers of the two input values PE nodes selected by the two input circuits as the genome of the PE node;
the output node of the VRC virtual reconfigurable circuit uses a multiplexer to select the output of a PE node as the input, and the number of the selected PE node is used as the genome of the output node;
the genomes of all PE nodes and the genomes of the output nodes jointly form a chromosome of the VRC virtual reconfigurable circuit.
Furthermore, a plurality of input signals exist in the PE node, enter a first multiplexer to select a first input signal, and the first input signal is a gene position 1 corresponding to the serial number of the PE node; a plurality of input signals enter a second multiplexer to select a second input signal, and the second input signal is a gene position 2 corresponding to the serial number of the PE node; the PE node saves a function table, and the function table comprises various one-bit logical operations and has corresponding numbers; selecting a function as an operation function of the PE node, and selecting a signal as a gene position 3 corresponding to the PE node; and carrying out operation on the two selected input signals by using the selected logic operation to obtain PE node output.
Further, the hamming distance comparison specifically includes:
inputting the configured VRC virtual reconfigurable circuit into a target input column, inverting the obtained output column, performing exclusive OR calculation on the inverted output column and a corresponding evolved hardware target output column respectively, and summing each bit to obtain a Hamming distance; and summing all the Hamming distances to obtain the fitness value of the chromosome.
Further, the method for realizing the inheritance in the ARM computing core specifically comprises the following steps:
s501, taking the high-similarity individual chromosomes matched in the static configuration library as an initial individual, and then randomly generating m-1 individuals; creating a roulette selection function fun _ roulette (m, n) according to a roulette method, the function being to input fitness of m individuals, selecting n individuals according to the roulette method, creating a random (k) function, the function being to generate k random numbers Ri;
s502, an ARM computing core is utilized to realize a fitness computing module, fitness values of m individuals are computed and stored, a genetic algorithm is skipped out after the fitness function output condition is triggered, and a target circuit is obtained after evolution is finished; simultaneously calculating a population diversity parameter delta;
s503, judging whether the maximum fitness of the m individuals is equal to or greater than the maximum fitness value; if the value is equal to or greater than the maximum fitness value, the evolution is exited, the evolution is completed, otherwise, the step S504 is entered;
s504, setting a self-adaptive exchange probability Pc, when a population diversity parameter delta is greater than a diversity comparison value a, Pc 1.3 to increase, selecting n1 individuals from m individuals in the step S502 as crossed chromosomes by using a roulette selection function fun _ roulette (m, n1), generating k random numbers by using a random generation function random (k) according to a total gene digit k of the chromosomes, pairing n1 individuals in pairs, and exchanging the ith gene digit when the ith random number is greater than the self-adaptive exchange probability Pc;
s505, setting a self-adaptive variation probability Pm, when a diversity parameter delta is greater than a diversity comparison value a, Pm 1.1, increasing, selecting n2 individuals from m individuals in the step S502 as chromosomes by using a roulette selection function fun _ roulette (m, n2), calculating the number w of the gene positions needing to be varied according to the total number k of the gene positions of the chromosomes multiplied by Pm, generating w random numbers by using a random generation function random (w), multiplying the w random numbers by the number k of the gene positions to obtain the number of the gene positions needing to be varied, and randomly changing the gene positions needing to be varied into a gene value in a designated range;
s506, obtaining n1 crossover filial generations from the step S504 by using an epoch-spanning elite algorithm, obtaining n2 variant filial generations from the step S505, respectively calculating fitness values, obtaining m parent fitness values from the step S502, and selecting m individuals from m + n1+ n2 individuals by using a function fun _ roulette (m + n1+ n2, m);
and S507, obtaining m individuals from the step S506, entering the step S502, jumping out of the genetic algorithm after the fitness function output condition is triggered, and obtaining a target circuit after evolution is finished.
Further, in step S502, the diversity parameter δ is specifically:
wherein favg is the average value of the m individual fitness values, fmax is the maximum value of the m individual fitness values, and fmin is the minimum value of the m individual fitness values.
Further, in step S504, the adaptive swap probability Pc specifically includes:
wherein a is a diversity comparison value, and δ is a diversity parameter.
Further, in step S504, the gene exchange is specifically:
wherein Ri is a random number.
Further, in step S505, the mutation probability Pm is automatically changed as follows:
wherein a is a diversity comparison value, and delta is a diversity parameter;
randomly transforming the jth gene locus into a value in a designated range, wherein the j value is specifically as follows:
wherein Ri is a random number.
Compared with the prior art, the invention has at least the following beneficial effects:
the circuit self-repairing method based on the improved evolution hardware is different from the traditional self-repairing circuit design method. The self-repairing function of the circuit is realized by adopting a method of evolving hardware, and various logic errors can be self-repaired under the condition of using less circuit resources. The traditional circuit uses a triple-modular redundancy backup and repair circuit, and the whole backup circuit can be started when a tiny logic error occurs in the circuit. The self-repairing circuit using the evolving hardware only repairs the error part, thereby greatly reducing circuit resources and improving reliability.
Further, for the implementation of the evolution hardware, a VRC virtual reconfigurable circuit is established on the bottom layer by utilizing the FPGA, and errors of different circuits are correspondingly repaired by means of the programmable characteristic of the FPGA. A genetic algorithm is realized in an ARM core of the evolution hardware, the evolution speed is increased, and the evolution function of the circuit is better completed.
Furthermore, a construction mode of a VRC virtual reconfigurable circuit is used in a reconfigurable part of the FPGA, and the reconfigurable characteristic of the circuit is completed under the condition that the bottom logic of the FPGA is not required to be known. And the logical programming language is used for logical abstraction, the bottom layer configuration bit stream is not specifically manipulated, and the reconstruction characteristic can be better realized.
Furthermore, the VRC virtual reconfigurable circuit is realized by a matrix constructed by a plurality of PE nodes, and the PE nodes are two-input one-output logic circuits. The PE node selects two input signals for a plurality of input signals by using two multiplexers, and then selects two input logic functions by using one multiplexer. So that the logic circuit information of each PE node can be expressed by only the selection signals of the three multiplexers. The number of the genome expressing the circuit chromosome information of the whole VRC is greatly reduced, and the evolution speed of the genetic algorithm is improved.
Furthermore, an important parameter for evaluating whether the chromosome information meets the evolution requirement in the genetic algorithm is a fitness value, and the fitness value is realized by a fitness function. Due to the implementation as a logic circuit, the output result of 0/1 for the target circuit constitutes a string code. Therefore, the design of the fitness function adopts the Hamming distance between the output of the evolution hardware and the target output, and the similarity degree of the 0/1 serial codes of the Hamming distance and the target output represents the fitness value of the evolution hardware after the evolution.
Furthermore, a genetic algorithm is realized in the ARM as a target circuit optimization algorithm. Because the circuit is 0/1 logic function, gradient optimization can not be carried out, and the genetic algorithm carries out similarity optimization by using the fitness value under the condition of not using the gradient, thereby having good fit for the characteristics of the evolution hardware.
Furthermore, for genetic algorithms, the characteristics of being premature and easy to enter a local optimal solution are provided, because populations in the genetic algorithms are rapidly similar after several rounds of evolution, and the diversity is poor. Therefore, the diversity parameter delta is introduced to evaluate the similarity degree of the population, and the parameter increase indicates that the population similarity degree is higher and the diversity is poorer, so that the method can be adjusted in the subsequent evolution.
Furthermore, one important parameter influencing the diversity of the population is the exchange probability Pc; when the population diversity decreases, the crossover probability Pc can be increased, increasing the population diversity. However, the population diversity is too large due to the too large exchange probability Pc, and the speed for searching the optimal solution is too slow; and (4) utilizing the population diversity parameter delta to construct an interval to complete the self-adaptive exchange probability Pc, and carrying out dynamic adjustment.
Further, random genome swapping was used for specific genome swaps. Realizing that k values are located in random numbers of 0-1 for k genome exchanges, and carrying out gene locus exchange when the random number is greater than Pc, otherwise, keeping the gene locus unchanged.
Furthermore, one important parameter affecting population diversity is the mutation probability Pm. When the population diversity is reduced, the crossover variation Pm can be improved, so that the population diversity is increased. However, the excessive variation probability Pm causes the excessive population diversity and the too slow speed of searching the optimal solution. And (4) constructing an interval by using the population diversity parameter delta to finish the self-adaptive variation probability Pm, and dynamically adjusting.
In summary, the present invention utilizes improved evolving hardware to implement self-healing circuits. The traditional evolution hardware is improved, so that the evolution speed of the evolution hardware is improved.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a block diagram of the overall architecture of the present invention;
FIG. 2 is a flow chart of the present invention;
FIG. 3 is a comparison of static configuration libraries in accordance with the present invention;
FIG. 4 is a block evolution hardware diagram of the present invention;
FIG. 5 is a diagram of an evolved circuit of the present invention;
FIG. 6 is a diagram of a PE module implementation of the present invention;
FIG. 7 is a diagram of a VRC virtual reconfigurable circuit implementation of the present invention;
FIG. 8 is a flow chart of the genetic algorithm of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Various structural schematics according to the disclosed embodiments of the invention are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, according to actual needs.
The invention provides a circuit self-repairing method based on improved evolution hardware, which adopts the evolution hardware to realize a self-repairing circuit; the compensation mechanism is a self-repairing circuit realization principle, and a compensation circuit is additionally arranged on a circuit system so as to repair error output. The principle of the compensation system is that the truth table of the compensation system is obtained by performing XOR operation on the target output and the error output by utilizing the property of the inverse calculation of the XOR operation. After the compensation system is realized, the repair function of error output is completed by utilizing XOR operation.
Referring to fig. 1 and fig. 2, a circuit self-repair method based on improved evolved hardware according to the present invention includes the following steps:
s1, when the circuit is in fault, carrying out bit XOR operation on the error output column of the fault circuit and the output column in the truth table of the correct circuit, and when the return value is 1, determining a repair section for the fault circuit; injecting an input column of a correct circuit truth table into a fault circuit to obtain an error output column, and transmitting the correct circuit truth table and the error output column of the fault circuit to a compensation system;
s2, utilizing a compensation system principle mechanism, and respectively carrying out XOR calculation by the compensation system according to the real output column and the fault circuit error output column in the correct circuit truth table of the step S1 to obtain a target output column of the evolvable hardware;
s3, matching the target output column of the evolution hardware with the evolution hardware output column stored in the static configuration library, wherein a Hamming distance is used as a comparison basis between the target output column of the evolution hardware and the evolution hardware output column;
referring to fig. 3, after the target output columns of the evolved hardware in step S2 are inverted, bit xor calculation is performed on the inverted target output columns of the evolved hardware and the target output columns of the evolved hardware stored in the static configuration library (the static configuration library stores the chromosome information of the evolved hardware and the corresponding evolved hardware output), and then each bit of the calculation result is added; the sum is a similarity value of the target evolution hardware and one evolution hardware stored in a static configuration library; the chromosome corresponding to the maximum value in the plurality of sum values in the static configuration library is taken as the high-similarity individual chromosome;
s4, dividing the evolvable hardware which is not evolved into a plurality of blocks by using a block evolution mechanism, and dividing a target output column and a target input column of the evolvable hardware according to the same number of blocks according to the number of the divided blocks;
s5, respectively transmitting the evolution hardware target input column divided in the step S4, the evolution hardware target output column and the high-similarity individual chromosomes obtained in the step S3 into non-evolution hardware which is also divided into corresponding blocks, realizing a self-adaptive genetic algorithm of the self-adaptive evolution hardware in an ARM core of the evolution hardware, and performing evolution on the non-evolution hardware;
referring to fig. 4 and 5, the evolving hardware is composed of an FPGA logic array and an ARM computational core; and constructing a VRC virtual reconfigurable circuit in the FPGA logic array by using a Verilog language, and simultaneously realizing a fitness calculation module in the FPGA logic array. And transmitting the target input column and the target output column of the evolution hardware into the FPGA. And (3) realizing a genetic algorithm in an ARM core, and importing high-similarity chromosome individuals.
Referring to FIG. 6, a plurality of input signals enter the first multiplexer to select the first input signal, which is the PE at the gene site 1. The multiple input signals enter a second multiplexer to select a second input signal, which is the PE at position 2. The PE node comprises a function table containing a plurality of one-bit logic operations, for example, 5 operations such as { AND, OR, NOR, XOR AND NAND }, a function is selected as the operation function of the PE node, AND a signal is selected as the gene bit 3 of the PE; and performing logic operation on the two selected input signals to finally obtain output.
A VRC virtual reconfigurable circuit is composed of input nodes in a first column, PE nodes arranged in the middle in a matrix mode and output nodes in a last column. Referring to fig. 7, the 6 PE nodes 2 × 3 are arranged in a matrix, the 3 input nodes AND the 3 output nodes are numbered 0 to 11 in total, AND the function sets are exemplified by 5 in total { AND, OR, NOR, XOR, NAND } AND are numbered 0 to 4.
And setting the link degree L, wherein the nodes in the same column cannot be connected and can only be connected with the front L-1 column according to the constraint of the matrix CGP. And each PE node selects the number of the connecting node as the gene position of the node. The genetic loci of the three multiplexers { input node 1, input node 2, arithmetic function } of the PE node constitute the genome of this node. The output nodes have only { output nodes } as a single gene. The genomes of all PE nodes and output nodes together form a chromosome of the VRC virtual reconfigurable circuit. The different chromosomes represent different circuits represented by the VRCs.
And in the second part, a fitness calculation module is realized by using an FPGA (field programmable gate array), a VRC (virtual reconfigurable Circuit) configured by chromosomes is used for inputting an evolved hardware target input, and the Hamming distance comparison is carried out on an output value and an evolved hardware output value.
And performing exclusive OR calculation on the negation of the output columns and the corresponding evolution hardware target output columns, and summing each bit to obtain the Hamming distance. And the sum of the Hamming distance between the input of all target input columns and the output of the configured VRC virtual reconfigurable circuit and the output value of the evolved hardware target is the fitness value of the chromosome, and the fitness value is input to an ARM computing core to be evolved by using a genetic algorithm.
In the third section, please refer to fig. 8, the genetic algorithm is implemented in the ARM computing core.
S501, taking the matched high-similarity individual chromosome in the static configuration library as an initial individual, and then randomly generating m-1 individuals. Creating a function fun _ roulette (m, n) according to a roulette algorithm, the function being to input fitness of m individuals, selecting n individuals according to the roulette algorithm; and creating a random generation function random (k), wherein the function is to generate k random numbers, and the value range is 0-1.
Setting parameters: a maximum fitness value MAX; the adaptive crossover probability Pc, the adaptive mutation probability Pm and the diversity comparison value a.
S502, the m individuals enter a fitness calculation module to calculate fitness values, the fitness calculation module is used for calculating the fitness values of the m individuals, and the fitness values are stored in a fitness storage module. And simultaneously calculating a representative diversity parameter delta, specifically:
wherein favg is the average value of m individual fitness values, fmax is the maximum value of m individual fitness values, and fmin is the minimum value of m individual fitness values. Larger values of δ indicate lower population diversity and vice versa indicate less diversity.
S503, judging whether the maximum fitness of the m individuals is equal to or greater than MAX; if so, exiting the evolution, completing the evolution, otherwise entering the next step;
s504, selecting n1 individuals (n1 is an even number) from the m individuals by using a function fun _ roulette (m, n 1). The exchange probability Pc is automatically changed according to the following formula;
when the diversity parameter delta is larger than a, the diversity is poor, and the Pc value is increased; when the diversity parameter delta is less than a, the diversity is better, and the Pc value is kept unchanged.
Generating k random numbers by using a random generation function random (k) according to the total gene number k (k is 3 PE number +1 output node number), wherein the value range is 0-1, n1 individuals are paired in pairs, and when the ith random number is larger than the Pc value, the ith gene position is kept unchanged; when the ith random number is smaller than the Pc value, the ith gene position is exchanged.
S505, selecting n2 individual tickets from m individuals by using a function fun _ roulette (m, n2), automatically changing the variation probability Pm, and increasing the Pm value when the diversity parameter delta is larger than a and the diversity is poor; when the diversity parameter delta is less than a, the diversity is better, the Pm value is kept unchanged, the gene locus number w to be varied is calculated according to the total gene locus number k of the chromosome multiplied by Pm, and w random numbers are generated by using a random generation function random (w) and the value range is 0-1;
the j gene position is randomly changed into another value, and the formula of j is as follows:
s506, using an epoch-spanning elite algorithm, computing n1 crossover children, n2 variant child fitness values, m parents, n1 crossover children, n2 variant children, and selecting m individuals from the m + n1+ n2 individuals using a function fun _ roulette (m + n1+ n2, m) as a next generation to enter S502.
The evolution hardware is completed by using a block evolution mechanism, part of the total target output of each block of evolution is output, and the target input of each block is the same;
and S6, performing exclusive OR operation by using the evolved evolvable hardware and the corresponding error position of the fault circuit to complete repair.
The improvement of the invention is as follows:
1. realizing static matching
When an error occurs and evolvement and repair are carried out, the chromosome information of the error output and corresponding evolvement hardware is stored; when the next error occurs, a match is first found in the static configuration library. If there is an identical error, the chromosome information is directly output. When the errors are not completely the same, the individual with the highest similarity is searched as an individual of the genetic algorithm in the evolution hardware, so that the evolution speed is improved.
2. For large-scale circuit evolution, a packet evolution method is adopted
Target outputs are grouped to improve parallelism.
3. Using adaptive genetic algorithms in evolving hardware
The genetic algorithm often has a premature phenomenon, and after several iterations, population individuals are highly similar and enter a local optimal solution. The diversity of the population decreases rapidly. In order to solve the sub-problem, an adaptive genetic algorithm is adopted, and a parameter delta is introduced to evaluate the diversity of the population of each generation. When the diversity is low, the exchange parameter Pm and the variation parameter Pc are increased, so that the population diversity is increased. The exchange parameter Pm and the variation parameter Pc are automatically changed according to the population characteristics.
In the application environment of aerospace and navigation, high requirements are put on the reliability of the circuit. The self-repairing circuit can automatically complete the repairing function of the circuit without manual intervention by using the evolution hardware as the self-repairing system of the circuit. Meanwhile, for the traditional triple-modular redundancy backup method, under the condition that a circuit generates errors, only the error part of the circuit is corrected, the whole backup is not started, and the circuit resources are greatly reduced. Meanwhile, a block evolution mechanism and a self-adaptive Pm and Pc parameter method are provided, and the evolution speed is improved.
In conclusion, the circuit self-repairing method based on the improved evolution hardware has a good application scene in the environments of aerospace, navigation and the like, and the self-adaptive characteristic can be used for repairing various logic circuits more flexibly.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. A circuit self-repairing method based on improved evolution hardware is characterized by comprising the following steps:
s1, when the circuit is in fault, carrying out bit XOR operation on the error output column of the fault circuit and the output column in the truth table of the correct circuit, and when the return value is 1, determining a repair section for the fault circuit; injecting an input column of a correct circuit truth table into a fault circuit to obtain an error output column;
s2, respectively carrying out exclusive OR calculation according to the true output column in the correct circuit truth table determined in the step S1 and the error output column of the fault circuit to obtain a target output column of the evolved hardware;
s3, after the target output column of the evolved hardware in the step S2 is inverted, bit XOR calculation is respectively carried out on the target output column of the evolved hardware and the target output column of the evolved hardware stored in the static configuration library, then each bit of the calculation result is added to obtain a sum value, and the sum value is used as the similarity value of the evolved hardware stored in the target evolved hardware and the static configuration library; taking the chromosome corresponding to the maximum value in the plurality of sum values in the static configuration library as a high-similarity individual chromosome;
s4, dividing the evolvable hardware which is not evolved into a plurality of blocks by using a block evolution mechanism, and dividing a target output column and a target input column of the evolvable hardware according to the same number of blocks according to the number of the divided blocks;
s5, respectively transmitting the evolution hardware target input column and the evolution hardware target output column which are divided in the step S4 and the high-similarity individual chromosomes obtained in the step S3 into non-evolution hardware which is divided into corresponding blocks, realizing a self-adaptive genetic algorithm of the self-adaptive evolution hardware in an ARM (advanced RISC machine) computing core of the evolution hardware, and completing evolution of the non-evolution hardware;
and S6, performing exclusive OR operation by using the evolved hardware and fault circuit corresponding error bit in the step S5 to complete repair.
2. The method according to claim 1, wherein in step S5, the evolving hardware comprises an FPGA logic array and an ARM computing core, and the VRC virtual reconfigurable circuit is constructed in the FPGA logic array; configuring a VRC virtual reconfigurable circuit by utilizing a chromosome, inputting the configured VRC virtual reconfigurable circuit into an evolving hardware target input column to generate an output column, comparing hamming distances of the output column and the evolving hardware target output column, and summing comparison values to serve as fitness values of corresponding chromosomes; and programming in an ARM computing core to realize a genetic method.
3. The method according to claim 2, wherein the VRC virtual reconfigurable circuit comprises input nodes, PE nodes and output nodes, the PE nodes are arranged in a matrix form, the link degree L is set, and the middle PE node in the same column is connected with the first L-1 column;
the PE node comprises two input circuits and an output circuit and has a unique number; the two input circuits are respectively connected with an output circuit for selecting the PE node by using a multi-path selector, and the number of the selected PE node is used as the gene position of the PE node;
selecting a logic operation for two input values selected by two input circuits by using a multiplexer in each PE node, and using the selected logic operation number as the gene position of the PE node; taking the serial numbers and the logic calculation serial numbers of the two input values PE nodes selected by the two input circuits as the genome of the PE node;
the output node of the VRC virtual reconfigurable circuit selects the output of one PE node as input by using a multiplexer, and the number of the selected PE node is used as the genome of the output node;
the genomes of all PE nodes and the genomes of the output nodes jointly form a chromosome of the VRC virtual reconfigurable circuit.
4. The method of claim 3, wherein a plurality of input signals are present in the PE node, and wherein the plurality of input signals enter the first multiplexer to select a first input signal, the first input signal corresponding to the genotype 1 of the PE node number; a plurality of input signals enter a second multiplexer to select a second input signal, and the second input signal is a gene position 2 corresponding to the serial number of the PE node; the PE node saves a function table, and the function table comprises various one-bit logical operations and has corresponding numbers; selecting a function as an operation function of the PE node, and selecting a signal as a gene position 3 corresponding to the PE node; and the two selected input signals are operated by using the selected logic operation to obtain PE node output.
5. The method of claim 2, wherein the hamming distance comparison is specifically:
inputting the configured VRC virtual reconfigurable circuit into a target input column, inverting the obtained output column, performing exclusive OR calculation on the inverted output column and a corresponding evolved hardware target output column respectively, and summing each bit to obtain a Hamming distance; and summing all the Hamming distances to obtain the fitness value of the chromosome.
6. The method of claim 2, wherein the genetic methods implemented in the ARM computing core are specifically:
s501, taking the high-similarity individual chromosomes matched in the static configuration library as an initial individual, and then randomly generating m-1 individuals; creating a roulette selection function fun _ roulette (m, n) according to a roulette method, the function being to input fitness of m individuals, selecting n individuals according to the roulette method, creating a random (k) function, the function being to generate k random numbers Ri;
s502, an ARM computing core is utilized to realize a fitness computing module, fitness values of m individuals are computed and stored, a genetic algorithm is skipped out after the fitness function output condition is triggered, and a target circuit is obtained after evolution is finished; simultaneously calculating a population diversity parameter delta;
s503, judging whether the maximum fitness of the m individuals is equal to or greater than the maximum fitness value; if the value is equal to or greater than the maximum fitness value, the evolution is exited, the evolution is completed, otherwise, the step S504 is entered;
s504, setting an adaptive crossover probability Pc, when a population diversity parameter delta is greater than a diversity comparison value a, Pc 1.3 for increasing, selecting n1 individuals from m individuals in the step S502 as crossed chromosomes by using a roulette selection function fun _ roulette (m, n1), generating k random numbers by using a random generation function random (k) according to the total gene number k of the chromosomes, pairing the n1 individuals in pairs, and when the ith random number is greater than the adaptive crossover probability Pc, exchanging the ith gene position;
s505, setting a self-adaptive variation probability Pm, when a diversity parameter delta is greater than a diversity comparison value a, Pm 1.1, increasing, selecting n2 individuals from m individuals in the step S502 as chromosomes by using a roulette selection function fun _ roulette (m, n2), calculating the number w of the gene positions needing to be varied according to the total number k of the gene positions of the chromosomes multiplied by Pm, generating w random numbers by using a random generation function random (w), multiplying the w random numbers by the number k of the gene positions to obtain the number of the gene positions needing to be varied, and randomly changing the gene positions needing to be varied into a gene value in a designated range;
s506, obtaining n1 crossover filial generations from the step S504 by using an epoch-spanning elite algorithm, obtaining n2 variant filial generations from the step S505, respectively calculating fitness values, obtaining m parent fitness values from the step S502, and selecting m individuals from m + n1+ n2 individuals by using a function fun _ roulette (m + n1+ n2, m);
and S507, obtaining m individuals from the step S506, entering the step S502, jumping out of the genetic algorithm after the fitness function output condition is triggered, and obtaining the target circuit after the evolution is finished.
7. The method according to claim 6, wherein in step S502, the diversity parameter δ is specifically:
wherein favg is the average value of the m individual fitness values, fmax is the maximum value of the m individual fitness values, and fmin is the minimum value of the m individual fitness values.
8. The method of claim 6, wherein in step S504, the adaptive swap probability Pc is specifically:
wherein a is a diversity comparison value, and δ is a diversity parameter.
9. The method according to claim 6, wherein in step S504, the gene exchange is specifically:
wherein Ri is a random number.
10. The method according to claim 6, wherein in step S505, the mutation probability Pm is automatically changed as follows:
wherein a is a diversity comparison value, and delta is a diversity parameter;
randomly transforming the jth gene locus into a value in a designated range, wherein the j value is specifically as follows:
wherein Ri is a random number.
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