CN104268253B - A kind of part triplication redundancy method counted based on look-up table configuration bit - Google Patents
A kind of part triplication redundancy method counted based on look-up table configuration bit Download PDFInfo
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Abstract
A kind of part triplication redundancy method counted based on look-up table configuration bit of the present invention, including step S1：It will treat that redundant circuit is mapped as k input look-up table formats, and read the information for treating redundant circuit, set up circuit topological structure database；Step S2：Circuit topological structure information is counted, and records the unrelated configuration bit information for treating each node in redundant circuit；Step S3：According to unrelated configuration bit number, the single particle effect sensitive information of look-up table is obtained；Step S4：The sensitive look-up table of single-particle inversion is extracted from the single particle effect sensitive information of look-up table, and triplication redundancy processing is carried out to the sensitive look-up table of single-particle inversion, obtain and insert voting machine between each redundant module and nonredundancy module according to redundant results, build the part triplication redundancy circuit with anti-single particle effect capability.The present invention can be greatly enhanced the reliability of system, and can save the full triplication redundancy circuit hardware spending of about half.
Description
Technical field
The present invention relates to digital display circuit fault-toleranr technique field, the more particularly to hardware in programming device triplication redundancy technology
Expense reduces method.
Technical background
Programming device (FPGA) has the characteristics of construction cycle is short, cost is low, flexibility is high and is widely used in electronics
In system design, the fpga chip configured based on SRAM (SRAM), the realization of its function is completely dependent on inside
Configuration data, according to existing literature and in-orbit flying quality, SRAM type FPGA device is mainly easy in space radiation environment
By single-particle inversion (Single Event Upset, SEU) influence, thus based on SRAM FPGA system design answer emphasis
Consider single-particle inversion protection.
Fig. 1 a, which are shown, treats that redundant circuit constitutes schematic diagram, and Fig. 1 b show full triplication redundancy circuit and constitute schematic diagram.Such as
Redundant circuit includes module M1, M2, M3 to treating shown in Fig. 1 a, and the digital circuit for treating that redundant circuit is two-valued function is then treated
The result of redundant circuit module M1, M2, M3 output is logical zero or logical one.Module M1 receives multiple logics of outside input
Signal, module M1 exports multiple first logical signals, and module M2 receives multiple first logical signals, module M2 output it is multiple
Second logical signal passes to module M3, and module M3 is output as treating multiple 3rd logical signals of redundant circuit.Treat redundancy
Circuit carries out the circuit after full triplication redundancy as shown in Figure 1 b, i.e., by treating in Fig. 1 a, redundant circuit entirely replicates two parts, is formed
The parallel-connection structure of three branch roads is made up of three module M1, M2, M3, wherein each module M3 exports multiple 3rd logical signals respectively,
Exporting the 3rd logical signal total number according to three module M3 sets same population purpose voting machine V, voting machine V to receive three respectively
Individual module M3 exports the 3rd logical signal of total number, the 3rd logical signal root that each voting machine V is exported to three module M3
Principle according to " the minority is subordinate to the majority " is put to the vote, and judges that the 3rd logical signal is exactly the same logical value, judges the
Three logical signals are two identical logical values, therefore are overturned voting machine V when some redundant module and can still export correctly
Result.
Triplication redundancy is fault-toleranr technique the most frequently used at present, because its reliability is widely used in space system.Should
Ifq circuit is replicated three parts by method, can also be by comparing the correct result of output when one of circuit makes a mistake.
When two modules malfunction simultaneously, voting machine will be unable to adjudicate correct result, therefore for SRAM type FPGA triplication redundancy technology
It is general to coordinate periodic refreshing technology to use, it can effectively ensure system safe and stable operation.
But triplication redundancy technology has the problem of circuit overhead is excessive, complete triplication redundancy circuit can reach circuit overhead
200% before to redundancy is even more more, and considers that the limitation of power and volume should try one's best in concrete application and reduce hardware and open
Pin.For sensitiveness of the circuit different piece to single particle effect, optionally carrying out part triplication redundancy to circuit block can
Suitably to reduce expense, part triplication redundancy technology is that, using sacrifice circuit reliability as cost, the saving of hardware spending is corresponding
Ground can bring the reduction of reliability.It is the problem of part triplication redundancy design to be considered that choice how is carried out to circuit.
Those skilled in the art is it is proposed that the concept of sensitive door, saves circuit overhead by the sensitive door of only redundancy, be somebody's turn to do
Method is originally inputted one input probability of setting for circuit based on experience value first, and each door is calculated further according to circuit topological structure
Input probability, the controlling value characteristic with reference to gate circuit each door can be defined as to single event is sensitive or single event not
It is sensitive.Insertion voting machine after the sensitive door redundancy of single event is constituted into original circuit with the insensitive door of single event again
Function, is then mapped as look-up table configuration by FPGA synthesis tools again.
Because the sensitiveness of prior art is according to gate level circuit structure and input probability calculating, it, which is mapped to, is based on looking into
Fault-tolerant effect and expense saving after the FPGA structure of table is looked for all to have a greatly reduced quality.
The content of the invention
(1) technical problem solved
, can be directly in lut circuits model present invention aims at one kind is found in order to solve problem of the prior art
Upper operation and the part triplication redundancy method inputted independent of circuit, with very profound significance.
(2) technical scheme
A kind of part triplication redundancy method counted based on look-up table configuration bit of present invention offer, including step are as follows：
Step S1：It will treat that redundant circuit is mapped as k- input look-up table formats, and read the information for treating redundant circuit, set up electricity
Road topology data storehouse, the look-up table is the look-up table in FPGA；
Step S2：Circuit topological structure information to circuit topological structure database is counted, and writing circuit topology
The unrelated configuration bit information of each node in redundant circuit is treated in structural database；
Step S3：According to unrelated configuration bit number, the single particle effect sensitive information of look-up table is obtained；
Step S4：The look-up table of single-particle inversion-sensitivity is extracted from the single particle effect sensitive information of look-up table, and
Triplication redundancy processing is carried out to the look-up table of single-particle inversion-sensitivity, obtain and according to redundant results in each redundant module and
Voting machine is inserted between nonredundancy module, the part triplication redundancy circuit with anti-single particle effect capability is built.
(3) beneficial effect
The present invention is taken after above technical scheme, has advantages below relative to prior art：1) because the present invention is by electricity
Single-particle inversion-sensitivity look-up table has carried out triplication redundancy in road, therefore, it is possible to effectively improve circuit anti-single particle effect capability,
Extend the mean free error time of circuit.2) part triplication redundancy fault-tolerance approach and full triplication redundancy fault-tolerance approach phase of the invention
Than, the unrelated configuration bit of the invention by calculating look-up table, targetedly selection needs to carry out the look-up table of triplication redundancy,
The reliability of SRAM type FPGA circuitry is ensured to a certain extent, can greatly save circuit overhead.3) window of the present invention
Method can obtain the unrelated configuration bit of major part of look-up table in the short period of time, and gained set is the unrelated of whole circuit
The subset of configuration bit set, i.e., the infimum of the whole unrelated configuration bit of circuit.
Brief description of the drawings
Fig. 1 a and Fig. 1 b are to treat that redundant circuit and full triplication redundancy circuit constitute schematic diagram；
The flow chart for the part triplication redundancy method that Fig. 2 is counted for the present invention based on look-up table configuration bit；
Fig. 3 is that the inventive method realizes a kind of part triple-modular redundancy circuit structure figure；
Fig. 4 is to treat that redundant circuit searches table level circuit structure diagram；
Fig. 5 is the lookup table level circuit structure diagram after present invention embodiment partial redundance used；
The workflow diagram of Fig. 6 unrelated configuration bit computational methods of look-up table used in the present invention；
Fig. 7 is present invention window division methods flow chart used；
Fig. 8 is present invention window division methods schematic diagram used；
Fig. 9 is the present invention unrelated configuration bit lookup method flow chart used；
The single event emulation mode flow chart that Figure 10 provides for the present invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, is described in further details to the present invention.
Triplication redundancy method in part of the present invention defines single-particle inversion-sensitivity according to the number of the unrelated configuration bit of look-up table and looked into
Look for table and single-particle inversion-insensitive look-up table, and only redundancy single-particle inversion-sensitivity look-up table.The part triplication redundancy
System includes triplication redundancy part and non-triplication redundancy part, wherein：Triplication redundancy part is by the way that the single-particle in circuit is turned over
Turn-sensitivity look-up table replicates two parts and insertion majority voting device is constituted at output；Non- triplication redundancy part is by the list in circuit
Particle upset-insensitive look-up table is constituted；The connection of triplication redundancy part and non-triplication redundancy part keeps opening up for ifq circuit
Structure is flutterred, designed part triplication redundancy circuit can keep ifq circuit function constant.
The flow chart for the part triplication redundancy method that the present invention is counted based on look-up table configuration bit, uses this as shown in Figure 2
The operation that method carries out part triplication redundancy embodiment to FPGA circuitry includes the steps：Step S1：Use California, USA
The instrument RASP that university Los Angeles branch school is provided will treat that redundant circuit is mapped as k- input look-up table formats, read this and treat redundant electric
Road information, sets up circuit topological structure database, and the look-up table is a kind of resource in FPGA, for realize combinational logic and
Sequential logic.Step S2：Circuit topological structure information to circuit topological structure database is counted, and writing circuit topology
The unrelated configuration bit information of each node in redundant circuit is treated in structural database；Node is drawn according to circuit topological structure
Point, node window is obtained, judges whether to calculate unrelated configuration bit further according to node window information, if the leaf section of window
When points are met less than leaf node maximum Lmax, then the number and record of the unrelated configuration bit of the node are calculated；If window
Leaf node number be unsatisfactory for be less than maximum Lmax when, then the unrelated configuration bit number of the node is designated as 0.Node is unrelated to match somebody with somebody
Set number calculating method is：It is window generating test set with exhaustive method, the exhaustive testing is applied to window leaf node
Collect and overturn one by one each configuration bit of node, whether the output of watch window root node changes；If overturning certain configuration bit and traversal
Whole exhaustive testing collection, window root node output is unchanged, then the configuration bit is the unrelated configuration bit of node.Step S3：
According to the unrelated configuration bit number of record, the single particle effect sensitive information of look-up table is obtained, this method sets one first
The unrelated configuration bit threshold value H of look-up table, when the unrelated configuration bit number of some look-up table is higher than the unrelated configuration bit threshold value H of look-up table
When, then can determine whether look-up table of the look-up table for single-particle inversion-insensitive, when some look-up table unrelated configuration bit number not
During configuration bit threshold value unrelated higher than look-up table, then it is assumed that the look-up table is the look-up table of single-particle inversion-sensitivity.The threshold value is set
It is fixed to need to be considered according to concrete application, treat that redundant circuit is higher to reliability requirement, threshold value H should be bigger, represented to treat superfluous with P
Remaining circuit shows out of order probability after being hit by single event, Nc represents look-up table configuration bit number, and this method is using public
Formula H=10 × (P-0.9) × Nc calculates the unrelated configuration bit threshold value of look-up table.When treating redundant circuit progress triplication redundancy, only
Redundancy processing is done to the look-up table of the single-particle inversion-sensitivity.Step S4：Part triplication redundancy circuit is built, from look-up table
Single particle effect sensitive information in extract the look-up table of single-particle inversion-sensitivity, and to the lookup of single-particle inversion-sensitivity
Table carries out triplication redundancy processing, obtains and voting is inserted between each redundant module and nonredundancy module according to redundant results
Device, builds the part triplication redundancy circuit with anti-single particle effect capability.
A kind of part triplication redundancy circuit realized as shown in Figure 3 using the inventive method；If existing result shows to treat superfluous
Only have module M1 to be easily to be influenceed and broken down by single particle effect in three modules in remaining circuit, and module M2 and module M3
To single particle effect and insensitive, then only carry out redundancy to module M1 to the property of may be selected by.
In view of above-mentioned setting Fig. 3 provides triplication redundancy circuit in part of the present invention, including three module M1, a module M2 and
An one module M3 and voting machine V, three module M1 are the first module M1, the second module M1, the 3rd module M1, wherein：The
One module M1, the second module M1, the 3rd module M1 input receive outside the multiple logical signals of input, due to the first module
M1, the second module M1, the 3rd module M1 are triplication redundancy signals, therefore multiple logical signals of outside input are fanned out into two parts points
The first module M1, the second module M1, the 3rd module M1 is not inputted to generate and export redundant signals；Voting machine V input and
One module M1, the second module M1, the 3rd module M1 output end connection, voting machine V is to the first module M1, the second module M1, the
The redundant signals of three module M1 outputs are put to the vote, and voting machine always exports phase in three according to the principle of " the minority is subordinate to the majority "
With value, when only one of which module M1 circuits are overturned and voting machine V is remained to by deciding by vote output correct knot during output error
Really；Module M2 input is connected with voting machine V output end, because module M2 is single-particle inversion-insensitive look-up table, mould
Block M2 is difficult to be overturned and malfunctioned by single event；Module M3 input is connected with module M2 output end, with module M2 phases
Together, module M3 is difficult to be overturned and malfunctioned by single event, by the final result of output circuit.From said structure, use
The part triplication redundancy circuit that the inventive method is realized is compared with full triplication redundancy circuit, and part triplication redundancy of the invention can be with
Unnecessary expense is saved, the difference of redundant module is treated according to physical circuit, the insertion number of voting machine is different from position, this
Saved circuit overhead can be caused different.
Application example of the present invention in physical circuit is given below：The present embodiment selects 1 MUX circuit using 8
Cm152a, the circuit is selected from the benchmark test circuit collection (MCNC ' 91) that South Carolina microelectronics center is provided, test electricity
Road, which is concentrated, includes multiple benchmark test circuits, and 8 select 1 MUX circuit cm152a to be a wherein less test circuit.
Fig. 4 shows to treat that redundant circuit searches table level circuit structure diagram, and it is that cm152a is reflected using RASP instruments to treat redundant circuit
The circuit inputted for 4- after look-up table configuration is penetrated, treats redundant circuit by [15], [16], [9], [10], [2], p1 this 6 look-up tables
Constitute tertiary structure.This treats that redundant circuit has 11 input signals to include：8 input signal pa to be selected of MUX, pb,
Pc, pd, pe, pf, pg, ph, coded input signal pi, pj, pk, this treats that redundant circuit has 1 output signal p1, and circuit is by compiling
Code input signal pi, pj, pk encoded radio select one in 8 input signals to be selected to be used as output signal.
The first order look-up table for treating redundant circuit is [15], [16], [9], [10], and look-up table [15] has 4 inputs, point
Do not receive from outside input signal pb, pf to be selected and coded input signal pj, pk；Believe in the middle of 1 output end, output first
Number.Look-up table [16] has 4 inputs, receive respectively from outside input signal pd, ph to be selected and coded input signal pj,
pk；1 output end, exports second M signal.Look-up table [9] has 4 inputs, receives respectively from outside input to be selected
Signal pa, pe and coded input signal pj, pk；1 output end, exports the 3rd M signal.Look-up table [10] has 4 inputs
End, is received from outside input signal pc, pg to be selected and coded input signal pj, pk respectively；1 output end, output the 4th
M signal.The second level look-up table for treating redundant circuit is [2], and look-up table [2] has 3 inputs, is received respectively from outside
Coded input signal pi and look-up table [15], first, second M signal of [16]；Believe in the middle of 1 output end, output the 5th
Number.
The third level look-up table for treating redundant circuit is p1, and look-up table p1 has 4 inputs, is received respectively from outside volume
Code input signal pi and look-up table [2], [9], the five, the three, the 4th M signals of [10]；1 output end, to outside output
Treat the output signal p1 of redundant circuit.
Treat that redundant circuit is made up of k- input look-up tables, k input of each look-up table receives the defeated of previous stage look-up table
Go out signal or original input signal, when a look-up table A input is connected with another look-up table B output end,
Claim the input look-up table that B is A.
As Fig. 5 shows that realized using the method for the present invention 8 select the selective triplication redundancies of 1 MUX circuit cm152a
Structure, selective triplication redundancy structural circuit includes non-redundant circuit part 51 and triplication redundancy circuit part 52, wherein three moulds
Redundant circuit part 52 includes look-up table [10] (1), [10] (2), [10] (3) and the voting machine V of three parts of redundancy.Citing makes below
With the present invention method judged result be look-up table [10] be single-particle inversion-sensitivity look-up table, remaining 5 are single-particle
Upset-insensitive look-up table, then look-up table [10] is replicated two parts of respectively [10] (2), [10] (3) by method of the invention,
Input signal pc, pg, pj, pk of look-up table [10] are also fanned out to two parts respectively as look-up table [10] (2), [10] (3) simultaneously
Input signal, then form three parts of function identical look-up tables [10] (1), [10] (2), [10] (3), they respectively have an output
End, exports the 4th M signal (1), the 4th M signal (2), the 4th M signal (3), these three output signals is led to respectively
Cross the input signal that look-up table p1 is re-used as after voting machine V puts to the vote.
Still so that above-mentioned 8 select 1 multiplexer circuit cm152a as an example, if as shown in Figure 4 using the method judged result of the present invention
Be single-particle inversion-sensitivity look-up table for look-up table [2], [9], [10], [2], [9], [10] output end and look-up table
P1 input is connected, then the method according to the invention look-up table [2], [9], [10] should respectively be carried out triplication redundancy and
Look-up table [2], [9], [10] output insert voting machine respectively, and the output result of three voting machines is used as the defeated of look-up table p1
Enter signal.So circuit also needs to additionally to increase by three look-up table conducts in redundancy after [2], [9], [10] three look-up tables
Voting machine.Be connected in view of input of the output end with look-up table p1 of look-up table [2], [9], [10], i.e., look-up table [2],
[9], [10] are look-up table p1 input look-up table, if look-up table p1 also to be carried out to redundancy and in look-up table p1 output
A voting machine is inserted, the resource of circuit consumption is identical with the mode for inserting three voting machines and can more ensure the reliable of circuit
Property, thus should take into full account when building part triplication redundancy circuit circuit structure and look-up table single event sensitiveness it
Between relation.The strategy of part triplication redundancy circuit building method is used in of the invention：Treat that redundant circuit carries out part to described
Also need to consider the concrete structure for treating redundant circuit during triplication redundancy processing, when the look-up table institute of redundancy single-particle inversion-insensitive
When the hardware spending brought is identical with the hardware spending that brings of insertion voting machine, redundancy single-particle inversion-insensitive should be selected
Look-up table, triplication redundancy is carried out to the single-particle inversion-insensitive look-up table.The lookup of one single-particle inversion-insensitive
The specific judgment mode whether table should carry out redundancy is：When a single-particle inversion-insensitive look-up table has two or two
When the look-up table of input more than individual is single-particle inversion-sensitivity look-up table, the single-particle inversion-insensitive look-up table should also be carried out
Triplication redundancy.
As shown in fig. 6, the workflow diagram that the unrelated configuration bit of the look-up table used in the present invention is calculated, described in step S2
The calculation procedure of the unrelated configuration bit of look-up table includes as follows：
Step S221：One node is chosen according to circuit node numbering.
Step S222：It is one window of the node division according to circuit topological structure, specific window division methods will be
Described in Fig. 7 of description of the invention.
Step S223：Whether decision node window divides success, if the node can be remembered the input of window with partition window
For leaf node, output is designated as root node, and the window information for setting up the data-base recording node enters step S224；If the node
The unsuccessful entrance step S226 of partition window.
Step S224：Whether the window leaf node number of decision node is less than leaf node number maximum set in advance
Lmax, because this method searches unrelated configuration bit by the way of fully simulated in window, workload is with the increasing of leaf node number
Plus exponentially increase again, when leaf node number is more than leaf node number maximum Lmax, into step S226, work as leaf node
When number is not more than the maximum Lmax of leaf node number, then into step S225.Leaf node number maximum is taken in the present embodiment
Lmax=20.
Step S225：The fully simulated nothing with look-up table where obtaining node of the input space is carried out to establish the node of window
Configuration bit is closed, specific unrelated configuration bit acquisition methods are by described in Fig. 8 of the present invention.
Step S226：For failing to set up the section of window or window leaf node number more than leaf node number maximum Lmax
The unrelated configuration bit number of node is directly designated as 0 by point.
Step S227：Set up the unrelated configuration bit information of data-base recording circuit node；
Step S228：Whole circuit is traveled through to count the unrelated configuration bit information of all nodes, and return to step S221,
Until the unrelated configuration bit Information Statistics of all nodes for traveling through whole circuit are finished, terminate this flow.
Window division methods flow chart used in the present invention is illustrated in figure 7, step is as follows：
Step S21：A certain node i in selection circuit.
Step S22：Judge that the node chosen is fanned out to whether number is more than tolerable fanout maximum set in advance
Omax, divides without window if the node fanout exceedes tolerable fanout maximum Omax and enters step S23, if should
Node fanout then enters step S27 not less than tolerable fanout maximum Omax.
The test set selected in the present embodiment, the test set is the benchmark test in the test sets of MCNC ' 91, the test set
There are several big circuits to include a small amount of many fan-out nodes in circuit, there is respective nodes fanout even up to tens, it is contemplated that
The diffusibility increase of its failure during node fanout increase, and the excessive window for often leading to mark off that is fanned out to is huge,
It can not also be operated in the later steps of this method, if therefore this step finds that node is fanned out to more than tolerable fanout maximum
Omax just not to the node division window, is divided labeled as node window and failed.Take tolerable fanout maximum in the present embodiment
Value Omax=50.
Step S23：N grades of input set, is included in and directly inputs set S_I1 before record node i, M grades after record node i
Output, be included in and be directly fanned out to output set S_O1.
Step S24：Rear M+N grades of output sets of all nodes, are included in and are fanned out to set indirectly in record input set S_I1
Preceding M+N grades of input set of all nodes, are included in input set S_I2 indirectly in S_O2, set of records ends S_O1.
Step S25：Ask and be fanned out to set S_O2 and indirectly input set S_I2 common factor indirectly, be designated as window associated section point set
Close S=S_O2^S_I2.
Step S26：Leaf node number and root node number that information calculates node i to be asked are fanned out to according to set S fan-in, and
Return to window and divide successful information.Wherein leaf node is the fan-in of all nodes and to be not belonging to set S node in window, root
Node is to belong to set S and it is fanned out at least one and is not belonging to set S.
In this step it should be noted that being originally inputted node and should be designated as leaf node, original output section in set S
Point should be designated as root node.The pi nodal functions specifically referred in this flow embodiment are divided.
Step S27：Flag node i windows divide failure, terminate the window division work of this node i.
1 Port Multiplier cm152a reference circuits are selected to introduce the specific of the window division methods that this method is used yet by 8 below
Operation, for the sake of simplicity, the present embodiment only describes the division methods of one-level window, i.e. M=N=1 situation：
The present embodiment selects 1 Port Multiplier cm152a reference circuits node [2] partition window for 8, for ease of observing and understanding, will
8 shown in Fig. 4, which select 1 Port Multiplier cm152a4- inputs to search table level circuit, is expressed as directed acyclic graph (Directed acyclic
Graph, DAG) form, as shown in figure 8, in the figure input signal still for pa, pb, pc, pd, pe, pf, pg, ph and pi,
Pj, pk, are used as the leaf node of directed acyclic graph；Output signal is still p1, as the root node of directed acyclic graph, in Fig. 4
First order intermediateness look-up table [9], [10], [15], the first order of [16] composition directed acyclic graph, second level intermediateness are looked into
Table [2] is looked for constitute the second level of directed acyclic graph, third level output look-up table p1 constitutes the second level of directed acyclic graph, had at this
Into acyclic figure, leaf node, root node and intermediateness node represent that line represents each section with the circle with nodal scheme
The connection status of point, the direction of arrow is the data transfer direction of circuit.Module 81 uses what this method was set up by node [2]
Window, if some node a input is another node b output end, then claim the input node that node b is node a, section
Point a is node b output node.The input of the node of module 81 [2] has input signal pi and node [15], [16], i.e. node
[2] input node is pi, [15], [16], and output end is that node p1 input, the i.e. output node of node [2] are p1, class
As, node [15] has that 4 input nodes are input signal pb, pf, pj, pk and an output node is node [2], node
[16] have that 4 input nodes are input signal pd, ph, pj, pk and an output node is node [2], node [9] have 4 it is defeated
Ingress is input signal pa, pe, pj, pk and an output node is node [2], and node [10] has 4 input nodes to be defeated
It is node [2] to enter signal pc, pg, pj, pk and an output node, and input signal pi does not have input node, there is 2 output nodes
For node [2], p1, output signal p1 has 4 input nodes to be input signal pi and node [2], [9], [10], does not export section
Point.The method for using the present invention is as follows for the specific implementation step of node [2] partition window：
To node [2] Look-ahead one-level input node, set S_I1={ pi, [15], [16] } is obtained, one is searched backward
Level output node, obtains set S_O1={ p1 }；
Each node in set S_I1 is searched respectively backward two-stage output obtain indirect output set SI_O2=pi,
[2], p1, [15], [16] }, the node p1 Look-aheads two-stage input in set S_O1 is obtained inputting set SI_I2=indirectly
{ p1, [2], pi, [15], [16], [9], pa, pe, pj, pk, [10], pc, pg }, take set SI_O2 and SI_I2 common factor to obtain
Module 811 in the window interdependent node set S={ pi, [2], p1, [15], [16] } of node [2], i.e. Fig. 7；
Node pb, pf, pj, pk, pd, ph, [9], [10] are included according to the set S window leaves that can obtain node [2], this
Outside, the node pi in set S is being originally inputted for circuit, is also the window leaf node of node [2]；There was only one in set S
Individual output node p1 is the root node of window.Can to sum up obtain the window of the node [2] comprising 9 leaf nodes pi, pb, pf,
Pj, pk, pd, ph, [9], [10] } and 1 root node p1 and 3 window interdependent nodes { [15], [16], [2] }.
As shown in figure 9, being unrelated configuration bit lookup method flow chart in present invention window used, drawn in step S27
The step of searching unrelated configuration bit in the window divided is as follows：
Step S231：If entering this flow for the first time, first configuration bit b of node is selectedk, k=0, otherwise k=k+
1, select next configuration bit b of nodek。
Step S232：Generate test vector, record output R (x) | bk；
It is window generating test set with exhaustive method, selects one of test vector x and obtained by logical simulation
The output R (x) of window root node | bk, wherein R (x) is root node output valve when window leaf node applies input vector x.
Step S233：Overturn configuration bit bk→bk, apply the test vector that previous step is produced, obtain output R ' (x) | (bk
→bk).The configuration bit b chosen in overturning step S21kAnd apply the test vector x in step S232 to window, by the window of acquisition
Mouth root node outputWherein R ' (x) is configuration bit bkUpset applies input vector x with rear hatch leaf node
When root node output valve,Represent to configuration bit bkCarry out single-particle inversion simulation, i.e. if there is bk=1
If there is bk=0
Step S234：Result R (x) in comparison step S232 and step S233 | bkWithIf havingThat is upset configuration bit bkThe output of window root node is not changed, then bkIt is not sensitive configuration
Position, then into step S235；If having
That is upset configuration bit bkThe output of rear hatch root node is changed, then bkIt is
Sensitive configuration bit, into step S237；
Step S235：To configuration bit bkWhether exhaustive all test sets are judged, if also have the test that does not apply to
Amount return to step S232 continues to test vector and tested, if being applied with all test vectors enters step
S236。
Step S236：Mark configuration bit bkIt is unrelated configuration bit.
Step S237：Mark configuration bit bkIt is sensitive configuration bit, i.e., is not unrelated configuration bit.
Step S238：Judge whether all configuration bits of traverse node, judge whether configuration bit number k reaches maximum
Value, if having reached maximum, into step S29；If configuration bit number k is not up to non-maximum, return to step S21 continues
Carry out the lookup of the unrelated configuration bit of the node.
Step S239：All configuration bits of the node, which have been emulated, to be finished, and sets up the unrelated configuration of the data-base recording node
Position information.
The part triplication redundancy circuit treated redundant circuit and built is provided for the present invention as shown in Figure 10 and carries out single-particle
Event simulation, to verify the ability of constructed part triplication redundancy circuit anti-single particle effect.The single event emulation
Comprise the following steps that：
Step S51：A configuration bit L of a look-up table of artificial circuit is treated in random selectionsbt, wherein L represented in circuit
Look-up table, s represents that look-up table is numbered, and b represents the configuration bit in look-up table, and t represents configuration bit number, that is, chooses s-th and look into
The t configuration bits looked in table.
Step S52：One test vector v of generation, O is exported according to treating that the acquisition of artificial circuit topology information is corresponding at random
(v)|Lsbt, the output valve of circuit when artificial circuit application input vector v is treated in wherein O (v) representatives.
Step S53：The configuration bit L chosen in overturning step S51sbtRepresent the t configuration bits in s-th of look-up table
On there occurs single event, and to treating that artificial circuit applies the test vector v that is generated in step S52 and obtain correspondence outputWherein O ' (v) represents upset configuration bit LsbtAfter treat artificial circuit apply input vector v when
The output valve of circuit.Represent to configuration bit LsbtCarry out single-particle inversion simulation, i.e. if there is Lsbt=1If there is Lsbt=0
Step S54：Output in comparison step S52 and step S53Circuit
Output end O, then into step S55；
If havingRepresent that the failure of injection can not be propagated to and treat artificial circuit
Output end O, into step S56.
Step S55：Treat that the number of faults of artificial circuit plus 1.
Step S56：Judge whether the trouble point quantity of injection has reached preset value, if not up to preset value, enter and return
Step S51 is returned to continue to inject failure；If having reached preset value, into step S57.
Step S57：Statistics treats the fault message of artificial circuit, and artificial circuit fault rate, single event emulation are treated in calculating
End-of-job.
Described above is only the preferred embodiment of the present invention, it is noted that those skilled in the art can be to this hair
It is bright to carry out various changes and modification without departing from the spirit and scope of the present invention.So, if these modifications and change of the present invention
Type belongs within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to exist comprising these changes and modification
It is interior.
Claims (7)
1. a kind of part triplication redundancy method counted based on look-up table configuration bit, including step are as follows：
Step S1：It will treat that redundant circuit is mapped as k- input look-up table formats, and read the information for treating redundant circuit, set up circuit and open up
Structural database is flutterred, the look-up table is the look-up table in FPGA；
Step S2：Circuit topological structure information to circuit topological structure database is counted, and writing circuit topological structure
The unrelated configuration bit information of each node in redundant circuit is treated in database；Wherein, the step of the unrelated configuration bit information is obtained
It is rapid as follows：Node is divided according to circuit topological structure, node window is obtained, judges whether further according to node window information
Unrelated configuration bit is calculated, if the leaf node number of window is met when being less than leaf node maximum, the node is calculated
Unrelated configuration bit number and record；If the leaf node number of window is unsatisfactory for being less than maximum, by the nothing of the node
Close configuration bit number and be designated as 0；
Step S3：According to unrelated configuration bit number, the single particle effect sensitive information of look-up table is obtained；
Step S4：The look-up table of single-particle inversion-sensitivity is extracted from the single particle effect sensitive information of look-up table, and to list
The look-up table of particle upset-sensitivity carries out triplication redundancy processing, obtains and according to redundant results in each redundant module and non-superfluous
Voting machine is inserted between complementary modul block, the part triplication redundancy circuit with anti-single particle effect capability is built.
2. triplication redundancy method in part as claimed in claim 1, it is characterised in that the unrelated configuration bit number calculating method of node
For：It is window generation exhaustive testing collection with exhaustive method, applies the exhaustive testing collection to window leaf node and overturn one by one
Whether each configuration bit of node, watch window root node output changes；If overturning certain configuration bit and traveling through whole exhaustive testing
Collection, window root node output is unchanged, then the configuration bit is the unrelated configuration bit of node.
3. triplication redundancy method in part as claimed in claim 1, it is characterised in that the single particle effect for obtaining look-up table is sensitive
The step of property information, is as follows：The unrelated configuration bit threshold value of a look-up table is set, when the unrelated configuration bit number of some look-up table is high
Then it is the look-up table of single-particle inversion-insensitive when look-up table unrelated configuration bit threshold value；When the unrelated configuration of some look-up table
Then it is the look-up table of single-particle inversion-sensitivity when position number is not higher than look-up table unrelated configuration bit threshold value.
4. triplication redundancy method in part as claimed in claim 3, it is characterised in that the unrelated configuration bit threshold value H of look-up table
It is expressed as follows：H=10 × (P-0.9) × Nc, wherein P are out of order general to be showed after redundant circuit is hit by single event
Rate, Nc is look-up table configuration bit number, it follows that treat that redundant circuit is higher to reliability requirement, the unrelated configuration bit threshold of look-up table
Value is bigger.
5. triplication redundancy method in part as claimed in claim 3, it is characterised in that carry out triplication redundancy treating redundant circuit
When, redundancy processing only is done to the look-up table of the single-particle inversion-sensitivity.
6. triplication redundancy method in part as claimed in claim 1, it is characterised in that treat redundant circuit and the part three built
Mould redundant circuit carries out single event emulation, to verify the energy of constructed part triplication redundancy circuit anti-single particle effect
Power.
7. triplication redundancy method in part as claimed in claim 1, it is characterised in that treat that redundant circuit carries out part three to described
Also need to consider the concrete structure for treating redundant circuit during the processing of mould redundancy, when the look-up table of one single-particle inversion of redundancy-insensitive
When can reduce the insertion of two or more voting machine, triplication redundancy should be carried out to the single-particle inversion-insensitive look-up table.
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| CN105718693B (en) * | 2016-01-28 | 2018-12-21 | 北京时代民芯科技有限公司 | A kind of FPGA circuitry Logic coverage optimization method based on configuration independent bit |
| CN109408839B (en) * | 2017-08-17 | 2023-08-25 | 复旦大学 | Radiation-resistant fault-tolerant FPGA circuit design method for reducing sensitive configuration bits through local redundancy |
| FR3082968B1 (en) * | 2018-06-21 | 2020-07-10 | Safran Electronics & Defense | METHOD FOR PROTECTING AN FPGA FROM NATURAL RADIATION |
| CN109766226A (en) * | 2018-12-28 | 2019-05-17 | 上海微阱电子科技有限公司 | A kind of multilayer secondary design realizes the digital circuit of multi-mode redundant voting function |
| CN111967684B (en) * | 2020-08-27 | 2024-02-02 | 北京合众伟奇科技股份有限公司 | Metering asset active distribution method based on big data analysis |
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