CN104461790B - A kind of selective triplication redundancy method based on look-up table ornamental tolerance - Google Patents

Abstract

The present invention proposes a kind of selective triplication redundancy method that SRAM type FPGA is measured based on ornamental, will treat that redundant circuit becomes the netlist form of k input look-up table, as the ifq circuit treating redundancy；It is the probable value of 1 according to all nodes in input step-by-step calculation circuit, in conjunction with the bit of storage, the ornamental of all look-up tables in step-by-step calculation circuit in look-up table memory cell；All look-up tables, in conjunction with the hardware spending ratio saved, are classified as sensitive and insensitive two classes of SEU by the anti-SEU ability of circuit after the ornamental computing redundancy according to look-up table；Select look-up table sensitive for SEU to do triplication redundancy, and between each redundancy look-up table and next stage nonredundancy look-up table, insert voting machine according to redundant results, it is achieved the selective triplication redundancy to ifq circuit.The method is applied on the FPGA product of SRAM, it is possible in reliability close to while full triplication redundancy, significantly reduce the resource overhead of FPGA.

Description

A kind of selective triplication redundancy method based on look-up table ornamental tolerance

Technical field

The present invention relates to digital display circuit fault-toleranr technique field, particularly to FPGA triplication redundancy skill Hardware spending in art reduces method.

Technical background

SRAM type FPGA is due to its low cost, good re_configurability and shorter exploitation week Phase, these characteristics were in built-in field, and especially Aero-Space built-in field receives widely Application.Owing to the logic circuit in FPGA is by the look-up table being dynamically loaded in SRAM entirely In memory cell, the bit of storage realizes, and is extremely easy to so working in space radiation environment Impact by single-particle inversion (Single Event Upset, SEU).SEU is by space radiation Charged particle projects what the sensitizing range of integrated circuit caused, and charged particle typically will not damage Hardware circuit itself, but the memory cell logical value normally resulting in FPGA changes (such as The bit of storage in FPGA line and look-up table memory cell), and then cause circuit function to change Become or the even system crash of result mistake.

Along with the development of integrated circuit technique, chip size is more and more less, and craft precision the most more comes The highest, circuit internal signal becomes increasingly susceptible to the interference of outside.Not only lead in space technology Territory, some application under common scenarios the most all propose requirement to the anti-SEU ability of circuit, because of This fault-tolerant ability has become as an important indicator of systematic function in every field.Traditional appearance The method of wrong technology many employings triplication redundancy, it is that currently used widest circuit reinforces skill Three identical circuit are i.e. carried out integrated by art, then to the result ballot that they run Mode is put to the vote, it is ensured that even if there being a circuit mistake occur, just also do not interfering with result Really property.

As shown in Figure 1a, before redundancy, circuit is made up of, once three modules M1, M2, M3 One module of any of which is destroyed by SEU, all can cause the result of final output error.Warp After crossing triplication redundancy, as shown in Figure 1 b, circuit replicates identical two part to its result, its In any one module impaired, all only can affect the output on a road, voting machine is according to ' minority clothes From majority ' principle, still can export correct result.This mode can greatly strengthen list The reliability of circuit under the influence of particle upset, but the shortcoming of triplication redundancy maximum is too much Extra hardware expense, it is typically the 200% of ifq circuit hardware size.

Summary of the invention

In order to strengthen the ability that the anti-SEU of SRAM type FPGA destroys, it is proposed that a kind of based on looking into Looking for the selective triplication redundancy method that table ornamental is measured, this method can be with relatively low hardware Expense so that the anti-SEU ability of circuit reaches the effect close to full triplication redundancy.

A kind of based on look-up table ornamental tolerance the selective triplication redundancy method of the present invention, bag Include step as follows:

Step S1: redundant circuit becomes k input and searches to use FPGA synthesis tool to treat The netlist form of table, as the ifq circuit treating redundancy；

Step S2: according to input step-by-step calculation circuit in all nodes be the probable value of 1, directly Output to ifq circuit；

Step S3: according to the ratio of storage in the probable value that node is 1 and look-up table memory cell Special position, from the beginning of the output of ifq circuit, in step-by-step calculation circuit, all look-up tables is considerable Property, until the input of ifq circuit；

Step S4: according to the anti-SEU ability of circuit after the ornamental computing redundancy of look-up table, In conjunction with comparing the hardware spending ratio that full triplication redundancy is saved, all look-up tables are classified as SEU Sensitivity and insensitive two classes of SEU；

Step S5: select look-up table sensitive for SEU to do triplication redundancy, builds triplication redundancy electricity Road.

Preferably, the ornamental of look-up table may be set to look-up table and causes itself because of SEU fault The probability that can observe at the output of circuit of exporting change.

Preferably, build valuation functions in step s 4, calculate the value of valuation functions, and depend on Select optimal redundancy ratio according to this value, in conjunction with ornamental size by look-up table descending, depend on According to sorting, all look-up tables are classified as SEU sensitivity and insensitive two classes of SEU；Described assessment Function is:

Evaluate (Rate)=SEU_immunity (Rate)^α*S(Rate)^β

Wherein, the hardware spending ratio that S (Rate) is saved by comparing full triplication redundancy, SEU_immunity (Rate) is the anti-SEU ability of circuit after redundancy, α, β be weight because of Son.

Preferably, if the next stage that look-up table sensitive for SEU in step S5 is connected is searched Table is that SEU is insensitive, then sensitive for SEU look-up table does triplication redundancy, forms redundancy and looks into After looking for table, voting to be inserted between the look-up table that redundancy look-up table and next stage SEU are insensitive Device.

Preferably, the three state buffer during described voting machine uses FPGA.

Preferably, the method also includes the step to the triplication redundancy circuit assessment built: pass through Linear feedback shift register generates the stochastic variable input vector A as circuit；Obtain Vector A is faultless circuit output vector Vector of input；Randomly select a look-up table to deposit The bit of storage in storage unit, by the logic of the bit of storage in this look-up table memory cell Value upset, forms faulty circuit；Obtain the faulty circuit output vector that vector A is input Vector_f；Analyze Vector_f the most consistent with Vector；Repeat the above steps is also added up The number of times that Vector_f is the most consistent with Vector；And then the triplication redundancy circuit constructed by assessment Assess anti-SEU ability.

Preferably, assessing the formula used by anti-SEU ability is

$\mathrm{SEU\; immunity}=(1-\frac{\mathrm{error}}{N})*100\%$

Wherein, error is the number of times that Vector_f and Vector is inconsistent, and N is fault simulation Number of times, SEU immunity is anti-SEU ability value.

The selective triplication redundancy method based on look-up table ornamental tolerance of the present invention

Triplication redundancy circuit is built by the method for the look-up table of selective redundancy SEU sensitivity, Compared with full triplication redundancy method, on the premise of ensureing that anti-SEU performance is basically unchanged, significantly Reduce the hardware spending of circuit after redundancy.

Accompanying drawing explanation

Fig. 1 a is the electrical block diagram before full triplication redundancy；

Fig. 1 b is the electrical block diagram after full triplication redundancy；

Fig. 2 is selective triplication redundancy method flow diagram based on ornamental tolerance；

Fig. 3 a is electrical block diagram before selectivity triplication redundancy of the present invention；

Fig. 3 b is electrical block diagram after selectivity triplication redundancy of the present invention；

Fig. 4 is circuit node probabilistic information calculation flow chart；

Fig. 5 is one 3 input look-up table schematic diagram；

Fig. 6 a is look-up table ornamental sample calculation figure；

Fig. 6 b is embodiment look-up table schematic diagram；

Fig. 7 is the ornamental calculation process schematic diagram of look-up table；

Fig. 8 is the screening process figure of look-up table sensitive for SEU；

Fig. 9 is the cm152a circuit diagram before the present embodiment selectivity triplication redundancy；

Figure 10 is the cm152a circuit diagram after the present embodiment selectivity triplication redundancy；；

Figure 11 is SEU fault simulation flow chart.

Detailed description of the invention

For making the purpose of the present invention, technological means and advantage clearer, below in conjunction with tool The enforcement sample of body, and referring to the drawings, the present invention is done comprehensively further description.

Problem based on the too much hardware spending of triplication redundancy complete in prior art, the present invention proposes A kind of selective triplication redundancy method based on look-up table ornamental tolerance, its objective is not Reduce, under the anti-SEU ability premise of loss redundant circuit, the look-up table number needing redundancy, with joint Save the hardware spending of circuit.Main thought is by analyzing all lookups in FPGA mapping circuit The ornamental of table, then according to ornamental tolerance look-up table is divided into look-up table sensitive for SEU and The look-up table that SEU is insensitive, and only look-up table sensitive for SEU is inserted triplication redundancy structure, This selective triplication redundancy based on ornamental tolerance can take into account anti-SEU ability and redundancy Consider of both rear hardware spending.Therefore the additional hardware comparing full triplication redundancy 200% is opened Pin, selective triplication redundancy can be saved substantial amounts of additional circuit expense, reach close to complete simultaneously The anti-SEU ability of triplication redundancy.

Fig. 2 illustrates the reality of the selective triplication redundancy method that the present invention measures based on ornamental Executing flow chart, this method carries out the operation of selective triplication redundancy and includes as follows FPGA circuitry 5 steps:

Step S1: redundant circuit is mapped as n input from gate leve to use Open-Source Tools RASP to treat Search table level circuit.Described look-up table is to realize circuit logic function in SRAM type FPGA Elementary cell, mostly typically be 4 inputs.According to storage in different look-up table memory cell Bit can realize different logic functions, and can repeatedly reconfigure.

Step S2: be the probable value of 1 according to all nodes in input step-by-step calculation circuit and be 0 Probable value, until the output of ifq circuit.For general circuit, its input signal The most random, the most typically acquiescence input node logic is the probability of ' 1 ' and is ' 0 ' Probability be all 0.5.It is all to have door that function is different or look-up table to be constituted due to circuit, The probability of its intermediate node and output node signal may be biased as 1 or be biased as 0.

Step S3: according to step S2 calculate the probable value that node is 1 and be 0 probable value, Calculate the ornamental of all nodes further.The ornamental of circuit node refers generally to its state and becomes Change the complexity can observed by output.The ornamental concept that the present embodiment uses is main It is applied to the assessment of circuit anti-SEU ability, and is used as the choosing of look-up table sensitive for SEU subsequently Select reference.For the ornamental of look-up table, it is defined below:

Look-up table because of SEU fault causes itself exporting change can be at the output of circuit The uncertain proposition observed, namely SEU fault can blaze abroad so that circuit produces The probability of mistake output.

Step S4: the look-up table ornamental calculated according to step S3 filters out sensitive the looking into of SEU Look for table.After so-called look-up table sensitive for SEU refers to SEU fault, having bigger probability will This error propagation is to output, and this probability ornamental of mistake presented hereinbefore is measured.Ornamental Higher look-up table is referred to as the look-up table that SEU is sensitive, needs a selected rational threshold for this Value, as the screening criteria of look-up table sensitive for SEU.The size of this threshold value influences whether sieve Look-up table sensitive for SEU after choosing number.It is the lowest that threshold value is arranged, the look-up table screened Will be the most, the anti-SEU ability of such circuit will be the highest, but the effect that hardware is saved is just Reduce.Therefore, the anti-SEU ability of circuit and the effect of hardware saving are that this disappears between the two That long relation, needs to weigh both, chooses most suitable threshold value optimum to arrive one Redundancy ratio.

Step S5: the look-up table sensitive for SEU filtered out according to previous step, inserts look-up table The part triplication redundancy of level, thus build the part triplication redundancy circuit with anti-SEU ability. If the next stage look-up table that sensitive look-up table is connected is that SEU is insensitive, then sensitive lookup Table does triplication redundancy, after forming redundancy look-up table, needs to insert voting machine and is then attached to next Insensitive for the SEU look-up table of look-up table insensitive for SEU (i.e. nonredundancy look-up table) of level. Three state buffer during wherein voting machine uses FPGA, to eliminate the interference of SEU and to reduce hard Part expense.

As shown in Figure 3 b, the selective triplication redundancy circuit after using the inventive method to realize, Fig. 3 a is the circuit structure before redundancy.If after calculating, discovery module M1, M3, M5 Easily affected by SEU and broken down, and module M2 and M4 are to SEU insensitive, then The property of may be selected by ground only carries out redundancy to module M1, M3, M5.

The schematic diagram of Fig. 3 b, including 5 modules M1, M2, M3, M4, M5 and 2 Voting machine Voter, wherein module M1, M3, M5 insert triplication redundancy structure, respectively by M1_1, M1_2, M1_3, M3_1, M3_2, M3_3 and M5_1, M5_2, M5_3 Three same modules are integrated, add that voting machine Voter constitutes part triplication redundancy circuit. Module M1, M3, M5 constitute one and propagate the path easily affected by SEU, therefore this road The module in footpath all inserts triplication redundancy, and path directly need not insert voting machine, such as Fig. 3 b institute Show.Owing to module M1_1, M1_2, M1_3 have three inputs, it is therefore desirable to by outside Input fan-out three parts connects the input of three redundant modules respectively.Similarly for module M1 also its It is connected to M2, but M2 is non-SEU sensitivity, is not required to triplication redundancy.Therefore, this Place needs to insert voting machine, decides by vote after an output, is connected to M2.

After module M1_1 occurs SEU fault, circuit is overturned and the value of output error.This Time voting machine voter1 receive from redundant module output and to redundant module M1_1, Three output signals of M1_2, M1_3 are put to the vote.One mistake output is correct defeated with two Go out, remain to the result correct by voting output, M2 according to the principle of " the minority is subordinate to the majority " Receiving correct input, therefore normal operation circuit will not be made mistakes.Also due to M3, M5 Being module sensitive for SEU, it is defeated that the mistake output of M1_1 is likely to result in M3_1, M5_1 The value made mistake, but to receive M5_1, M5_2, M5_3 tri-defeated for voting machine voter2 After going out, still can decide correct output so that circuit will not be made mistakes.

Being that SEU is insensitive for module M2 and M4, even if can make mistakes, its fault is difficult to Blaze abroad via M5, the reliability of electric current will not be impacted.

As shown in Figure 4, for the flow process of the node signal probability calculation described in step S2 of the present invention Figure, its calculation procedure includes the following:

Step S41: first input circuit file, extracts key letter according to the form of circuit file Breath, such as inputs number, exports number, the Topology connection information between look-up table number and look-up table, Set up the description information of circuit.Arranging the probability that all input logical values are 1 is 0.5, phase The probability that should be 0 is also 0.5.For general circuit, its input is the most all random, Therefore SP1 and SP0 of input node is 0.5.

Step S42: according to the circuit topology information extracted, to circuit hierarchy, obtain circuit Progression.The look-up table being connected with input is the 1st grade, and the look-up table being connected with output is last One pole.Judging according to progression in its all look-up tables being connected with input of intermediate look-up table progression The highest determines.If the input of a look-up table is respectively coupled to look-up table A, B, C, D's Export, and the progression of look-up table A, B, C, D is 3,4,4,5 respectively, then this look-up table Progression be 6.

Step S43: the next look-up table of selection circuit current level starts to calculate, until this The level all look-up tables of circuit all calculate complete.When just starting, start to calculate from the first order of circuit.

Step S44: calculate look-up table output logic be 1 and be 0 probability (SP).This Invention one look-up table of definition is output as a node of circuit, and node probable value is SP (signal probability).For a circuit, in the case of input vector is random, its joint Point logic be 1 probability be designated as SP1, logic be 0 probability be designated as SP0.Then node probability Value SP (signal probability) can be according to it on the premise of known circuit logic function The SP being originally inputted determines.The calculating details of concrete probability is discussed in detail in Figure 5.

Step S45: calculated node probabilistic information is added the circuit that step S41 is extracted In description information, as the foundation of next stage look-up table probability calculation.

Step S46: judge that the look-up table of current level the most all calculated probabilistic information, as The most no, continue to calculate the next look-up table of current level；If it is, enter under circuit One-level, continues to calculate.This traversal mode ensure that when every one-level look-up table calculates, its input SP information be all to be computed and updated.

Step S47: the next stage look-up table of selection circuit.

Step S48: judge that current level is whether beyond the afterbody of circuit.If it does not, Continue to calculate the look-up table of current level；If it is, whole look-up table probabilistic information is described Calculate complete.

Through above step, the probabilistic information of all look-up tables of circuit can be obtained, according to these Probabilistic information, can calculate the ornamental of all look-up tables further.

Fig. 5 is the schematic diagram of one 3 input look-up table, has 8 configuration (b₀～b₇) position is certainly Fixed concrete logic function, three inputs, an output.When input is in ' 000 ' during state, Choose b₀, then b it is output as₀Value；Input be in ' 010 ' time, choose b₂, then b it is output as₂ Value.Therefore the bit of storage in each look-up table memory cell can be obtained according to input probability Probability P (the b that position is selected₀)～P (b₇).According to the bit quilt of storage in look-up table memory cell The probabilistic information chosen, the specific formula for calculation that can obtain output probability SP1 and SP0 is as follows

${\mathrm{SP}}_1=\underset{i=1}{\overset{2^n}{\mathrm{\Σ}}}P\left(b_i\right),(b_i=1)---\left(1\right),$

${\mathrm{SP}}_0=\underset{i=1}{\overset{2^n}{\mathrm{\Σ}}}P\left(b_i\right),(b_i=0)---\left(2\right),$

Wherein n is to look for the input number of table, and 2ⁿThe i.e. bit of storage in look-up table memory cell Number.

The node probable value calculated according to previous step, can calculate the ornamental of node further. The ornamental of circuit node is referred generally to its state and changes the difficulty or ease journey can observed by output Degree.Definition look-up table ornamental is in the present invention: because SEU fault causes the output of itself The uncertain proposition that change can observe at the output of circuit, namely a SEU fault energy Enough blaze abroad so that circuit produces the probability of mistake output.

According to defined above, for a look-up table LUT1, its ornamental depends on its fan Go out the input state of electronic circuit.Assume electronic circuit only one of which look-up table LUT2, then work as LUT2 Other inputs are in non-control state, namely during sensitiveness, the output of LUT1 can be led to Cross LUT2 successfully to propagate to next stage.

Fig. 6 a is the schematic diagram of look-up table ornamental calculated example, a look-up table exporting change Whether can one-level one-level travel to forward output, depend on other look-up tables in propagation path Input state.Fig. 6 a calculates the ornamental of look-up table [1], the output of [1] and look-up table [2] Input pb be connected, then the propagation of look-up table [1] output end p b will depend on pa, pc State and the logic function of look-up table [2].

For more detailed description details, it is assumed that the logic function of look-up table [2] be 3 inputs with Door, has pa, pb, pc tri-input, and wherein pb is connected with the output of look-up table [1], has 8 Bit { the b of storage in individual look-up table memory cell₀～b₇, as shown in Figure 6 b.Patrol according to it Collecting function, in concrete look-up table memory cell, the bit information of storage is { b₀=0, b₁=0, b₂=0, b₃=0, b₄=0, b₅=0, b₆=0, b₇=1}.When the state of pa, pb, pc is ' 111 ', choosing The bit b of storage in middle look-up table memory cell₇=1, it is output as 1；As pa, pb, pc During for other states, output is 0.

Overturn, as pa, pc if look-up table [1] is caused exporting pb by a SEU interference When state is ' 00 ', no matter how pb overturns, changes, the output of look-up table [2] all without Change, namely the exporting change of look-up table [1] can not be propagated via look-up table [2].

Only when the state of pa, pc is ' 11 ', pb is the defeated of ' 0 ' then look-up table [2] Go out for ' 0 '；Pb for ' 1 ' then look-up table [2] be output as ' 1 '；Namely pb upset can make Obtaining the exporting change of look-up table [2], the exporting change of look-up table [1] can pass via look-up table [2] Broadcast.

Assume that the SP1 of pa, pc through the calculating of step S2 is respectively 0.5 and 0.6, then look into The probability looking for the exporting change of table [1] can propagate via look-up table [2] is 0.5*0.6=0.3, looks into The exporting change looking for table [1] cannot be 1 0.3=0.7 via the probability that look-up table [2] propagate.

But look-up table ornamental refers to that its state changes the difficulty or ease can observed by output Degree.Therefore the exporting change of look-up table [1] needs to continue to propagate to output via look-up table [2], Until the output of circuit.Its ornamental calculation expression is:

0_[1]=0.3*0_[2](3),

Wherein 0_[1]The ornamental of expression look-up table [1], 0_[2]Represent the ornamental of look-up table [2].

Fig. 7 is ornamental calculation process schematic diagram.For a circuit, its look-up table ornamental Calculating process contrary with node probability calculation process, be from the output of circuit to input step by step Calculate.

Step S71: first input circuit file, extracts key letter according to the form of circuit file Breath, such as inputs number, exports number, the Topology connection information between look-up table number and look-up table, Set up the description information of circuit.

The all nodes of input circuit be 1 probable value and be 0 probable value, as ornamental meter The foundation calculated.Then the look-up table ornamental arranging all outputs is 1.Can according to look-up table The definition of the property seen, it is clear that any change caused because of SEU of output, all can be directly in output End is observed, namely its ornamental is 100%.

Step S72: according to the circuit topology information extracted, to circuit hierarchy, obtain circuit Progression.The look-up table being connected with input is the 1st grade, and the look-up table being connected with output is last One pole.Judging according to progression in its all look-up tables being connected with input of intermediate look-up table progression The highest determines.If the input of a look-up table is respectively coupled to look-up table A, B, C, D's Export, and the progression of look-up table A, B, C, D is 3,4,4,5 respectively, then this look-up table Progression be 6.

Step S73: the next look-up table of selection circuit current level starts to calculate ornamental, Until this grade of all look-up table of circuit all calculates complete.When just starting, from the afterbody of circuit Start to calculate.

Step S74: from afterbody to first order step-by-step calculation ornamental.Why want reverse Step-by-step calculation, the propagation being because look-up table ornamental to rely on the look-up table with its next stage.

If the output of look-up table LUT1 is only connected to a look-up table LUT2, then its ornamental It is calculated as follows:

O_LUT1=P_propagate*O_LUT2(4),

Wherein P_propagateRepresent the probability that the exporting change of look-up table 1 is propagated via look-up table 2.

If look-up table LUT1 is output as many fan-outs, namely the output of look-up table LUT1 and n The input of individual look-up table is connected (n > 1).Then according to probability theory, its ornamental is calculated as follows:

$O_{\mathrm{LUT}1}=(1-\underset{i=1}{\overset{n}{\mathrm{\Π}}}(1-P_{\mathrm{propagate}\_i}))*O_{\mathrm{LUT}2}---\left(5\right),$

Wherein P_{propagate_i}It is to look for the probability that the exporting change of table 1 is propagated via i-th fan-out.

Step S75: calculated node ornamental information addition step circuit is described information In, the foundation calculated as upper level look-up table ornamental.

Step S76: judge that the look-up table of current level the most all calculated ornamental information, If it does not, continue to calculate the next look-up table of current level；If it is, enter circuit Upper level, continues to calculate.This traversal mode ensure that when every one-level look-up table calculates, its fan The look-up table ornamental information gone out is all to be computed and updated.

Step S77: the upper level look-up table of selection circuit.

Step S78: judge that current level is whether beyond the first order of circuit.If it does not, continue The continuous look-up table calculating current level；If it is, whole look-up table ornamental information is described Calculate complete.

Fig. 8 illustrates the flow process of the look-up table sensitive according to node ornamental information sifting SEU Figure.After so-called look-up table sensitive for SEU refers to SEU fault, have bigger probability by this Error propagation is to output, and this probability ornamental of mistake presented hereinbefore is measured.Ornamental Higher look-up table is referred to as the look-up table that SEU is sensitive, needs for this to select one reasonably Threshold value, as the selection standard of look-up table sensitive for SEU.The size of this threshold value can affect To look-up table sensitive for SEU number namely the size of redundancy ratio.It is low that threshold value is arranged, The look-up table screened will be many, and redundancy ratio is high, and the anti-SEU ability of such circuit is just Can be the highest, but the effect that hardware is saved just reduces；The height that threshold value is arranged, screens Look-up table few, redundancy ratio is low, but the anti-SEU ability of circuit will decline.Therefore, The effect that the anti-SEU ability of circuit and hardware are saved is shifting relation between the two, Need both are weighed, choose most suitable threshold value to arrive an optimum redundancy ratio.

For the circuit under different redundancy ratios, the anti-SEU ability of its correspondence and redundancy ratio it Between relation have equation below to express:

$\mathrm{SEU}\_\mathrm{immunity}\left(\mathrm{Rate}\right)=(1-\frac{1}{N}*\underset{i=1}{\overset{N*(1-\mathrm{Rate})}{\mathrm{\Σ}}}{O}_i)*100\%---\left(6\right),$

Wherein Rate is redundancy ratio, and N is the number of circuit look-up table, O_iIt is corresponding look-up table LUTi Ornamental.

Step S81: first input circuit file, extracts key letter according to the form of circuit file Breath, such as inputs number, exports number, the Topology connection letter between look-up table number and look-up table Breath, sets up the description information of circuit.

The ornamental information of all nodes of input circuit, and be stored in array Observability [].

Step S82: to array according to the size descending of ornamental.

Step S83: according to the order of array Observability [], from the lookup that ornamental is the highest Table starts redundancy, the number of incremental increase redundancy look-up table.When just starting, n=1, the most superfluous Yu first look-up table.

Step S84: the ornamental of known each look-up table, it is known that redundancy ratio Rate=n/N (N For total look-up table number), can be with the anti-SEU ability of circuit after computing redundancy according to formula (6) Data, and be stored in array SEU_immunity [].

Step S85: structure valuation functions, balance redundancy ratio and anti-SEU ability, to reach The minimum balance between redundancy ratio row and the highest anti-SEU ability.

Evaluate (Rate)=SEU_immunity (Rate)^α*S(Rate)^β[7],

$S\left(\mathrm{Rate}\right)=\frac{200\%-\mathrm{Rate}*2}{200\%}*100\%---\left(8\right),$

Wherein the hardware spending ratio that full triplication redundancy is saved is compared in S (Rate) expression, and α, β are Weighted factor, during balance, if the anti-SEU ability of circuit is the most crucial, α May be configured as the number slightly larger than 1；Whereas if hardware resource is more in short supply, need to save More hardware, can be set to the number slightly larger than 1 by β.

Step S86: judge n whether equal to N, namely the most all look-up tables of redundancy, If it does not, n increases by 1, the look-up table of n+1 before continuation redundancy；If it is, end redundancy Operation.

Step S87: find out the maximum of valuation functions Evaluate (Rate), and corresponding Redundancy ratio.This redundancy ratio is takes into account anti-SEU ability and the optimal redundancy of hardware spending Ratio.

Step S88: according to obtaining redundancy ratio Rate, before mark, N*Rate look-up table is The look-up table that SEU is sensitive.

Name the application example of a physical circuit, illustrate the present invention be embodied as step and The redundant results of final circuit.Example uses in MCNC 8 to select 1 MUX circuit cm152a。

Fig. 9 illustrates until redundant circuit opening up after RASP instrument is mapped as 4 input look-up tables Flutter structure chart.This circuit is made up of [15], [16], [9], [10], [2], these 6 look-up tables of pl. Circuit progression is three grades, has 11 input signals, and 8 including MUX to be selected defeated Enter signal pa, pb, pc, pd, pe, pf, pg, ph and three coded input signal pi, Pj, pk, have 1 output signal pl.

First the SP arranging input is 0.5, be 1 and be 0 probability be 0.5.Then Calculate probable value SP1 and the SP0 of all node signals.It is calculated the output of look-up table [15] It is the probability SP1=0.25 of 1, is the probability SP0=0.75 of 0；Look-up table [16] is output as 1 Probability SP1=0.25, be the probability SP0=0.75 of 0；Look-up table [9] is output as the probability of 1 SP1=0.25, is the probability SP0=0.75 of 0；Look-up table [10] is output as the probability SP1=0.25 of 1, It is the probability SP0=0.75 of 0；Look-up table [2] is output as the probability SP1=0.21875 of 1, is 0 Probability SP0=0.78125；Look-up table pl is output as the probability SP1=0.389648 of 1, is 0 Probability SP0=0.610352.

Then the probable value according to node calculates the ornamental of all nodes, is calculated look-up table [15] ornamental O_[15]=0.3；The ornamental O of look-up table [16]_[16]=0.3；Look-up table [9] Ornamental O_[9]=0.3；The ornamental O of look-up table [10]_[10]=0.3；The ornamental of look-up table [2] O_[2]=0.78125；The ornamental O of look-up table pl_pl=1.

By all look-up table ornamental descendings, there is O_pl=1, O_[2]=0.78125, O_[15]=0.3, O_[16]=0.3, O_[9]=0.3, O_[10]=0.3.By (redundancy during an ornamental redundancy 1 from high to low Ratio 16%), anti-SEU ability is 67%；(redundancy ratio 33%), anti-SEU during redundancy 2 Ability is 80%；During redundancy 3 (redundancy ratio 50%), anti-SEU ability is 85%；Redundancy When 4 (redundancy ratio 67%), anti-SEU ability is 90%；During redundancy 5 (redundancy ratio 83%), Anti-SEU ability is 95%；During redundancy 6 (redundancy ratio 100%), anti-SEU ability is 100%.

Above redundancy ratio data and anti-SEU capacity data are substituted into valuation functions (α=2, β=1), obtain the value of valuation functions be respectively Evaluate (16%)=0.38, Evaluate (33%)=0.43, Evaluate (50%)=0.36, Evaluate (67%)=0.27, Evaluate (83%)=0.15, Evaluate (100%)=0.Wherein maximum is Evaluate (33%)=0.43, therefore obtains Optimal redundancy ratio is 33%, namely 2 look-up tables of redundancy, is to look for table [2] respectively and searches Table pl.

Last tag look-up table [2] and look-up table pl are look-up table sensitive for SEU, and insert three Mould redundancy, the circuit structure after redundancy is as shown in Figure 10.

In order to assess the anti-SEU ability of circuit after selective redundancy, the present invention is given below A kind of SEU fault simulation method, Figure 11 shows the flow chart of this method, its concrete steps As follows:

Step S111: use LFSR (linear feedback shift register) to send out as random vector Raw device, generates the input as circuit of the random vector.

Step S112: carry out fault simulation according to the input vector of circuit, obtain circuit without reason Output vector Vector under barrier state.This output vector will be as ' gold output ' and fault Under output contrast, with the most wrong generation of decision circuitry.

Step S113: randomly select in any look-up table memory cell of any look-up table and store Bit, by this look-up table memory cell storage bit logical value upset, simulation The generation of SEU fault.

Step S114: keep input vector constant, again the circuit after fault is done fault mould Intend, obtain output vector Vector_f under fault.

Step S115: output vector Vector_f under fault is done with ' gold output ' Vector Contrast, if identical, illustrates that fault is made mistakes without result in circuit；If it is different, explanation fault Result in output to make a mistake.

Step S116: circuit is made mistakes, adds 1 by variable error, the number of times that writing circuit is made mistakes.

Step S117: decision circuitry SEU injects whether number of times reaches preset value N, if do not had Have and reach, continue to produce new input vector, re-inject SEU；If reached, then SEU Fault simulation completes, and terminates emulation.

Step S118: the data obtained according to above step, counting circuit anti-SEU ability is such as Under:

$\mathrm{SEU\; immunity}=(1-\frac{\mathrm{error}}{N})*100\%---\left(9\right).$

Claims (6)

1. a selective triplication redundancy method based on look-up table ornamental tolerance, its feature exists In, comprise the following steps that

Step S1: redundant circuit becomes k input and searches to use FPGA synthesis tool to treat The netlist form of table, as the ifq circuit treating redundancy；

Step S2: according to input step-by-step calculation circuit in all nodes be the probable value of 1, directly Output to ifq circuit；

Step S3: according to the ratio of storage in the probable value that node is 1 and look-up table memory cell Special position, from the beginning of the output of ifq circuit, in step-by-step calculation circuit, all look-up tables is considerable Property, until the input of ifq circuit；

Step S4: according to the anti-SEU ability of circuit after the ornamental computing redundancy of look-up table, In conjunction with comparing the hardware spending ratio that full triplication redundancy is saved, all look-up tables are classified as SEU Sensitivity and insensitive two classes of SEU；

Step S5: select look-up table sensitive for SEU to do triplication redundancy, builds triplication redundancy electricity Road；

Wherein, the ornamental of described look-up table is to look for table and causes described look-up table because of SEU fault The probability that the exporting change of itself can observe at the output of circuit.

2. the method for claim 1, it is characterised in that build in step s 4 and comment Estimate function, calculate the value of valuation functions, and select optimal redundancy ratio according to this value, in conjunction with All look-up tables, by look-up table descending, are classified as SEU according to sorting sensitive by ornamental size Two classes insensitive with SEU；Described valuation functions is:

Evaluate (Rate)=SEU_immunity (Rate)^α*S(Rate)^β

Wherein, the hardware spending ratio that S (Rate) is saved by comparing full triplication redundancy, SEU_immunity (Rate) is the anti-SEU ability under redundancy ratio is Rate, α, β It it is weighted factor；

Wherein, described Rate represents the redundancy ratio of look-up table；

$SEU\_immunity\left(Rate\right)=(1-\frac{1}{N}*\underset{i=1}{\overset{N*(1-Rate)}{\Σ}}{O}_i)*100\%\left(6\right),$

Wherein N is the number of circuit look-up table, O_iIt it is the ornamental of corresponding look-up table LUTi；

$S\left(Rate\right)=\frac{200\%-Rate*2}{200\%}*100\%.$

3. method as claimed in claim 2, it is characterised in that if SEU in step S5 The next stage look-up table that sensitive look-up table is connected is that SEU is insensitive, then SEU is sensitive Look-up table do triplication redundancy, after forming redundancy look-up table, be at redundancy look-up table and next stage Voting machine is inserted between the look-up table that SEU is insensitive.

4. method as claimed in claim 3, it is characterised in that described voting machine uses FPGA In three state buffer.

5. the method as described in any one of claim 1-4, it is characterised in that it is right also to include The step of the triplication redundancy circuit assessment built: generate one by linear feedback shift register Stochastic variable is as the input vector A of circuit；Obtain the fault-free electricity that described vector A is input Road output vector Vector；Randomly select the bit of storage in a look-up table memory cell, By the logical value upset of the bit of storage in this look-up table memory cell, form faulty circuit； Obtain faulty circuit output vector Vector_f that described vector A is input；Analyze Vector_f The most consistent with Vector；Repeat the above steps and add up Vector_f whether with Vector mono- The number of times caused；And then the triplication redundancy circuit anti-SEU ability of assessment constructed by assessment.

6. method as claimed in claim 5, it is characterised in that assess anti-SEU ability institute Formula be

$SEUimmunity=(1-\frac{error}{N})*100\%$

Wherein, error is the number of times that Vector_f and Vector is inconsistent, and N is fault simulation Number of times, SEU immunity is anti-SEU ability value.