CN114625197B - High-voltage linear voltage regulator with current enabling control - Google Patents
High-voltage linear voltage regulator with current enabling control Download PDFInfo
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- CN114625197B CN114625197B CN202210380270.4A CN202210380270A CN114625197B CN 114625197 B CN114625197 B CN 114625197B CN 202210380270 A CN202210380270 A CN 202210380270A CN 114625197 B CN114625197 B CN 114625197B
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- 239000003990 capacitor Substances 0.000 claims description 6
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003381 stabilizer Substances 0.000 description 2
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention belongs to the technical field of electronic circuits, and particularly relates to a high-voltage linear voltage regulator with current enabling control. The invention provides a high-voltage linear voltage regulator with current enabling control, and particularly relates to a high-voltage linear voltage regulator which is characterized in that a power tube grid electrode is pulled down by current in a current control mode when enabling is invalid, so that a power tube is turned off, and enabling control over an internal power supply is realized. When enabled, the operation principle is similar to that of the traditional linear voltage regulator. The linear voltage regulator with the current enable control has the advantages that the linear voltage regulator with the current enable control is enabled in a current control mode, stable adjustment of output voltage is achieved, and therefore the circuit can be widely applied to application scenes of converting high voltage into low voltage.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a high-voltage linear voltage regulator with current enabling control.
Background
With the increasing severity of environmental pollution and the development of new energy, bidirectional dc converters are widely used, such as dc uninterruptible power supply systems, aerospace power supply systems, electric vehicles, etc., and common isolated bidirectional converters have topological structures such as forward, flyback, push-pull, bridge, etc. In these application scenarios, the input voltage is high, and a relatively stable power supply voltage is required to drive these off-chip power tubes, and the common voltages include 5v,15v,20v, and the like, depending on the types of power tubes. The invention provides a high-voltage linear voltage stabilizer, which converts higher input voltage into lower voltage for driving an off-chip power tube.
Disclosure of Invention
In view of the above problems, the present invention provides a high voltage linear regulator with current enable control, which utilizes a current control manner to turn off the linear regulator by using current when an enable signal is invalid; when the enable signal is active, stable regulation of the output is achieved.
The technical scheme of the invention is as follows: through the current control mode, when the enable is invalid, the grid of the power tube is pulled down by using the current, so that the power tube is turned off, and the enable control of the internal power supply is realized. When enabled, the operation principle is similar to that of the traditional linear voltage regulator.
The technical scheme of the invention is as follows:
<xnotran> , , C1, CL, R1, R2, R3, R4, Q1, Q2, Q3, Q4, NMOS M1, NMOS M2, NMOS M3, NMOS M4, NMOS HM1, NMOS HM2, NMOS HM3, NMOS HM4, NMOS HM5, PMOS HP1, PMOS HP2, PMOS HP3, PMOS HP4, PMOS HP5, PMOS HP6, PMOS HP7, Z1, Z2, Z3, Z4, Z5, Z6, IBIAS1, IBIAS2, MOS ME1, MOS ME2, MOS ME3, MOS ME4, MOS ME5, MOS ME6; </xnotran> Wherein,
the drain electrode of the first high-voltage NMOS tube HM1 is connected with an input voltage and one end of a third resistor R3, the grid electrode of the first high-voltage NMOS tube HM1 is connected with the cathode of the first Zener tube Z1, the other end of the third resistor R3 and one end of a fourth resistor R4, and the source electrode of the first high-voltage NMOS tube HM1 is connected with the anode of the first Zener tube Z1, the drain electrode of the second high-voltage NMOS tube HM2 and the drain electrode of the third high-voltage NMOS tube HM 3; the grid electrode of the third high-voltage NMOS tube HM3 is connected with the cathode of the third Zener tube Z3, the other end of the fourth resistor R4 and the cathode of the fourth Zener tube Z4; the anode of the third Zener diode Z3 is connected with the source electrode of the third high-voltage NMOS tube HM 3; the anode of the fourth Zener diode Z4 is connected with the cathode of the fifth Zener diode Z5, the anode of the fifth Zener diode Z5 is connected with the cathode of the sixth Zener diode Z6, and the anode of the sixth Zener diode Z6 is grounded;
the grid electrode of the second high-voltage NMOS tube HM2 is connected with the cathode electrode of the second Zener tube Z2, the drain electrode of the fourth high-voltage PMOS tube HP4 and the collector electrode of the fourth triode Q4;
the source electrode of the first high-voltage PMOS tube HP1, the source electrode of the second high-voltage PMOS tube HP2, the source electrode of the third high-voltage PMOS tube HP3, the source electrode of the fourth high-voltage PMOS tube HP4 and the source electrode of the fifth high-voltage PMOS tube HP5 are connected with the source electrode of the third high-voltage NMOS tube HM 3;
the grid electrode of the third high-voltage PMOS tube HP3 and the grid electrode of the fourth high-voltage PMOS tube HP4 are connected with the drain electrode of the sixth enabling MOS tube ME6; the drain electrode of the third high-voltage PMOS pipe HP3 is connected with the drain electrode of the second high-voltage PMOS pipe HP2 and the collector electrode of the third triode Q3; the base electrode and the collector electrode of the third triode Q3 are interconnected, and the base electrode of the fourth triode Q4 is connected with the collector electrode of the third triode Q3;
the grid electrode of the first high-voltage PMOS tube HP1 and the grid electrode of the second high-voltage PMOS tube HP2 are connected with the drain electrode of the fifth enabling MOS tube ME 5; the drain electrode of the first high-voltage PMOS tube HP1 is connected with the drain electrode of the sixth high-voltage PMOS tube HP6 and the collector electrode of the first triode Q1;
the grid electrode and the drain electrode of the fifth high-voltage PMOS pipe HP5 are interconnected, and the drain electrode of the fifth high-voltage PMOS pipe HP5 is connected with the collector electrode of the second triode Q2; the base electrode of the second triode Q2 is connected with reference voltage VREF _2P5V, and the emitting electrode of the second triode Q2 is connected with the emitting electrode of the first triode Q1 and the drain electrode of the fourth high-voltage NMOS tube HM 4; the grid electrode of the fourth high-voltage NMOS tube HM4 is connected with the drain electrode of the first enabling MOS tube ME1, and the source electrode of the fourth high-voltage NMOS tube HM4 is grounded;
the gate source and the drain of a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3 and a fourth NMOS tube M4 are interconnected to form a protection module, wherein the source electrode of the fourth NMOS tube M4 is connected with the drain electrode of a sixth high-voltage PMOS tube HP6, and the source electrode of the first NMOS tube M1 is connected with the drain electrode of a seventh high-voltage PMOS tube HP 7;
a first capacitor C1 and a first resistor R1 which are connected in parallel are connected between the drain electrode of the seventh high-voltage PMOS tube HP7 and the base electrode of the first triode Q1, and the base electrode of the first triode Q1 is grounded through a second resistor R2;
the drain electrode of the fifth high-voltage NMOS transistor HM5 is connected to the drain electrode of the fourth high-voltage PMOS transistor HP4, the gate electrode of the fifth high-voltage NMOS transistor HM5 is connected to a first external control signal, the source electrode of the fifth high-voltage NMOS transistor HM5 is grounded, and the first external control signal is used for pulling up the gate electrode of the fifth high-voltage transistor HM5 when the power is turned on;
the input end of the first bias current source IBIAS1, the source electrode of the fifth enabling MOS tube ME5 and the source electrode of the sixth enabling MOS tube ME6 are connected with the source electrode of the third high-voltage NMOS tube HM 3; the output end of the first bias current source IBIAS1 is connected with the drain electrode of the first enabling MOS tube ME1 and the drain electrode of the third enabling MOS tube ME 3; the grid electrode and the drain electrode of the first enabling MOS tube ME1 are interconnected, and the source electrode of the first enabling MOS tube ME1 is grounded; the grid electrode of the third enabling MOS tube ME3 and the grid electrode of the fourth enabling MOS tube ME4 are connected with a second external control signal, and the source electrode of the third enabling MOS tube ME3 is grounded; the second external control signal is used for switching off the third enabling MOS tube ME3 and the fourth enabling MOS tube ME4 when the input voltage is undervoltage; the drain electrode of the fourth enabling MOS tube ME4 is connected with the drain electrode of the fifth enabling MOS tube ME5, the source electrode of the fourth enabling MOS tube ME4 is connected with the input end of the second bias current source IBIAS2, and the output end of the second bias current source IBIAS2 is grounded; the grid electrode and the drain electrode of the fifth enabling MOS tube ME5 are interconnected; the grid electrode and the drain electrode of the sixth enabling MOS tube ME6 are interconnected, the drain electrode of the sixth enabling MOS tube ME6 is connected with the drain electrode of the second enabling MOS tube ME2, the grid electrode of the second enabling MOS tube ME2 is connected with the grid electrode of the first enabling MOS tube ME1, and the source electrode of the second enabling MOS tube ME2 is grounded;
the source of the second high-voltage NMOS transistor HM2 is the output end of the linear regulator, and the output end is grounded after passing through the second capacitor CL.
The linear voltage regulator with the current enable control has the advantages that the linear voltage regulator with the current enable control is enabled in a current control mode, stable adjustment of output voltage is achieved, and therefore the circuit can be widely applied to application scenes of converting high voltage into low voltage.
Drawings
FIG. 1 shows the core of a high voltage linear regulator according to the present invention.
Fig. 2 shows the bias part of the high voltage linear regulator according to the present invention.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings;
the invention provides a linear voltage regulator core module, which is shown in figure 1. The first Zener diode Z1, the third Zener diode Z3, the fourth Zener diode Z4, the fifth Zener diode Z5, the sixth Zener diode Z6, the third resistor R3, the fourth resistor R4, the first high-voltage NMOS transistor HM1 and the third high-voltage NMOS transistor HM3 generate pre-bias voltage VREF _17V which is used for generating bias current and reference voltage; the first high-voltage P pipe HP1, the second high-voltage P pipe HP2, the third triode Q3, the fourth triode Q4 and the fifth high-voltage N pipe HM5 form an enabling part; a first triode Q1, a second triode Q2, a fifth high-voltage P pipe HP5, a sixth high-voltage P pipe HP6, a seventh high-voltage P pipe HP7, a second high-voltage N pipe HM2, a first resistor R1, a second resistor R2, a first capacitor C1 and a capacitor CL form a core part of the high-voltage linear voltage stabilizer; the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3 and the fourth NMOS tube M4 form a protection module, and corresponding protection is generated when the input VIN of a bus is under-voltage, the output VCC overflows and the external high voltage is artificially connected respectively, so that the reliability of the circuit is improved.
Specifically, when the module is operating normally, it is a more traditional linear regulator, and its stability is more conventional and not described too much.
Specifically, when the system is powered on, the system generates a Disable _ VCC signal to pull up the gate of the fifth high-voltage tube HM5, so that a pull-down current is generated to discharge the gate of the second high-voltage tube HM2, and the HM2 is prevented from being turned on by mistake in the power-on process. When the bus inputs VIN and is under-voltage, the system generates an enable signal VCC _ LOCK _1, the first enable tube ME1, the sixth enable tube ME6 are turned off, and the fifth enable tube ME5 starts normal mirroring, so that in the core module, the fourth high-voltage N tube HM4, the first triode Q1, the second triode Q2, the fifth high-voltage P tube HP5 and the sixth high-voltage P tube HP6 are turned off, the first high-voltage P tube HP1, the second high-voltage P tube HP2 of the enable module start mirroring current, the third high-voltage P tube HP3, the fourth high-voltage P tube HP4 are turned off, and the third triode Q3 and the fourth triode Q4 generate corresponding bias currents. The mirror current generated by the first high-voltage P tube HP1 pulls up the grid of the seventh high-voltage P tube HP7, and simultaneously the current mirrored by the fourth triode Q4 pulls down the grid of the second high-voltage N tube HM2, so that the gate-source voltage difference of the second high-voltage N tube HM2 is reduced, and the charging for the output VCC is stopped. Meanwhile, as the grid electrode of the seventh high-voltage P tube HP7 is raised, in order to avoid grid-source breakdown, when the grid electrode of the seventh high-voltage P tube is higher than a certain voltage, the first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3 and the fourth NMOS tube M4 start to be conducted, so that the grid-source voltage difference of the seventh high-voltage P tube HP7 is clamped, and the problem of circuit reliability caused by overhigh voltage is avoided.
Specifically, when the output voltage VCC is connected to a higher external power supply, the base current of the first triode Q1 is increased, so that a larger pull-down current is generated at the collector of the first triode Q1, and the gate voltage of the seventh high-voltage P-tube HP7 is rapidly reduced. In this process, since the second high-voltage pipe HM2 has no additional pull-down branch, the gate voltage thereof can only reach the output voltage VCC at the lowest, and therefore, the gate-source voltage of the seventh high-voltage pipe HP7 may be too large. To avoid this problem, the body diodes of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 will be forward biased, thereby increasing the gate voltage of the seventh high-voltage line HP 7. Since the forward bias current of the body diode is determined by the bias current of the fourth high-voltage pipe HM4 at this time, the body diode is turned on without causing a failure problem such as latch-up.
In summary, the high voltage linear regulator proposed by the present invention has the feature of current enable control, and can ensure the reliability of the circuit under the conditions of enabling turn-off and external VCC, and is suitable for driving the off-chip power transistor.
Claims (1)
1. <xnotran> , , C1, CL, R1, R2, R3, R4, Q1, Q2, Q3, Q4, NMOS M1, NMOS M2, NMOS M3, NMOS M4, NMOS HM1, NMOS HM2, NMOS HM3, NMOS HM4, NMOS HM5, PMOS HP1, PMOS HP2, PMOS HP3, PMOS HP4, PMOS HP5, PMOS HP6, PMOS HP7, Z1, Z2, Z3, Z4, Z5, Z6, IBIAS1, IBIAS2, MOS ME1, MOS ME2, MOS ME3, MOS ME4, MOS ME5, MOS ME6; </xnotran> Wherein,
the drain electrode of the first high-voltage NMOS tube HM1 is connected with an input voltage and one end of a third resistor R3, the grid electrode of the first high-voltage NMOS tube HM1 is connected with the cathode of the first Zener tube Z1, the other end of the third resistor R3 and one end of a fourth resistor R4, and the source electrode of the first high-voltage NMOS tube HM1 is connected with the anode of the first Zener tube Z1, the drain electrode of the second high-voltage NMOS tube HM2 and the drain electrode of the third high-voltage NMOS tube HM 3; the grid electrode of the third high-voltage NMOS tube HM3 is connected with the cathode of the third Zener tube Z3, the other end of the fourth resistor R4 and the cathode of the fourth Zener tube Z4; the anode of the third Zener tube Z3 is connected with the source electrode of the third high-voltage NMOS tube HM 3; the anode of the fourth Zener diode Z4 is connected with the cathode of the fifth Zener diode Z5, the anode of the fifth Zener diode Z5 is connected with the cathode of the sixth Zener diode Z6, and the anode of the sixth Zener diode Z6 is grounded;
the grid electrode of the second high-voltage NMOS tube HM2 is connected with the cathode electrode of the second Zener tube Z2, the drain electrode of the fourth high-voltage PMOS tube HP4 and the collector electrode of the fourth triode Q4;
the source electrode of the first high-voltage PMOS tube HP1, the source electrode of the second high-voltage PMOS tube HP2, the source electrode of the third high-voltage PMOS tube HP3, the source electrode of the fourth high-voltage PMOS tube HP4 and the source electrode of the fifth high-voltage PMOS tube HP5 are connected with the source electrode of the third high-voltage NMOS tube HM 3;
the grid electrode of the third high-voltage PMOS tube HP3 and the grid electrode of the fourth high-voltage PMOS tube HP4 are connected with the drain electrode of the sixth enabling MOS tube ME6; the drain electrode of the third high-voltage PMOS pipe HP3 is connected with the drain electrode of the second high-voltage PMOS pipe HP2 and the collector electrode of the third triode Q3; the base electrode and the collector electrode of the third triode Q3 are interconnected, and the base electrode of the fourth triode Q4 is connected with the collector electrode of the third triode Q3;
the grid electrode of the first high-voltage PMOS tube HP1 and the grid electrode of the second high-voltage PMOS tube HP2 are connected with the drain electrode of the fifth enabling MOS tube ME 5; the drain electrode of the first high-voltage PMOS pipe HP1 is connected with the drain electrode of the sixth high-voltage PMOS pipe HP6 and the collector electrode of the first triode Q1;
the grid electrode and the drain electrode of the fifth high-voltage PMOS pipe HP5 are interconnected, and the drain electrode of the fifth high-voltage PMOS pipe HP5 is connected with the collector electrode of the second triode Q2; the base electrode of the second triode Q2 is connected with the reference voltage, and the emitting electrode of the second triode Q2 is connected with the emitting electrode of the first triode Q1 and the drain electrode of the fourth high-voltage NMOS tube HM 4; the grid electrode of the fourth high-voltage NMOS tube HM4 is connected with the drain electrode of the first enabling MOS tube ME1, and the source electrode of the fourth high-voltage NMOS tube HM4 is grounded;
the gate source and the drain of a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3 and a fourth NMOS tube M4 are interconnected to form a protection module, wherein the source electrode of the fourth NMOS tube M4 is connected with the drain electrode of a sixth high-voltage PMOS tube HP6, and the source electrode of the first NMOS tube M1 is connected with the drain electrode of a seventh high-voltage PMOS tube HP 7;
a first capacitor C1 and a first resistor R1 which are connected in parallel are connected between the drain electrode of the seventh high-voltage PMOS tube HP7 and the base electrode of the first triode Q1, and the base electrode of the first triode Q1 is grounded through a second resistor R2;
the drain electrode of the fifth high-voltage NMOS transistor HM5 is connected to the drain electrode of the fourth high-voltage PMOS transistor HP4, the gate electrode of the fifth high-voltage NMOS transistor HM5 is connected to a first external control signal, the source electrode of the fifth high-voltage NMOS transistor HM5 is grounded, and the first external control signal is used for pulling up the gate electrode of the fifth high-voltage transistor HM5 when the power is on;
the input end of a first bias current source IBIAS1, the source electrode of a fifth enabling MOS tube ME5 and the source electrode of a sixth enabling MOS tube ME6 are connected with the source electrode of a third high-voltage NMOS tube HM 3; the output end of the first bias current source IBIAS1 is connected with the drain electrode of the first enabling MOS tube ME1 and the drain electrode of the third enabling MOS tube ME 3; the grid electrode and the drain electrode of the first enabling MOS tube ME1 are interconnected, and the source electrode of the first enabling MOS tube ME1 is grounded; the grid electrode of the third enabling MOS tube ME3 and the grid electrode of the fourth enabling MOS tube ME4 are connected with a second external control signal, and the source electrode of the third enabling MOS tube ME3 is grounded; the second external control signal is used for switching off the third enabling MOS tube ME3 and the fourth enabling MOS tube ME4 when the input voltage is undervoltage; the drain electrode of the fourth enabling MOS tube ME4 is connected with the drain electrode of the fifth enabling MOS tube ME5, the source electrode of the fourth enabling MOS tube ME4 is connected with the input end of the second bias current source IBIAS2, and the output end of the second bias current source IBIAS2 is grounded; the grid electrode and the drain electrode of the fifth enabling MOS tube ME5 are interconnected; the grid electrode and the drain electrode of the sixth enabling MOS tube ME6 are interconnected, the drain electrode of the sixth enabling MOS tube ME6 is connected with the drain electrode of the second enabling MOS tube ME2, the grid electrode of the second enabling MOS tube ME2 is connected with the grid electrode of the first enabling MOS tube ME1, and the source electrode of the second enabling MOS tube ME2 is grounded;
the source of the second high-voltage NMOS transistor HM2 is the output end of the linear regulator, and the output end is grounded after passing through the second capacitor CL.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000353021A (en) * | 1999-06-11 | 2000-12-19 | Ricoh Co Ltd | Ccd analog signal processing ic and its overvoltage protective circuit |
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| CN105630052A (en) * | 2014-10-27 | 2016-06-01 | 朱丹 | Reference signal generation circuit for circuit protection |
| CN110007708A (en) * | 2019-04-18 | 2019-07-12 | 电子科技大学 | A kind of linear voltage regulator with pull-up current and pull-down current ability |
| US10503185B1 (en) * | 2018-07-12 | 2019-12-10 | Texas Instruments Incorporated | Supply voltage regulator |
| WO2021248267A1 (en) * | 2020-06-08 | 2021-12-16 | 深圳技术大学 | Voltage reference circuit with high power supply ripple rejection |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8680783B2 (en) * | 2011-08-10 | 2014-03-25 | Cree, Inc. | Bias voltage generation using a load in series with a switch |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000353021A (en) * | 1999-06-11 | 2000-12-19 | Ricoh Co Ltd | Ccd analog signal processing ic and its overvoltage protective circuit |
| CN105630052A (en) * | 2014-10-27 | 2016-06-01 | 朱丹 | Reference signal generation circuit for circuit protection |
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| US10503185B1 (en) * | 2018-07-12 | 2019-12-10 | Texas Instruments Incorporated | Supply voltage regulator |
| CN110007708A (en) * | 2019-04-18 | 2019-07-12 | 电子科技大学 | A kind of linear voltage regulator with pull-up current and pull-down current ability |
| WO2021248267A1 (en) * | 2020-06-08 | 2021-12-16 | 深圳技术大学 | Voltage reference circuit with high power supply ripple rejection |
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