CN114614340B - Coplanar electrode vertical cavity surface emitting laser and preparation method thereof - Google Patents
Coplanar electrode vertical cavity surface emitting laser and preparation method thereof Download PDFInfo
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- CN114614340B CN114614340B CN202210511190.8A CN202210511190A CN114614340B CN 114614340 B CN114614340 B CN 114614340B CN 202210511190 A CN202210511190 A CN 202210511190A CN 114614340 B CN114614340 B CN 114614340B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
- H01S5/18311—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement using selective oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/0211—Substrates made of ternary or quaternary compounds
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Abstract
The invention relates to the technical field of semiconductor lasers, and particularly discloses a coplanar electrode vertical cavity surface emitting laser and a preparation method thereof. According to the laser disclosed by the invention, the oxidation insulating layer grows between the buffer layer and the N-type DBR layer, and the current insulating layer is formed after oxidation, so that the substrate and the laser electrode are insulated, the impedance of the laser is favorably reduced, and the influence of a back-end circuit on the laser is removed.
Description
Technical Field
The invention relates to the technical field of semiconductor lasers, in particular to a coplanar electrode vertical cavity surface emitting laser and a preparation method thereof.
Background
Vertical Cavity Surface Emitting Lasers (VCSELs) have the advantages of low cost, low threshold, high speed, low power consumption, and the like, and are widely applied in the fields of short-distance data communication, parallel high-speed optical fiber communication, and the like. According to the positions of the positive and negative electrodes, two device types of a coplanar electrode structure (the positive and negative electrodes are designed on the same plane) and a non-coplanar electrode structure (the positive and negative electrodes are not on the same plane) are provided. Different electrode structure lasers can be selected according to circuit or structural design of devices and modules, the back of the VCSEL with the different-surface electrode is N-pole metal, the back metal electrode can conduct a plurality of devices, signal crosstalk exists during use, and the VCSEL cannot be made into an array product. Coplanar electrode VCSELs have the advantage of low capacitance, which has certain advantages in high rate applications.
In high-speed applications above 10Gb/s, the substrate of the VCSEL with the coplanar electrode needs to be selected from a semi-insulating substrate. Since the doped substrate has less defects, good quality and relatively low price, and is generally applied, most VCSELs have N-type doped GaAs substrate at present. The substrate has conductivity, so that the VCSEL substrate with the coplanar electrode can introduce parallel capacitance to the laser, high-frequency roll-off is brought, and the high-speed performance of the laser is reduced; meanwhile, when the coplanar electrode VCSEL is applied, the back surface of the VCSEL is welded into a circuit through conductive silver paste (the back surface is generally grounded GND), and due to the conductivity of the substrate, a potential difference is formed between the positive electrode and the negative electrode of the VCSEL and the GND, so that the laser is additionally influenced, and the risk of reliability is brought after long-term use.
Disclosure of Invention
In order to solve the technical problem, the invention provides a coplanar electrode vertical cavity surface emitting laser and a preparation method thereof, so that an oxidation insulating layer grows between a buffer layer and an N-type DBR layer, and a current insulating layer is formed after oxidation, thereby insulating a substrate and a laser electrode, being beneficial to reducing the impedance of the laser and removing the influence of a back-end circuit on the laser.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the utility model provides a coplane electrode vertical cavity surface emitting laser, includes by the substrate, buffer layer, oxidation insulating layer, N type DBR layer, lower restriction layer, quantum well active area, go up restriction layer, oxidation restriction layer, P type DBR layer, ohmic contact layer that set gradually from bottom to top, the laser is two-stage step structure, and first step from the top down is etched 3-10 to the position on N type DBR layer, and second step from the top down is etched to the juncture of oxidation insulating layer and buffer layer, and the outside deposit of first step and second step has the passive film, the side part regional packing of first step and second step has BCB insulating medium, first step top sets up the metal positive pole, sets up the metal negative pole on the second step.
In the above scheme, the material of the oxidized insulating layer is Al formed by oxidizing AlAs 2 O 3 And the thickness of the oxidation insulating layer is 10-15 nm.
In the above scheme, the material of the oxidation limiting layer is Al x Ga 1-x As or AlAs, wherein x =0.96-1.0, said oxide confinement layer being oxidized all around to Al 2 O 3 The central region is not oxidized, and the thickness of the oxidation limiting layer is 15-25 nm.
In the above scheme, the substrate is an n-type doped GaAs substrate, the buffer layer is made of GaAs, and the thickness of the buffer layer is 15-25 nm.
In the above scheme, the N-type DBR layer and the P-type DBR layer are both Al x Ga 1-x As and Al y Ga 1-y As is alternately grown, wherein x =0.1-0.2, y =0.8-1.0,the N-type DBR layer comprises 20-40 pairs of N-type DBRs, and the P-type DBR layer comprises 20-40 pairs of P-type DBRs.
In the above scheme, the material of the lower limiting layer and the upper limiting layer is Al x Ga 1-x As, wherein x = 0.3-0.6.
In the above scheme, the quantum well active region is made of Al x Ga 1-x As and GaAs are alternately grown, wherein x =0.3-0.35, or In x Ga 1-x As and Al y Ga 1-y And the As is alternately grown, wherein x =0.05-0.1, y =0.3-0.35, and the thickness of the quantum well active region is 5-8 nm.
In the scheme, the ohmic contact layer is made of GaAs and the thickness is 15-25 nm.
A method for preparing a coplanar electrode vertical cavity surface emitting laser comprises the following steps:
(1) selecting an N-type doped GaAs substrate, and growing a buffer layer, an oxidation insulation layer, an N-type DBR layer, a lower limiting layer, a quantum well active region, an upper limiting layer, an oxidation limiting layer, a P-type DBR layer and an ohmic contact layer on the substrate in sequence to manufacture an epitaxial wafer;
(2) performing dry etching on the epitaxial wafer to form two steps, wherein the first step is etched from top to bottom to the position of 3-10 pairs of N-type DBR layers, and the second step is etched from top to bottom to the junction of the oxide insulating layer and the buffer layer;
(3) depositing a layer of Si on the first step by adopting a PECVD process 3 N 4 Or SiO 2 The film is used as a mask to cover the oxidation limiting layer;
(4) carrying out full-layer oxidation on the oxidation insulating layer by adopting a wet oxidation process, wherein the oxidation time ensures that the whole layer is completely oxidized;
(5) etching to remove the mask of the first step, then continuing to perform a wet oxidation process to partially oxidize the oxidation limiting layer, and controlling the oxidation time to oxidize out the required aperture;
(6) depositing a layer of Si on the upper part of the substrate by adopting PECVD process 3 N 4 Or SiO 2 A passivation film; filling partial areas on the side surfaces of the first step and the second stepA BCB insulating medium; sputtering a metal anode on the top of the first step and sputtering a metal cathode on the second step by a magnetron sputtering technology; and finally, grinding and thinning the substrate to reach the required device thickness.
In the above scheme, the wet oxidation process comprises: placing the epitaxial wafer into an oxidation furnace, heating the oxidation furnace to 380-420 ℃, setting the water temperature to 92-98 ℃, introducing nitrogen to exhaust redundant air in the oxidation furnace, wherein the flow rate is 0.5-2L/min, and stabilizing for 15-25 min; and then, introducing water vapor and nitrogen at the flow rate of 3-6L/min, and controlling the oxidation time to ensure that the oxidation insulating layer is completely oxidized or the oxidation limiting layer is oxidized to form the required aperture size.
Through the technical scheme, the coplanar electrode vertical cavity surface emitting laser and the preparation method thereof provided by the invention have the following beneficial effects:
according to the invention, an oxidation insulating layer grows between the buffer layer and the N-type DBR layer, and a current insulating layer is formed after oxidation, so that the substrate and the laser electrode are insulated, the substrate insulating function of the VCSEL with the coplanar electrode is realized, the impedance of the laser is favorably reduced, and the influence of a back-end circuit on the laser is removed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a schematic diagram of a VCSEL according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for fabricating a coplanar electrode vcsel according to an embodiment of the present invention.
In the figure, 1, a substrate; 2. a buffer layer; 3. oxidizing the insulating layer; 4. an N-type DBR layer; 5. a lower confinement layer; 6. a quantum well active region; 7. an upper confinement layer; 8. an oxidation limiting layer; 9. a P-type DBR layer; 10. an ohmic contact layer; 11. a first step; 12. a second step; 13. a passivation film; 14. a BCB insulating medium; 15. a metal positive electrode; 16. a metal negative electrode.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The invention provides a coplanar electrode vertical cavity surface emitting laser, which comprises a substrate 1, a buffer layer 2, an oxide insulating layer 3, an N-type DBR layer 4, a lower limiting layer 5, a quantum well active region 6, an upper limiting layer 7, an oxide limiting layer 8, a P-type DBR layer 9 and an ohmic contact layer 10 which are sequentially arranged from bottom to top. The laser is of a two-stage step structure, a first step 11 is etched from top to bottom to the position of 3-10 pairs of N-type DBR layers 4, a second step 12 is etched from top to bottom to the junction of an oxidation insulating layer 3 and a buffer layer 2, a passivation film 13 is deposited outside the first step 11 and the second step 12, a BCB insulating medium 14 is filled in partial areas of the sides of the first step 11 and the second step 12, a metal anode 15 is arranged at the top of the first step 11, and a metal cathode 16 is arranged on the second step 12.
In this embodiment, the material of the oxide insulating layer 3 is Al formed by oxidizing AlAs 2 O 3 The thickness of the oxide insulating layer 3 is 10-15 nm.
The material of the oxidation limiting layer 8 is Al x Ga 1-x As or AlAs, where x =0.96-1.0, in this example, the usual Al can be selected 0.98 Ga 0.02 As, the periphery of the oxidation limiting layer 8 is oxidized to Al 2 O 3 The central region is not oxidized and the thickness of the oxide confinement layer 8 is 15-25 nm.
The substrate 1 is an n-type doped GaAs substrate 1, the buffer layer 2 is made of GaAs, and the thickness of the buffer layer 2 is 15-25 nm. The existing substrate 1 selected may have defects, so a layer of buffer layer 2 of the same material needs to be deposited on the existing substrate, and the growth of the materials above the epitaxial wafer is ensured to meet the requirements.
The N-type DBR layer 4 and the P-type DBR layer 9 are both Al x Ga 1-x As and Al y Ga 1-y As is alternately grown, wherein x =0.1-0.2 and y =0.8-1.0, and in this embodiment, Al is selected for both the N-type DBR layer 4 and the P-type DBR layer 9 0.12 Ga 0.88 As and Al 0.9 Ga 0.1 As is alternately grown. The N-type DBR layer 4 includes 20-40 pairs of N-type DBRs, and the P-type DBR layer 9 includes 20-40 pairs of P-type DBRs. This exampleIn the N-type DBR layer 4, the optical thickness of each DBR pair is half of the wavelength of the emitted laser, and the growth logarithm of the N-type DBR is determined according to the reflectivity, so that the reflectivity can be ensured to be between 99.0% and 99.8%, such as 34 pairs. In the P-type DBR layer 9, the optical thickness of each pair of DBRs is half of the wavelength of emitted laser, and the growth logarithm of the P-type DBR ensures that the reflectivity is between 99.9% and 99.96%, such as 23 pairs.
The lower limiting layer 5 and the upper limiting layer 7 are made of Al x Ga 1-x As, wherein x = 0.3-0.6.
The material of the quantum well active region 6 is Al x Ga 1-x As and GaAs are alternately grown, wherein x =0.3-0.35, or In x Ga 1-x As and Al y Ga 1-y And the As grows alternatively, wherein x =0.05-0.1, y =0.3-0.35, and the thickness of the quantum well active region 6 is 5-8 nm.
The ohmic contact layer 10 is made of GaAs and has a thickness of 15-25 nm.
A method for manufacturing a coplanar electrode vertical cavity surface emitting laser, as shown in fig. 2, comprises the following steps:
(1) selecting an N-type doped GaAs substrate 1, and growing a buffer layer 2, an oxidation insulation layer 3, an N-type DBR layer 4, a lower limiting layer 5, a quantum well active region 6, an upper limiting layer 7, an oxidation limiting layer 8, a P-type DBR layer 9 and an ohmic contact layer 10 on the substrate 1 in sequence to manufacture an epitaxial wafer;
(2) performing dry etching on the epitaxial wafer to form two steps, wherein the first step 11 is etched from top to bottom to the position of 3-10 pairs of N-type DBR layers 4, the diameter of the step is 20-30 mu m, the second step 12 is etched from top to bottom to the junction of the oxide insulating layer 3 and the buffer layer 2, and the diameter of the step is 45-55 mu m;
(3) depositing a layer of Si on the first step 11 by adopting a PECVD process 3 N 4 Or SiO 2 The thin film is used as a mask to cover the oxidation limiting layer 8, and the thickness of the thin film is 120 nm-180 nm;
(4) the oxide insulating layer 3 is subjected to full-layer oxidation by a wet oxidation process, thereby insulating the substrate 1 from and above the N-type DBR layer 4. The wet oxidation process comprises the following steps: placing the epitaxial wafer into an oxidation furnace, heating the oxidation furnace to 380-420 ℃, setting the water temperature to 92-98 ℃, introducing nitrogen to exhaust redundant air in the oxidation furnace, wherein the flow rate is 0.5-2L/min, and stabilizing for 15-25 min; then, introducing water vapor and nitrogen gas at the flow rate of 3-6L/min, and controlling the oxidation time to ensure that the oxidation insulation layer 3 is completely oxidized;
(5) etching to remove the mask of the first step 11, and then continuing to perform a wet oxidation process to partially oxidize the oxidation limiting layer 8, wherein the wet oxidation process comprises the following steps: placing the epitaxial wafer into an oxidation furnace, heating the oxidation furnace to 380-420 ℃, setting the water temperature to 92-98 ℃, introducing nitrogen to exhaust redundant air in the oxidation furnace, wherein the flow rate is 0.5-2L/min, and stabilizing for 15-25 min; then, introducing water vapor and nitrogen, wherein the flow rate is 3-6L/min, and the oxidation time is determined according to the required aperture size;
(6) depositing a layer of Si on the upper part of the substrate 1 by adopting PECVD process 3 N 4 Or SiO 2 A passivation film 13; filling a BCB insulating medium 14 in the partial area of the side parts of the first step 11 and the second step 12; sputtering a metal anode 15 on the top of the first step 11 and sputtering a metal cathode 16 on the second step 12 by a magnetron sputtering technology; the metal anode 15 and the metal cathode 16 are made of sequentially deposited Ti, Pt and Au or sequentially deposited Au, Ge, Ni and Au; and finally, grinding and thinning the substrate 1 to reach the required device thickness.
The current limitation formed by the wet oxidation process can also be realized by ion implantation and the like.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A preparation method of a coplanar electrode vertical cavity surface emitting laser is characterized in that the laser comprises a substrate, a buffer layer, an oxidation insulating layer, an N-type DBR layer, a lower limiting layer, a quantum well active region, an upper limiting layer, an oxidation limiting layer, a P-type DBR layer and an ohmic contact layer which are sequentially arranged from bottom to top, the laser is of a two-stage step structure, a first step is etched to the position of 3-10 pairs of N-type DBR layers from top to bottom, a second step is etched to the junction of the oxidation insulating layer and the buffer layer from top to bottom, passivation films are deposited outside the first step and the second step, the partial areas of the side surfaces of the first step and the second step are filled with BCB insulating media, the top of the first step is provided with a metal anode, and the second step is provided with a metal cathode;
the preparation method comprises the following steps:
(1) selecting an N-type doped GaAs substrate, and growing a buffer layer, an oxidation insulation layer, an N-type DBR layer, a lower limiting layer, a quantum well active region, an upper limiting layer, an oxidation limiting layer, a P-type DBR layer and an ohmic contact layer on the substrate in sequence to manufacture an epitaxial wafer;
(2) performing dry etching on the epitaxial wafer to form two steps, wherein the first step is etched from top to bottom to the position of 3-10 pairs of N-type DBR layers, and the second step is etched from top to bottom to the junction of the oxide insulating layer and the buffer layer;
(3) depositing a layer of Si on the first step by adopting a PECVD process 3 N 4 Or SiO 2 The film is used as a mask to cover the oxidation limiting layer;
(4) carrying out full-layer oxidation on the oxidation insulating layer by adopting a wet oxidation process, wherein the oxidation time ensures that the whole layer is completely oxidized;
(5) etching to remove the mask of the first step, then continuing to perform a wet oxidation process to partially oxidize the oxidation limiting layer, and controlling the oxidation time to oxidize out the required aperture;
(6) depositing a layer of Si on the upper part of the substrate by adopting PECVD process 3 N 4 Or SiO 2 A passivation film; filling BCB insulating media in partial areas of the side portions of the first step and the second step; sputtering a metal anode on the top of the first step and sputtering a metal cathode on the second step by a magnetron sputtering technology; finally, liningAnd grinding and thinning the bottom to reach the required device thickness.
2. The method as claimed in claim 1, wherein the oxide insulating layer is made of Al formed by oxidizing AlAs 2 O 3 And the thickness of the oxidation insulating layer is 10-15 nm.
3. The method as claimed in claim 1, wherein the oxide confinement layer is Al x Ga 1-x As or AlAs, wherein x =0.96-1.0, said oxide confinement layer being oxidized all around to Al 2 O 3 The central region is not oxidized, and the thickness of the oxidation limiting layer is 15-25 nm.
4. The method as claimed in claim 1, wherein the substrate is n-type doped GaAs, the buffer layer is made of GaAs, and the thickness of the buffer layer is 15-25 nm.
5. The method according to claim 1, wherein said N-type and P-type DBR layers are both Al x Ga 1-x As and Al y Ga 1-y And the As is alternately grown, wherein x =0.1-0.2, y =0.8-1.0, the N-type DBR layer comprises 20-40 pairs of N-type DBRs, and the P-type DBR layer comprises 20-40 pairs of P-type DBRs.
6. The method as claimed in claim 1, wherein the lower and upper confinement layers are made of Al x Ga 1-x As, wherein x = 0.3-0.6.
7. The method as claimed in claim 1, wherein the quantum well active region is made of Al x Ga 1-x As and GaAs are alternately grown, wherein x =0.3-0.35, or In x Ga 1-x As and Al y Ga 1-y As is alternately grown, wherein x =0.05-0.1, y =0.3-0.35, and the thickness of the quantum well active region is 5-8 nm.
8. The method as claimed in claim 1, wherein the ohmic contact layer is made of GaAs and has a thickness of 15-25 nm.
9. The method according to claim 1, wherein the wet oxidation process comprises: placing the epitaxial wafer into an oxidation furnace, heating the oxidation furnace to 380-420 ℃, setting the water temperature to 92-98 ℃, introducing nitrogen to exhaust redundant air in the oxidation furnace, wherein the flow rate is 0.5-2L/min, and stabilizing for 15-25 min; and then introducing water vapor and nitrogen at the flow rate of 3-6L/min, and controlling the oxidation time to ensure that the oxidation insulating layer is completely oxidized or the oxidation limiting layer is oxidized to be in the required aperture size.
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