CN114586171A - 一种功率器件的终端结构和其制作方法、及一种功率器件 - Google Patents

一种功率器件的终端结构和其制作方法、及一种功率器件 Download PDF

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CN114586171A
CN114586171A CN202080022689.1A CN202080022689A CN114586171A CN 114586171 A CN114586171 A CN 114586171A CN 202080022689 A CN202080022689 A CN 202080022689A CN 114586171 A CN114586171 A CN 114586171A
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layer
type
field limiting
substrate
power device
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杨文韬
黄伯宁
赵倩
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thyristors (AREA)

Abstract

本申请实施例提供一种功率器件的终端结构，包括衬底和设于衬底第一表面的多个场限环，衬底包括漂移层和掺杂层，掺杂层从衬底的第一表面向内扩散形成，掺杂层和漂移层为第一导电类型，且掺杂层的杂质浓度大于漂移层的杂质浓度，场限环为第二导电类型。采用本申请所提供的终端结构，通过掺杂层的设计，实现对场限环中杂质的横向扩散限制，一方面减小终端结构的设计尺寸，降低芯片成本；另一方面降低外部电荷对终端结构的影响，提升功率器件的可靠性。同时本申请还提供一种功率器件的终端结构的制作方法和一种功率器件。

Description

PCT国内申请，说明书已公开。

Claims (17)

  1. PCT国内申请，权利要求书已公开。
CN202080022689.1A 2020-09-30 2020-09-30 一种功率器件的终端结构和其制作方法、及一种功率器件 Pending CN114586171A (zh)

Applications Claiming Priority (1)

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PCT/CN2020/119634 WO2022067750A1 (zh) 2020-09-30 2020-09-30 一种功率器件的终端结构和其制作方法、及一种功率器件

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CN114586171A true CN114586171A (zh) 2022-06-03

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US (1) US20230238426A1 (zh)
EP (1) EP4207306A4 (zh)
JP (1) JP2023544308A (zh)
CN (1) CN114586171A (zh)
WO (1) WO2022067750A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032878A (en) * 1990-01-02 1991-07-16 Motorola, Inc. High voltage planar edge termination using a punch-through retarding implant
US5075739A (en) * 1990-01-02 1991-12-24 Motorola, Inc. High voltage planar edge termination using a punch-through retarding implant and floating field plates
JPH10270370A (ja) * 1997-03-26 1998-10-09 Sharp Corp 不純物の拡散方法ならびに半導体装置およびその製造方法
JP4992269B2 (ja) * 2006-03-30 2012-08-08 株式会社日立製作所 電力半導体装置
JP5277882B2 (ja) * 2008-11-12 2013-08-28 富士電機株式会社 半導体装置およびその製造方法
CN101740641B (zh) * 2009-12-24 2012-08-08 杭州立昂电子有限公司 一种半导体器件
JP5641055B2 (ja) * 2010-12-17 2014-12-17 富士電機株式会社 半導体装置およびその製造方法
US8802529B2 (en) * 2011-07-19 2014-08-12 Alpha And Omega Semiconductor Incorporated Semiconductor device with field threshold MOSFET for high voltage termination
JP5628462B1 (ja) * 2012-12-03 2014-11-19 パナソニック株式会社 半導体装置およびその製造方法
CN104600103A (zh) * 2013-10-30 2015-05-06 无锡华润上华半导体有限公司 高压半导体器件、高压半导体器件终端及其制造方法

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EP4207306A4 (en) 2023-10-18
US20230238426A1 (en) 2023-07-27
EP4207306A1 (en) 2023-07-05
JP2023544308A (ja) 2023-10-23
WO2022067750A1 (zh) 2022-04-07

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