CN114585157A - Capacitor-embedded circuit board and manufacturing method thereof - Google Patents
Capacitor-embedded circuit board and manufacturing method thereof Download PDFInfo
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- CN114585157A CN114585157A CN202011388036.3A CN202011388036A CN114585157A CN 114585157 A CN114585157 A CN 114585157A CN 202011388036 A CN202011388036 A CN 202011388036A CN 114585157 A CN114585157 A CN 114585157A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 239000003990 capacitor Substances 0.000 claims abstract description 93
- 238000000034 method Methods 0.000 claims abstract description 60
- 238000003825 pressing Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 238000010030 laminating Methods 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 4
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 238000004891 communication Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 83
- 238000013461 design Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application provides a manufacturing method of a buried capacitor circuit board and the buried capacitor circuit board. The method comprises the following steps: providing a substrate and a buried core plate; the performance parameters of the substrate are lower than those of the embedded capacitor core board, and the embedded capacitor core board is used as a decoupling capacitor; a first accommodating groove is formed in a first preset position of the substrate; and embedding the embedded core plate into the first accommodating groove and pressing. The method effectively improves the flexibility of the arrangement position of the capacitor-embedded core board and effectively reduces the production cost of the capacitor-embedded circuit board.
Description
Technical Field
The invention relates to the technical field of circuit board manufacturing, in particular to a capacitor-embedded circuit board and a manufacturing method thereof.
Background
With the development of electronic products in short, small, light and thin directions, the requirements on the volume of the PCB and the density of electronic components thereon are higher and higher. For this reason, in the process of mounting electronic components on a PCB, an embedded technology, such as an embedded capacitor, is widely used.
At present, in order to improve the utilization rate of the PCB and reduce the stability of signal transmission, the embedded capacitor generally covers a layer of embedded core board on the conductive layer of the PCB to replace the scheme of mounting a capacitor element on the PCB, thereby reducing the volume of the product.
However, since the material of the capacitor-embedded core board is more expensive than that of the common core board, the capacitor-embedded circuit board manufactured by the method has higher cost and lower flexibility of the arrangement position of the capacitor-embedded core board.
Disclosure of Invention
According to the manufacturing method of the capacitor-embedded circuit board and the capacitor-embedded circuit board, the problems that the cost of the capacitor-embedded circuit board manufactured by the existing method is high, and the flexibility of the arrangement position of the capacitor-embedded core board is low can be solved.
In order to solve the technical problem, the application adopts a technical scheme that: a method for manufacturing a buried capacitor circuit board is provided. The method comprises the following steps: providing a substrate and a buried core plate; the performance parameters of the substrate are lower than those of the embedded capacitor core board, and the embedded capacitor core board is used as a decoupling capacitor; a first accommodating groove is formed in a first preset position of the substrate; and embedding the embedded core plate into the accommodating groove and pressing.
In order to solve the above technical problem, another technical solution adopted by the present application is: a buried-capacitor circuit board is provided. This buried capacitor circuit board includes: a substrate and a buried core plate; wherein, the base plate is provided with a containing groove; the embedded core plate is embedded in the accommodating groove; the performance parameters of the substrate are lower than those of the embedded capacitor core plate, and the embedded capacitor core plate is used as a decoupling capacitor.
The manufacturing method of the embedded-capacitor circuit board comprises the steps of providing a substrate and an embedded-capacitor core board, arranging a first accommodating groove at a first preset position of the substrate, embedding the embedded-capacitor core board into the first accommodating groove, and pressing to arrange the embedded-capacitor core board at the first preset position of the substrate; the position of the first accommodating groove is determined according to the first preset position, so that the capacitor-embedded core plate can be arranged at the position of the substrate where the capacitor is required to be arranged according to actual requirements, the capacitor-embedded core plate is not required to be arranged at the position where the capacitor is not required to be arranged, the flexibility of the position where the capacitor-embedded core plate is arranged is improved, the size of the capacitor-embedded core plate is greatly reduced, and the production cost of the capacitor-embedded circuit board is effectively reduced.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a buried-capacitor circuit board according to a first embodiment of the present application;
fig. 2 is a schematic structural diagram of a capacitor-embedded core board according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a product after being processed in step S12 in fig. 1 according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a product after being processed in step S13 in fig. 1 according to an embodiment of the present application;
fig. 5a is a flowchart of a method for manufacturing a buried-capacitor circuit board according to an embodiment of the present application;
FIG. 5b is a schematic diagram of the structure of the product in FIG. 5a after being processed in step S14 according to an embodiment of the present application;
fig. 6 is a flowchart of a method for manufacturing a buried-capacitor circuit board according to a second embodiment of the present application;
fig. 7 is a schematic structural diagram of a product after being processed in step S25 in fig. 6 according to an embodiment of the present application;
fig. 8 is a flowchart of a method for manufacturing a buried-capacitor circuit board according to a third embodiment of the present application;
fig. 9 is a schematic structural diagram of the product after being processed in step S36 in fig. 8 according to an embodiment of the present application;
FIG. 10 is a schematic diagram of the product structure in FIG. 8 after being processed in step S37 according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a product after being processed in step S38 in fig. 8 according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1 to fig. 4, in which fig. 1 is a flowchart of a method for manufacturing a buried capacitor circuit board according to a first embodiment of the present application; fig. 2 is a schematic structural diagram of a capacitor-embedded core board according to an embodiment of the present application; fig. 3 is a schematic structural diagram of a product after being processed in step S12 in fig. 1 according to an embodiment of the present application; fig. 4 is a schematic structural diagram of a product after being processed in step S13 in fig. 1 according to an embodiment of the present application; in this embodiment, a method for manufacturing a capacitive circuit board is provided, where a BGA (Ball Grid Array) region of a PCB board that needs to be subjected to a capacitive circuit design is laminated with a decoupling capacitor core plate material, and a BGA region or other regions that do not need to be subjected to a capacitive circuit design is laminated with a cheap common core plate (FR-4), so that not only can flexibility and high-density interconnectivity of the circuit design be effectively improved, but also material cost can be effectively reduced, and reliability of the capacitor is improved, which has important reference significance for designing and processing the PCB board.
Specifically, referring to fig. 1, the method for manufacturing the buried-capacitor circuit board includes:
step S11: a substrate and a buried capacitor core plate are provided.
The performance parameter of the substrate 11 is lower than that of the embedded core 12, and in one embodiment, the substrate 11 may specifically include at least two layers of core 111, a dielectric layer 112 for bonding two adjacent layers of core 111, and at least one circuit layer (not shown); the core board 111 may be a copper-clad board, and the dielectric layer 112 may be a prepreg.
Wherein, the embedded capacitor core plate 12 is used as a decoupling capacitor; in an embodiment, referring to fig. 2, the embedded core 12 specifically includes a substrate 121, a first metal layer 122a and a second metal layer 122b, wherein the first metal layer 122a and the second metal layer 122b are laminated on opposite sides of the substrate 121, and the lengths of the first metal layer 122a and the second metal layer 122b are the same as the length of the substrate 121; of course, the length of the first metal layer 122a and/or the second metal layer 122b may also be greater than the length of the substrate board 121; in a specific embodiment, a circuit layer is formed on the first metal layer 122a and/or the second metal layer 122 b.
Specifically, the substrate board 121 may include a ceramic material and/or a silicon-based material, and the first metal layer 122a and the second metal layer 122b may be copper layers.
Step S12: a first accommodating groove is formed in a first preset position of the substrate.
Specifically, the structure of the product after the processing of step S12 can be specifically seen in fig. 3; in a specific implementation process, a position of the substrate 11 where a capacitor needs to be disposed may be determined according to the position of the embedded capacitor BGA and the circuit design on the substrate 11, that is, a first preset position of the substrate 11 is determined, and then the first receiving groove 110a is formed in the first preset position. Specifically, the first receiving grooves 110a may be rectangular grooves, and the depth of the first receiving grooves 110a is the same as the thickness of the single-layer core board 111, and it can be understood that in step S12, the first receiving grooves 110a penetrating through the upper and lower surfaces of the core board 111 are substantially formed in the outermost core board 111 of the substrate 11.
Step S13: and embedding the embedded core plate into the first accommodating groove and pressing.
Specifically, the structure of the product processed in step S13 can be specifically seen in fig. 4; in the specific implementation process, after the embedded core 12 is embedded in the first receiving groove 110a, the embedded core 12 and the core 111 with the first receiving groove 110a are nested with each other, and the embedded core 12 is specifically pressed with the dielectric layer 112 in the substrate 11, so that the embedded core 12 and the substrate 11 are bonded together through the dielectric layer 112 to form a nested structure.
Specifically, the number of the embedded core boards 12 is at least two, at least two first accommodating grooves 110a are formed in the substrate 11, and each embedded core board 12 is correspondingly disposed in one first accommodating groove 110 a.
In an embodiment, refer to fig. 5a and fig. 5b, wherein fig. 5a is a flowchart of a method for manufacturing a buried circuit board according to an embodiment of the present application; FIG. 5b is a schematic diagram of the structure of the product in FIG. 5a after being processed in step S14 according to an embodiment of the present application; the method further comprises after step S13:
step S14: and forming a first through hole on the embedded capacity core board and the substrate to conduct the embedded capacity core board and the substrate.
Specifically, the structure of the product after being processed in step S14 can be specifically seen in fig. 5 b; specifically, the first via hole 13a penetrates through the first metal layer 122a, the second metal layer 122b and the at least one core board 111 to communicate the embedded core board 12 and the circuit layer on the substrate 11. It is understood that the first via hole 13a may be a blind hole, a buried hole, or a through hole.
Specifically, step S14 specifically includes punching the embedded core plates 12 and the substrates 11 in the stacking direction of the core plates 111 to form communication holes; in the specific implementation process, the embedded capacitor core plate 12 and the substrate 11 can be drilled in a laser drilling or milling manner by a milling machine; then forming a conductive medium in the via hole to form a first via hole 13 a; specifically, a conductive medium may be filled in the via hole by means of copper deposition, or a conductive medium may be formed on the via hole wall of the via hole by means of plating a metal layer, so as to form the first via hole 13 a; the metal layer may be a copper layer.
Of course, in other embodiments, after the first receiving groove 110a is formed, a first sub-via hole is formed in the substrate 11 at a position corresponding to the first receiving groove 110a, then the embedded core 12 is laminated, a second sub-via hole is formed in the embedded core 12, and the first sub-via hole is communicated with the second sub-via hole to form the first via hole 13a, so as to conduct the circuit layers on the substrate 11 and the embedded core 12.
It can be understood that, in the capacitive buried circuit board 10 manufactured by the method for manufacturing a capacitive buried circuit board provided in the above embodiment, the capacitive buried core 12 is specifically disposed on the outer layer of the capacitive buried core 12, and the structure of the capacitive buried core 12 on the substrate 11 is similar to that of the blind via.
In the manufacturing method of the embedded-capacitor circuit board provided by this embodiment, the substrate 11 and the embedded-capacitor core board 12 are provided, the first accommodating groove 110a is formed in the first preset position of the substrate 11, and then the embedded-capacitor core board 12 is embedded into the first accommodating groove 110a and is pressed, so that the embedded-capacitor core board 12 is arranged at the first preset position of the substrate 11; the position of the first accommodating groove 110a is determined according to the first preset position, so that the capacitor-embedded core board 12 can be set at the position of the substrate 11 where the capacitor is needed according to actual requirements, and the capacitor-embedded core board 12 does not need to be set at the position where the capacitor is not needed, thereby not only improving the flexibility of the setting position of the capacitor-embedded core board 12, but also greatly reducing the volume of the capacitor-embedded core board 12 compared with the scheme of setting the capacitor-embedded core board 12 on the whole surface of the substrate 11, and effectively reducing the production cost of the manufactured capacitor-embedded circuit board 10.
Referring to fig. 6 and fig. 7, fig. 6 is a flowchart illustrating a method for manufacturing a buried capacitor circuit board according to a second embodiment of the present application; fig. 7 is a schematic structural diagram of the product after being processed in step S25 in fig. 6 according to an embodiment of the present application; in this embodiment, another method for manufacturing a buried-capacitor circuit board is provided, which is different from the method for manufacturing a buried-capacitor circuit board provided in the first embodiment described above in that: further laminating at least one core board 111 on the buried core board 12 to form a multilayer board 11'; it can be understood that, in the capacitor-embedded circuit board 10 manufactured by the method for manufacturing a capacitor-embedded circuit board provided in this embodiment, the capacitor-embedded core board 12 is located at an inner layer of the capacitor-embedded circuit board 10. The buried core board 12 has a structure similar to the buried structure of the buried via on the multi-layer board 11'.
Specifically, referring to fig. 6, the method specifically includes:
step S21: a substrate and a buried core board are provided.
Step S22: a first accommodating groove is formed in a first preset position of the substrate.
Step S23: and embedding the embedded core plate into the first accommodating groove and pressing.
Step S24: and forming a first through hole on the embedded capacitor core board and the substrate to conduct the embedded capacitor core board and the substrate.
Specifically, the specific implementation process of the step S21 to the step S24 is the same as or similar to the specific implementation process of the step S11 to the step S14 in the manufacturing method of the capacitor embedded circuit board provided in the first embodiment, and the same or similar technical effects can be achieved.
Step S25: and laminating at least one core board on the embedded core board to form the multilayer board.
In particular, the specific structure of the multilayer sheet 11' can be seen in fig. 7; the number of lamination layers of the core board 111 may be specifically determined according to the requirement of the actual circuit design, which is not limited in this embodiment; specifically, in the lamination process, the laminations between two adjacent core boards 111 and between the core board 111 and the embedded core board 12 are specifically bonded through the dielectric layer 112, and the dielectric layer 112 may be a prepreg.
Of course, in other embodiments, after step S22, a first sub-via hole is opened at a position of the substrate 11 corresponding to the first receiving groove 110a, and then step S23 is executed to open a second sub-via hole on the embedded core board 12, and the first sub-via hole is communicated with the second sub-via hole to form a first via hole 13a for conducting the circuit layers on the substrate 11 and the embedded core board 12; and then directly performs step S25.
Compared with the method for manufacturing the capacitor-embedded circuit board provided by the first embodiment, the method for manufacturing the capacitor-embedded circuit board provided by the embodiment can not only improve the flexibility of the arrangement position of the capacitor-embedded core board 12, but also effectively reduce the production cost of the manufactured capacitor-embedded circuit board 10; and through further laminating at least one layer of core board 111 on the embedded capacitor core board 12, the embedded capacitor core board 12 can be positioned at any required inner layer position of the multilayer board 11' according to the actual circuit design, the structure is flexible, the application is wide, and meanwhile, the embedded capacitor core board 12 can be protected while the decoupling effect is realized.
Referring to fig. 8, fig. 8 is a flowchart illustrating a method for manufacturing a buried capacitor circuit board according to a third embodiment of the present application; in this embodiment, there is provided another method for manufacturing a buried-capacitor circuit board, which is different from the method for manufacturing a buried-capacitor circuit board provided in the second embodiment described above in that: a second accommodating groove 110b is further formed in a second preset position on the multilayer board 11'; then, one of the embedded core boards 12 is embedded into the second accommodating groove 110b and pressed; it can be understood that, in the capacitor-embedded circuit board 10 manufactured by the method for manufacturing a capacitor-embedded circuit board provided in this embodiment, the capacitor-embedded core boards 12 are located at the inner layer and the outer layer of the capacitor-embedded circuit board 10, and the structure of the capacitor-embedded core boards 12 on the multilayer board 11' is similar to the capacitor-embedded structure of the blind hole and the buried hole combination.
Specifically, referring to fig. 8, the method includes:
step S31: a substrate and a buried core board are provided.
Step S32: a first accommodating groove is formed in a first preset position of the substrate.
Step S33: and embedding the embedded core plate into the first accommodating groove and pressing.
Step S34: and forming a first through hole on the embedded capacitor core board and the substrate to conduct the embedded capacitor core board and the substrate.
Step S35: and laminating at least one core board on the embedded core board to form the multilayer board.
Specifically, the specific implementation process of the step S31 to the step S35 is the same as or similar to the specific implementation process of the step S21 to the step S25 in the manufacturing method of the capacitor embedded circuit board provided in the second embodiment, and the same or similar technical effects can be achieved.
Step S36: and a second accommodating groove is formed in a second preset position on the multilayer board.
Specifically, the structure of the product after the processing in step S36 can be seen in fig. 9, and fig. 9 is a schematic view of the structure of the product after the processing in step S36 in fig. 8 according to an embodiment of the present disclosure; specifically, the specific implementation process of forming the second receiving groove 110b in the multilayer board 11' is the same as or similar to the specific implementation process of step S12 in the method for manufacturing a buried-capacitor circuit board provided in the first embodiment, and the same or similar technical effects can be achieved.
Step S37: and embedding one of the embedded core plates into the second accommodating groove and pressing.
Specifically, the structure of the product processed in step S37 can be seen in fig. 10, and fig. 10 is a schematic view of the structure of the product processed in step S37 in fig. 8 according to an embodiment of the present disclosure. Specifically, the specific implementation process of step S37 is the same as or similar to the specific implementation process of step S13 in the method for manufacturing a capacitor-embedded circuit board provided in the first embodiment, and the same or similar technical effects can be achieved.
Step S38: and forming a second through hole on the embedded core board and the multilayer board so as to conduct the embedded core board and the multilayer board.
Specifically, the structure of the product after the processing in step S38 can be seen in fig. 11, and fig. 11 is a schematic view of the structure of the product after the processing in step S38 in fig. 8 according to an embodiment of the present disclosure. Specifically, the specific implementation process of opening the second via hole 13b is the same as or similar to the specific implementation process of step S14 in the manufacturing method of the capacitor embedded circuit board provided in the first embodiment, and the same or similar technical effects can be achieved. It will be appreciated that the second via hole 13b is used to communicate the newly embedded buried core board 12 with the wiring layer on the multilayer board 11'.
It is understood that, in this embodiment, after the first receiving groove 110a (the second receiving groove 110b) is formed, the first sub-via hole is formed at a position of the substrate 11 corresponding to the first receiving groove 110a (the second receiving groove 110b), then the embedded core board 12 is laminated, the second sub-via hole is formed on the embedded core board 12, and the first sub-via hole is communicated with the second sub-via hole to form the first via hole 13a (the second via hole 13b), so as to conduct the circuit layer on the substrate 11 and the embedded core board 12.
It should be noted that, in the specific implementation process, the step S35 may be executed again according to the actual circuit design and the layer number requirement of the buried capacitor circuit board 10, so as to meet the actual production requirement of the buried capacitor circuit board 10.
Compared with the method for manufacturing the embedded capacitor circuit board provided by the second embodiment, the method for manufacturing the embedded capacitor circuit board provided by the embodiment is provided; further, a second accommodating groove 110b is formed in a second preset position on the multilayer board 11', one of the embedded core boards 12 is embedded into the second accommodating groove 110b and pressed, so that the multilayer board 11' can design the embedded core boards 12 on the inner layer and the outer layer of a circuit at the same time according to the requirement of actual circuit design, and the embedded circuit board 10 is more flexible and wide in structure while the high-density interconnection design of the embedded technology is realized; thereafter, second via holes 13b are formed in the buried core board 12 and the multilayer board 11 'to communicate the newly embedded buried core board 12 with the wiring layer on the multilayer board 11'.
With continued reference to fig. 5b, fig. 7 and fig. 11, in the present embodiment, a buried circuit board 10 is provided. The buried capacitor circuit board 10 has high flexibility in circuit design, high density interconnection, low production cost and high capacitor reliability.
Specifically, the buried capacitor circuit board 10 includes a substrate 11 and a buried capacitor core board 12.
Wherein, the performance parameter of the substrate 11 is lower than that of the embedded core board 12; the substrate 11 is provided with a receiving groove, and the embedded core board 12 is embedded in the receiving groove to cooperate with the substrate 11 to form the embedded circuit board 10. The receiving grooves may be specifically the first receiving groove 110a and/or the second receiving groove 110b in the above embodiments, and the specific positions thereof may be determined according to the embedded-capacitor BGA and the circuit design position, so that the embedded-capacitor core board 12 can be set only at the position of the substrate 11 where the capacitor needs to be set according to the actual requirement, and the embedded-capacitor core board 12 does not need to be set at the position where the capacitor does not need to be set, which not only improves the flexibility of the setting position of the embedded-capacitor core board 12, but also greatly reduces the volume of the embedded-capacitor core board 12 compared with the scheme of setting the embedded-capacitor core board 12 on the whole surface of the substrate 11, and effectively reduces the production cost of the embedded-capacitor circuit board 10.
In an embodiment, the number of the embedded core boards 12 is at least two, at least two receiving slots are formed on the substrate 11, and each embedded core board 12 is correspondingly disposed in one receiving slot.
The substrate 11 may specifically include at least two core boards 111 stacked together, a dielectric layer 112 for bonding the two adjacent core boards 111, and at least one circuit layer; the core board 111 may be a copper-clad board, and the dielectric layer 112 may be a prepreg. The depth of the receiving groove on the substrate 11 may be the same as the thickness of the single-layer core board 111.
In an embodiment, the receiving slot is located at an outer layer of the substrate 11, and at this time, the embedded core board 12 is located on the core board 111 at the outer layer of the substrate 11 and is nested with the core board 111 at the outer layer, and a specific structure of the embedded circuit board 10 provided in this embodiment can be seen in fig. 5 b; in another embodiment, the accommodating groove is located on the core 111 of the inner layer of the substrate 11, and at this time, the embedded core 12 is located in the inner layer of the substrate 11 and is nested with the core 111 of the inner layer of the substrate 11, and the specific structure of the embedded circuit board 10 provided in this embodiment can be seen in fig. 7; in another embodiment, the core 111 of the outer layer and the core 111 of the inner layer of the substrate 11 are both provided with receiving slots, and at this time, the embedded core 12 is embedded in both the outer layer and the inner layer of the substrate 11, that is, a part of the embedded core 12 is embedded in the core 111 of the outer layer of the substrate 11, and a part of the embedded core 12 is embedded in the core 111 of the inner layer of the substrate 11; specifically, the embodiment provides a specific structure of the buried wiring board 10, which can be seen in fig. 11.
Wherein, the embedded capacitor core plate 12 is used as a decoupling capacitor; in an embodiment, referring to fig. 2, the embedded core 12 specifically includes a substrate 121, a first metal layer 122a and a second metal layer 122b, wherein the first metal layer 122a and the second metal layer 122b are laminated on opposite sides of the substrate 121, and the lengths of the first metal layer 122a and the second metal layer 122b are the same as the length of the substrate 121; of course, the length of the first metal layer 122a and/or the second metal layer 122b may also be greater than the length of the substrate board 121; in a specific embodiment, a circuit layer is formed on the first metal layer 122a and/or the second metal layer 122 b.
Specifically, the substrate board 121 may include a ceramic material and/or a silicon-based material, and the first metal layer 122a and the second metal layer 122b may be copper layers.
In the embodiment, the substrate 11 and the embedded core 12 are further provided with via holes, and the via holes penetrate through the first metal layer 122a, the second metal layer 122b and the at least one core 111 to communicate the embedded core 12 and the circuit layer on the substrate 11. Specifically, the via holes may be the first via hole 13a and the second via hole 13b in the above embodiments.
Specifically, the via hole comprises a first sub-via hole and a second sub-via hole which are mutually communicated; the first sub-via hole penetrates through the first metal layer 122a and the second metal layer 122b, and the second sub-via hole penetrates through at least one core board 111 and is electrically connected to the circuit layer on the substrate 11. Specifically, the second sub via hole extends from the bottom of the accommodating groove toward a direction away from the embedded core plate 12 along the stacking direction of the core plates 111; the second via hole 13b may be a blind hole or a through hole, which is not limited in this embodiment and can be selected according to the actual circuit design. In one embodiment, the central axes of the first sub via hole and the second sub via hole are the same; of course, in other embodiments, the central axes of the first sub via hole and the second sub via hole may be offset, and this embodiment is not limited thereto as long as the embedded core board 12 and the circuit layer on the substrate 11 can be communicated with each other.
In the capacitance-embedded circuit board 10 provided by this embodiment, by arranging the substrate 11 and the capacitance-embedded core board 12, the accommodating groove is formed in the substrate 11, and the capacitance-embedded core board 12 is embedded in the accommodating groove, so that the capacitance-embedded core board 12 can be arranged only at a position of the substrate 11 where a capacitor needs to be arranged according to actual requirements, and the capacitance-embedded core board 12 does not need to be arranged at a position where a capacitor does not need to be arranged, which not only improves the flexibility of the arrangement position of the capacitance-embedded core board 12, but also greatly reduces the volume of the capacitance-embedded core board 12 compared with a scheme in which the capacitance-embedded core board 12 is arranged on the whole surface of the substrate 11, and effectively reduces the production cost of the capacitance-embedded circuit board 10; meanwhile, the substrate 11 and the capacitor-embedded circuit board 10 are electrically connected by forming via holes in the substrate 11 and the capacitor-embedded core 12.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (13)
1. A manufacturing method of a buried circuit board is characterized by comprising the following steps:
providing a substrate and a buried core plate; the performance parameters of the substrate are lower than those of the embedded capacitor core plate, and the embedded capacitor core plate is used as a decoupling capacitor;
a first accommodating groove is formed in a first preset position of the substrate;
and embedding the embedded core board into the first accommodating groove and pressing.
2. The method of claim 1, wherein the number of the capacitor-embedded core boards is at least two, the substrate is provided with at least two first receiving slots, and each capacitor-embedded core board is correspondingly disposed in one of the first receiving slots.
3. The method of claim 1 or 2, wherein the capacitor-embedded core board comprises a substrate board, a first metal layer and a second metal layer; the first metal layer and the second metal layer are laminated on two opposite sides of the substrate plate; the substrate comprises at least two layers of core boards and at least one circuit layer which are arranged in a stacked mode, and the via hole penetrates through the first metal layer, the second metal layer and the at least one layer of core board to communicate the embedded core board with the circuit layer on the substrate.
4. The method of claim 3, wherein the substrate board comprises a ceramic material and/or a silicon-based material.
5. The method of manufacturing a capacitor-embedded circuit board according to claim 1, wherein after the step of embedding the capacitor-embedded core board in the first receiving groove and performing the press-fitting, the method further comprises: laminating at least one core board on the buried core board to form a multilayer board.
6. The method of claim 5, wherein the step of laminating at least one core board on the capacitor core board to form a multi-layer board further comprises:
a second accommodating groove is formed in a second preset position on the multilayer board;
and embedding one embedded core board into the second accommodating groove and pressing.
7. The method of claim 5, wherein after the step of inserting and pressing the capacitive core board into the first receiving slot, and before the step of laminating at least one core board on the capacitive core board to form a multi-layer board, the method further comprises:
and forming a first through hole on the embedded capacitor core plate and the substrate so as to conduct the embedded capacitor core plate and the substrate.
8. The method of claim 7, wherein the step of forming the first via holes in the capacitor-embedded core board and the substrate comprises:
perforating the embedded core plate and the substrate along the lamination direction of the core plates to form communicating holes;
and forming a conductive medium in the communication hole.
9. A buried-capacitor circuit board, comprising:
a substrate provided with a containing groove;
the embedded core plate is embedded in the accommodating groove;
and the performance parameter of the substrate is lower than that of the embedded capacitor core plate, and the embedded capacitor core plate is used as a decoupling capacitor.
10. The circuit board of claim 9, wherein the number of the capacitor-embedded core boards is at least two, at least two of the receiving slots are formed in the substrate, and each of the capacitor-embedded core boards is disposed in one of the receiving slots.
11. The buried capacitor wiring board of claim 9 or 10, wherein the buried capacitor core board comprises a substrate board, a first metal layer, and a second metal layer; the first metal layer and the second metal layer are laminated on two opposite sides of the substrate plate; the substrate comprises at least two layers of core plates and at least one circuit layer which are arranged in a stacked mode; and the substrate and the capacitor-embedded core board are provided with via holes, and the via holes penetrate through the first metal layer, the second metal layer and at least one layer of core board so as to communicate the capacitor-embedded core board and the circuit layer on the substrate.
12. The buried via board of claim 11, wherein the via hole includes a first sub-via hole and a second sub-via hole that are in conduction with each other; the first sub-via hole penetrates through the first metal layer and the second metal layer, and the second sub-via hole penetrates through at least one layer of the core board and is communicated with the circuit layer on the substrate.
13. The buried circuit board of claim 9 or 10, wherein the substrate comprises at least two layers of core boards arranged in a stack; the accommodating groove is positioned on the core board at the outer layer and/or the core board at the inner layer of the substrate.
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| CN202011388036.3A CN114585157A (en) | 2020-12-01 | 2020-12-01 | Capacitor-embedded circuit board and manufacturing method thereof |
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| CN202011388036.3A CN114585157A (en) | 2020-12-01 | 2020-12-01 | Capacitor-embedded circuit board and manufacturing method thereof |
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