KR100547350B1 - Method of manufacturing multi-layer printed circuit board in parallel - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of connecting via holes, which serve to electrically connect a circuit layer and an insulating layer in a method of manufacturing a parallel multilayer printed circuit board, wherein the connecting layer is connected to an insulating layer among plating layers filling the via holes of the circuit layer. It relates to a method for improving the reliability of the electrical connection between the circuit layer and the insulating layer by forming the circuit layer connection portion, which is a portion, to be smaller than the insulation layer connection portion, which is a portion which is connected to the circuit layer among the fillers filling the via holes of the insulating layer. .

In the parallel multilayer printed circuit board manufacturing method according to the present invention, A. processing a through-hole in the copper-clad laminate, plating the inner wall of the copper-clad laminate and the through-hole by copper plating and filling the inside of the through-hole by a plating layer And forming a circuit pattern on the copper-clad laminate, the circuit pattern including a circuit layer connection part, which is a part of the plating layer connected to an insulating layer. B. processing a through-hole having a diameter larger than the diameter of the circuit layer connection portion to the plate-shaped insulating material to which the release film is attached, filling the through-hole with a conductive filler, and removing the release film. Forming an insulating layer; C. disposing the formed circuit layer and the insulating layer alternately in a predetermined position; And D. compressing the disposed circuit layer and the insulating layer, wherein the circuit layer connecting portion is an insulating portion which is connected to the circuit layer in the conductive filler filling the through hole of the insulating layer by the pressing step. It is characterized in that it is embedded in the layer connection.

Parallel, Printed Circuit Board, Via Hole, Circuit Layer, Insulation Layer, Connections

Description

Method of manufacturing multi-layer printed circuit board in parallel

1A to 1D show a method of manufacturing a circuit layer in a conventional parallel multilayer printed circuit board manufacturing method.

2A to 2D illustrate a method of forming an insulating layer among layers constituting a multilayer printed circuit board in a conventional parallel multilayer printed circuit board manufacturing method.

3 illustrates a state in which circuit layers and insulating layers are alternately arranged in a conventional parallel multilayer printed circuit board manufacturing method.

4 is a cross-sectional view of a printed circuit board completed by pressing the substrates arranged in FIG.

Fig. 5 shows a cross section of a circuit layer manufactured according to the conventional method shown in Figs. 1A to 1D.

6A to 6D illustrate a method of manufacturing a circuit layer in a method of manufacturing a parallel multilayer printed circuit board according to the present invention.

7A to 7D illustrate a method of manufacturing an insulating layer in a method of manufacturing a parallel multilayer printed circuit board according to the present invention.

8 illustrates a state in which circuit layers and insulating layers are alternately arranged in the method of manufacturing a parallel multilayer printed circuit board of the present invention.

9 is a cross-sectional view of a printed circuit board completed by pressing the substrates arranged in FIG.

Fig. 10 shows a cross section of a circuit layer manufactured according to the method of the present invention shown in Figs. 6A-6D.

※ Description of the main parts of the drawings

606,606a, 606b, 606c: circuit layer

707,707a, 707b: insulation layer

607,607a, 607b, 607c, 607d: circuit layer connection

708,708a, 708b, 708c, 708d: Insulation layer connection

The present invention relates to a method for improving the reliability of an electrical connection between a circuit layer and an insulating layer in the manufacture of a parallel multilayer printed circuit board. More specifically, the present invention relates to a method of connecting via holes, which serve to electrically connect the circuit layer and the insulating layer in a so-called parallel multilayer printed circuit board manufacturing method, and among the plating layers filling the via holes of the circuit layer. Improving the reliability of the electrical connection between the circuit layer and the insulating layer by forming the circuit layer connecting portion, which is a portion to be connected with the insulating layer, to be smaller than the insulating layer connecting portion, which is the portion to be connected to the circuit layer among the fillers filling the via holes of the insulating layer. It is about a method.

As electronic products become smaller and thinner, thinner, denser, more compact, and smaller in size, more and more, multilayer printed circuit boards are also undergoing fine patterns, miniaturization, and packaging. Accordingly, in order to increase the micropattern formation, reliability, and design density of multilayer printed circuit boards, there is a tendency to change the structure of the multilayer structure of the circuit together with the change of raw materials, and the parts are also SMT (Dual In-Line Package) type. As the surface mount technology type is changed, the mounting density is also increasing. In addition to the portableization of electronic devices, high functionalization, the Internet, moving pictures, and high-capacity data transmission and reception make the design of printed circuit boards complicated and require high-level technology.

A power supply circuit, a ground circuit, a signal circuit, and the like are formed in the inner layer of the multilayer printed circuit board, and a preplex is sandwiched between the inner layer and the outer layer or the outer layer to insulate and bond. At this time, the wiring of each layer is connected using a via hole (conducting hole).

Conventionally, a so-called build-up method of manufacturing a laminate of additional insulating layers and circuit layers, starting with a double-sided printed circuit board, has been used, but recently, the required number of insulating layers and circuit layers in parallel are respectively used. A so-called parallel manufacturing method or batch lamination method has emerged, which is completed and then compressed at once.

1A-1D, 2A-2D, 3 and 4 illustrate a conventional method for manufacturing a parallel multilayer printed circuit board.

1A to 1D show a method of manufacturing a circuit layer in a conventional parallel multilayer printed circuit board manufacturing method.

FIG. 1A shows a conventional copper clad laminate 101, in which copper foil 302 is coated on both sides of insulating layer 103.

In Fig. 1B, a fine through hole 104 is machined into a copper clad laminate. Through-holes are machined to diameters of 50-100 µm using YAG or CO2 lasers and mechanical drilling.

In Fig. 1C, the inner surface of the upper surface, the lower surface, and the inner wall of the through hole are plated by electroless plating and electrolytic plating on the copper-clad laminated plate processed with the through hole. As shown in FIG. 1C, the plating layer 105 is formed on the upper surface, the lower surface, and the inner wall of the through hole of the substrate, and the fine through hole 104 is filled by the plating layer 105 without a separate plugging (filling) process.

In addition to the method of filling the through hole 104 by plating as described above, there is also a method of filling the remaining space with insulating ink after plating the inner wall by electroless plating and electrolytic plating, and without electroless plating and electroplating. There is also a method of filling the inner wall of the through hole with a conductive ink.

In Fig. 1D, a circuit pattern is formed using a circuit pattern forming method such as etching. The circuit layer 106 thus formed may be used as a circuit layer in a parallel printed circuit board manufacturing method.

2A to 2D illustrate a method of forming an insulating layer among layers constituting a multilayer printed circuit board in a conventional parallel multilayer printed circuit board manufacturing method.

2A shows a planar insulating material 201 with a release film 202 attached to both sides of the preplex 203. The thickness of the prepreg can be selectively used according to the specification of the product. The thickness of the release film is 20-30 μm, and may be one already attached at the time of prepreg fabrication, and in some cases, the release film may be adhered.

In FIG. 2B, the through hole 204 is machined by drilling into the flat insulating material 201. At this time, the through hole preferably uses mechanical drilling.

In FIG. 2C, the through hole 204 is filled with paste 205, and in FIG. 2D, the release film 202 is removed.

The circuit layer 206 thus formed is used as an insulating layer in a parallel printed circuit board manufacturing method.

As the material of the insulating layer 201, a release film 202 may be laminated on the single-layer insulating material 203 shown in FIG. 2A, but a fully cured state (c-stage) may be used instead of the insulating material 203. The thermosetting resin of the semi-cured state (b-stage) is laminated | stacked on both surfaces of the thermosetting resin of the above, and what bonded the release film on it can also be used.

In Fig. 3, a predetermined number of circuit layers 106a, 106b and 106c formed by the method shown in Figs. 1A to 1 and a predetermined number of insulating layers formed by the method shown in Figs. 2A to 2A to 2D. 206a and 206b are alternately arranged.

Targeting the placed layers or The circuit layer connecting portion 107 and the insulating layer connecting portion 207 are precisely matched by a pin method or the like.

Then, as shown in Fig. 3, the arranged circuit layer and the insulating layer are pressed in the direction of the arrow shown by the compression press to complete the six-layer multilayer printed circuit board as shown in Fig. 4.

3 and 4, since the circuit layer connecting portion 107 is filled by electroplating and made of copper, and the insulating layer connecting portion 207 is filled with conductive ink, the circuit layer connecting portion 107 When the insulating layer connecting portion 207 is connected, the insulating layer connecting portion 207 is pressed against the circuit layer connecting portion 107 as shown in 401 due to the difference in hardness. That is, in the conventional multilayer printed circuit board manufacturing method, the circuit layer connection part 107 is processed widely, and is connected, pressing the insulating layer connection part 207.

Fig. 5 shows a cross section of a circuit layer manufactured according to the conventional method shown in Figs. 1A to 1D. The diameter of the via hole is typically processed to about 100 μm. Accordingly, the diameters of the circuit layer connecting portions 501 and 503 become about 250 μm, and the diameter of the circuit pattern 502 of the portion not connected to the insulating layer connecting portion is limited to about 50 μm or less, and the gap between the via holes is also limited. Since it cannot be narrowed, it becomes an obstacle to the densification of the circuit.

In the conventional parallel multilayer printed circuit board manufacturing, there is a need for a method that can improve the design freedom by improving the reliability of the electrical connection between the circuit layer and the insulating layer and narrowing the via hole spacing.

SUMMARY OF THE INVENTION An object of the present invention is a printed circuit manufactured by a parallel multilayer printed circuit board manufacturing method by increasing the contact cross-sectional area of a circuit layer connecting portion and an insulating layer connecting portion connecting a circuit layer and an insulating layer in a parallel multilayer printed circuit board manufacturing method. It is to improve the reliability of the electrical connection through the interlayer via hole of the substrate.

Another object of the present invention is to reduce the area occupied by a circuit layer connection portion connected to an insulating layer on a circuit layer in a method of manufacturing a parallel multilayer printed circuit board, thereby securing an area in which a circuit pattern can be designed, and printing with higher density. It is to provide a circuit board manufacturing method.

In the parallel multilayer printed circuit board manufacturing method according to the present invention, A. processing a through-hole in the copper-clad laminate, plating the inner wall of the copper-clad laminate and the through-hole by copper plating and filling the inside of the through-hole by a plating layer And forming a circuit pattern on the copper-clad laminate, the circuit pattern including a circuit layer connection part, which is a part of the plating layer connected to an insulating layer. B. processing a through-hole having a diameter larger than the diameter of the circuit layer connection portion to the plate-shaped insulating material to which the release film is attached, filling the through-hole with a conductive filler, and removing the release film. Forming an insulating layer; C. disposing the formed circuit layer and the insulating layer alternately in a predetermined position; And D. compressing the disposed circuit layer and the insulating layer, wherein the circuit layer connecting portion is an insulating portion which is connected to the circuit layer in the conductive filler filling the through hole of the insulating layer by the pressing step. It is characterized in that it is embedded in the layer connection.

A multilayer printed circuit board according to the present invention includes a predetermined number of circuit layers having through-holes filled by plating and having a circuit pattern formed thereon; And a predetermined number of insulating layers stacked between the predetermined number of circuit layers and having a through hole filled with a conductive filler, wherein the circuit is a part connected to the insulating layer among the plating layers filling the through holes of the circuit layer. The layer connection part may be embedded in an insulation layer connection part, which is a part connected to the circuit layer among the fillers filling the through holes of the insulating layer.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

6A to 6D, 7A to 7D, 8 and 9 illustrate a method of manufacturing a multilayer printed circuit board according to the present invention.

6a to 6d illustrate a method of manufacturing a circuit layer in a method of manufacturing a parallel multilayer printed circuit board according to the present invention.

6A shows a copper foil laminated plate 601 in which copper foil 602 is coated on both surfaces of the insulating layer 603.

In Fig. 6B, via holes 604 are processed in the copper clad laminate 601. Figs. The via hole 604 is processed to a diameter of 50-100 μm using a YAG or CO 2 laser and mechanical drilling.

In Fig. 6C, both surfaces of the copper-clad laminate 601 and the inner wall of the via hole 604 are copper plated, where the via hole 604 is embedded by plating.

Then, circuit patterns are formed on both surfaces of the copper clad laminate 601 as shown in FIG. 6D. In the present invention, the copper plating layer plated inside the via hole 604 is electrically connected to the conductive filler filled in the via hole of the insulating layer when the insulating layer is combined with the insulating layer. 607 is formed to be equal to or smaller than the diameter of the via hole 604.

7A to 7D illustrate a method of manufacturing an insulating layer in a method of manufacturing a parallel multilayer printed circuit board according to the present invention.

The insulating layer substrate 701 of FIG. 7A has an insulating layer in which a thermosetting resin layer 703 in a semi-cured state is laminated on both surfaces of a thermosetting resin layer 702 in a fully cured state (c-stage). The release film 704 is adhered on it.

The thickness of the thermosetting resin layers 702 and 703 may be selectively used according to the specifications of the product. The thickness of the release film 704 may be 20-30 μm, and a product that is already attached at the time of manufacturing the thermosetting resin layers 702 and 703 may be used. It may be used by adhering the release film through a separate process.

In Fig. 7B, the through hole 705 is processed by drilling into the substrate 701 for insulating layer. At this time, the through hole is made larger than the diameter of the circuit layer via hole 604 processed in Fig. 6B, and when the circuit layer connecting portion 607 and the insulating layer connecting portion 708 are joined, the circuit layer connecting portion 607 is insulated by crimping. The processing is large enough to be embedded in the layer connection 708. The through hole 705 is preferably machined using mechanical drilling.

In FIG. 7C, the inside of the through hole 705 is filled with the conductive paste 706. Although the conductive paste 706 has conductivity, even if cured, its hardness is lower than that of metal.

In FIG. 7D, the release film 704 is removed.

The insulating layer 707 thus formed is used as an insulating layer in a method of manufacturing a parallel printed circuit board.

As a material of the insulating layer substrate 701, a semi-cured thermosetting resin layer 703 is laminated on both surfaces of the fully cured (c-stage) thermosetting resin layer 702 shown in Fig. 7A. Instead of using the used one, one composed of a single layer of insulating material may be used.

In Fig. 8, circuit layers 606a, 606b and 606c manufactured by the method shown in Figs. 6A to 6D and insulating layers 707a and 707b manufactured by the method shown in Figs. 7A to 7D are shown. Alternately.

The arranged layers are aligned so that the circuit layer connections 607a, 607b, 607c, and 607d and the insulating layer connections 708a, 708b, 708c and 708d are accurately matched by a method such as targeting or a pin method.

Targeting is the process of drilling the target hole in the 'target guide mark' of the inner layer, which is the reference point for drilling, and usually uses a target drill by X-ray.

In the case of the pin method, when the hole, which is the standard of interlayer matching, is processed and laminated at the same position before drilling, the circuit layer and the insulating layer where the hole is processed are inserted into the pin to insert the circuit layer and the insulating layer. The way of matching.

Then, as shown in Fig. 8, the arranged circuit layer and the insulating layer are pressed using a compression press in the direction of the arrow shown to complete a six-layer multilayer printed circuit board as shown in Fig. 9.

Heat presses are often used as presses that compress each stacked layer into a single printed circuit board. This is carried out by stacking the stacked substrates in a case and pressing / heating them by placing them on a hot plate above and below the vacuum chamber. This method is called VHL (Vacuum Hydraulic Lamination) method.

In addition, there is also a vacuum press in which a heat transfer source is installed in a vacuum chamber as a heating source and laminated in a pressurized state using gas. Since this method does not require a hot plate, regardless of the number of layers, for example, six layers, eight layers, and ten layers can be laminated at once, which is advantageous for small quantity production.

8 and 9, circuit layer connection parts 607a, 607b, 607c, and 607d are filled by electroplating, and are made of copper, and insulating layer connection parts 708a, 708b, 708c, and 708d are conductive inks. Is filled, the circuit layer connection portion 107 is insulated due to the difference in hardness when the circuit layer connection portions 607a, 607b, 607c and 607d and the insulation layer connection portions 708a, 708b, 708c and 708d are connected. It is harder than the connecting portions 708a, 708b, 708c and 708d, and the diameter of the insulating layer connecting portion is larger than that of the circuit layer connecting portion as described above. Is connected to the insulating layer connection portions 708a, 708b, 708c, and 708d.

Comparing the cross-sectional views of Figs. 4 and 9, the circuit layer connection portion and the insulation layer connection portion of the printed circuit board manufactured according to the method of the present invention of Fig. 9 are connected by a larger surface area than in the conventional method of Fig. 4, so that the electrical connection Stable and reliable in

Fig. 10 shows a cross section of a circuit layer manufactured according to the method of the present invention shown in Figs. 6A-6D. The diameter of the filled via hole is usually processed to about 100 mu m, and the diameters of the circuit layer connection portions 1001 and 1003 are also processed to about 100 mu m.

Compared with the cross-sectional view shown in FIG. 5, in FIG. 10, since the gap between the filled via holes can be secured, there are many circuit patterns 1002 having a width of about 50 μm between the via holes, compared to the prior art. The number can be designed, and the spacing between these circuit patterns 1002 and the filled via holes can also be secured up to about 75 μm, which improves the design freedom of the circuit as compared with the conventional invention. Therefore, it is advantageous for high density integrated circuit design.

According to the present invention, in the so-called parallel multilayer printed circuit board manufacturing method, a printed circuit manufactured by the parallel multilayer printed circuit board manufacturing method by increasing the contact cross-sectional area connecting the circuit layer and the insulating layer and the contact layer area of the insulating layer connecting portion. It is possible to improve the reliability of the electrical connection through the interlayer via holes of the substrate.

In addition, according to the present invention, the object is to reduce the area of the circuit layer layer via hole connection in the parallel multilayer printed circuit board manufacturing method, to secure the area in which the circuit pattern can be designed, and to manufacture a higher density printed circuit board. .

Claims (10)

A. processing through-holes in copper-clad laminate, Plating the inner wall of the copper clad laminate and the through hole by copper plating, and filling the inside of the through hole with a plating layer; and Forming a circuit pattern on the copper-clad laminate including a circuit layer connection portion which is a portion of the plating layer that is connected to an insulating layer; B. processing through-holes having a diameter larger than that of the circuit layer connection part in a flat plate insulating material having a release film attached thereto; Filling the through hole with a conductive filler, and Forming an insulating layer including removing the release film; C. disposing the formed circuit layer and the insulating layer alternately in a predetermined position; And D. pressing the disposed circuit layer and insulating layer, And the circuit layer connecting portion is embedded in an insulating layer connecting portion which is a portion of the conductive filler filling the through hole of the insulating layer and connected to the circuit layer by the pressing step. The method of claim 1, wherein the diameter of the circuit layer connection portion is equal to or smaller than the diameter of the through hole. The method of claim 1, wherein the disposing of the C. circuit layer and the insulating layer comprises: And precisely aligning the circuit layer connection part and the insulating layer connection part by targeting the arranged circuit layer and the insulating layers by a pin method or a pin method. The method of claim 1, wherein a diameter of the through hole of the circuit layer is 50-100 μm. The parallel multilayer printed circuit board of claim 1, wherein the planar insulating material comprises a resin layer in a semi-cured state (b-stage) laminated on both sides of a resin in a fully cured state. Way. The method of claim 1, wherein a distance between the through holes of the circuit layer is 0.4 mm or less. A predetermined number of circuit layers having through holes filled by plating and in which circuit patterns are formed; And And a predetermined number of insulating layers having a through hole filled with a conductive filler and stacked between the predetermined number of circuit layers, The circuit layer connecting portion, which is a portion of the plating layer filling the through hole of the circuit layer, is connected to the insulating layer, and is buried by pressing the insulating layer connecting portion, which is a portion connected to the circuit layer, of the filler filling the through hole of the insulating layer. Multilayer printed circuit board, characterized in that. The multilayer printed circuit board of claim 7, wherein a diameter of the circuit layer connection portion is equal to or smaller than a diameter of the through hole of the circuit layer. The multilayer printed circuit board of claim 7, wherein a distance between the through holes of the circuit layer is 0.4 mm or less. The method according to claim 1 or 7, The insulating layer connection portion is a multilayer printed circuit board, characterized in that the hardness is lower than the circuit layer connection portion.

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