CN114582959B - Groove type power MOS device and manufacturing method thereof - Google Patents
Groove type power MOS device and manufacturing method thereof Download PDFInfo
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- CN114582959B CN114582959B CN202210483500.XA CN202210483500A CN114582959B CN 114582959 B CN114582959 B CN 114582959B CN 202210483500 A CN202210483500 A CN 202210483500A CN 114582959 B CN114582959 B CN 114582959B
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
The invention provides a trench type power MOS device and a manufacturing method thereof.A substrate at the outer side of a terminal trench at the outermost side of a terminal region is additionally provided with at least one doped region at the required depth, the doped region is doped with impurities of a second conduction type, the net doped conduction type of the doped region is a first conduction type, the depletion width near the terminal trench at the outermost side and the curvature radius of the boundary line of a depletion region can be optimized, so that the distance between a depletion boundary line and the terminal trench at the outermost side of the terminal region is enough, the electric field distribution is changed, the impact ionization rate is reduced, and the withstand voltage of the terminal structure of the device and the reliability of the whole device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a groove type power MOS device and a manufacturing method thereof.
Background
The improvement of device performance and the reduction of cost are important issues in the design and manufacture of Trench (Trench) type power MOS (Metal Oxide Semiconductor) devices. The terminal structure not only directly affects the device performance of the trench type power MOS device, but also plays an important role in reducing the cost as an important component of the trench type power MOS device.
At present, the size of the trench of the termination structure of the trench power MOS device is usually designed to be consistent with the cell region, so as to avoid additional process steps in the manufacturing process of the termination structure and reduce the cost, but at present, the withstand voltage of the termination structure and the overall reliability of the device are still to be further improved.
Disclosure of Invention
The invention aims to provide a trench type power MOS device and a manufacturing method thereof, which can improve the withstand voltage of a terminal region and the reliability of the whole device.
To achieve the above object, the present invention provides a trench type power MOS device having a termination structure formed on a termination region of a substrate of a first conductivity type, the termination structure comprising:
at least one terminal trench formed in the terminal region of the substrate, wherein one terminal trench located at an outermost side of the terminal region is an outermost terminal trench;
a first dielectric layer covering the inner surface of the terminal trench;
the conductive material layer is filled in the terminal groove and formed on the first dielectric layer;
at least one doped region formed in the substrate of the termination region outside the outermost termination trench and doped with impurities of a first conductivity type and a second conductivity type, and the net doped conductivity type of the doped region is the first conductivity type.
Optionally, the trench power MOS device has at least two doping regions, and the doping regions are sequentially arranged from top to bottom along a depth extending direction from the outermost terminal trench; the concentration of net doping of each doping region is consistent, or the concentration of net doping of each doping region is gradually increased from top to bottom along the depth extending direction of the outermost terminal trench.
Optionally, at least part of the doped regions are connected up and down.
Optionally, each of the doping regions is spaced apart from the outermost terminal trench, the lowermost doping region is located outside the bottom of the outermost terminal trench, and the top of the uppermost doping region is lower than the top of the outermost terminal trench.
Optionally, the termination structure may further comprise a guard ring of the second conductivity type disposed in the substrate below the bottom of the respective termination trench.
Optionally, the trench power MOS device further includes a cell structure, an interlayer dielectric layer, and a source metal; the cell structure is formed on a cell area of the substrate, and the terminal area is positioned at the periphery of the cell area; the source metal extends to the upper part of the terminal area at the outer side of the terminal groove at the outermost side from the upper part of the cellular area, and is respectively and electrically isolated from the conductive material layer and the substrate of the terminal area through the interlayer dielectric layer; the width of each doped region is the same as the length of the source metal beyond the outermost terminal trench.
Optionally, the cell structure includes at least one cell trench, and a gate and source conductive layer formed in each of the cell trenches; the grid electrode and the source electrode conducting layer are arranged in the cell groove to form an upper-lower structure or a left-right structure; the source metal is electrically connected with the source conducting layer and part of the conducting material layer in the terminal groove at the same time.
Optionally, the substrate includes a base of the first conductivity type and a semiconductor epitaxial layer of the first conductivity type, and the termination trench, the cell trench and each of the doped regions are formed in the semiconductor epitaxial layer.
Based on the same inventive concept, the invention also provides a manufacturing method of the trench type power MOS device, which comprises the following steps:
providing a substrate of a first conductive type, and forming at least one terminal groove in a terminal area of the substrate, wherein one terminal groove located at the outermost side of the terminal area is the outermost terminal groove;
forming a first dielectric layer and a conductive material layer, wherein the first dielectric layer covers the inner surface of the terminal groove, and the conductive material layer is filled in the terminal groove and is formed on the first dielectric layer;
wherein, before or after forming the termination trench, the manufacturing method further includes: and forming a patterned mask layer on the surface of the substrate, and taking the patterned mask layer as a mask to implant impurities of a second conductivity type into the substrate outside the outermost terminal trench so as to form at least one doped region, wherein the net doped conductivity type of the doped region is the first conductivity type.
Optionally, the substrate outside the outermost terminal trench is implanted with impurities of the second conductivity type at least twice at different depths to form at least two doped regions, and the doped regions are sequentially arranged from top to bottom along a depth extending direction from the outermost terminal trench.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. at least one doping area doped with impurities of a second conduction type is additionally arranged on the outer side of the outermost terminal groove of the terminal area, the net doping conduction type of the doping area is the first conduction type, the depletion width near the outermost terminal groove and the curvature radius of the boundary line of the depletion area can be optimized, the distance between the depletion boundary line and the outermost terminal groove of the terminal area is enough, the electric field distribution is changed, the impact ionization rate is reduced, and therefore the withstand voltage of the terminal structure of the device and the reliability of the whole device are improved.
2. The arrangement width of the doping region additionally arranged on the outer side of the outermost terminal groove is the same as the length of the source metal exceeding the outermost terminal groove, so that the width of the device terminal cannot be additionally increased, and the increase of the area of the device is avoided.
3. The required patterned mask layer is formed only by adding a photomask, at least one time of second-conductivity-type impurity injection and annealing activation are carried out on the substrate on the outer side of the terminal groove on the outermost side of the terminal area under the masking effect of the patterned mask layer, the net doping of the injection area after the impurities are annealed and activated is still the first conductivity type, but the net doping concentration becomes light, the process is simple, and the cost is low.
Drawings
Fig. 1 is a schematic diagram of an electric field distribution in a termination region of a conventional trench power MOS device.
Fig. 2 is a schematic diagram showing the impact ionization rate distribution of the termination region of the conventional trench power MOS device.
Fig. 3 is a schematic cross-sectional view of a trench power MOS device according to an embodiment of the invention.
Fig. 4 is a flowchart of a method for manufacturing a trench power MOS device according to an embodiment of the invention.
Fig. 5 to fig. 7 are schematic cross-sectional views of devices in a method for manufacturing a trench power MOS device according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of a trench power MOS device according to another embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of a trench power MOS device according to still another embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It will be understood that when a layer is referred to as being formed on another layer, it can be formed directly on the other layer or intervening layers may also be present. Where the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, it is merely for convenience in describing and simplifying the description, and it is not intended to indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items. The terms "identical", "equal" and "consistent" include identical and identical meanings, and may also include meanings that are approximately the same or approximately equal under the allowed process tolerances. The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Referring to fig. 1, in a termination structure of a trench power MOS device in the prior art, a guard Ring (P Ring) 101 is usually added at the bottom of a plurality of trenches (which are usually formed by the same etching process as trenches of a cell region) in a termination region, so that an electric field distribution of the termination region where the termination structure is located is more reasonable than that of the cell region, and a withstand voltage of the termination region is higher than that of the cell region by a certain ratio, thereby greatly improving an EAS (Energy avalanche Energy) capability of the device and an ESD (Electro-Static discharge) capability between a drain and a source, and significantly improving reliability of the device.
However, the inventor has found that, in the termination structure, the voltage difference is large near the outermost trench 100 (the rightmost trench in fig. 1 and 2), the depletion width is too small, the electric field is large (as shown in fig. 1), and the impact ionization rate is high (as shown in fig. 2). Therefore, the region near the outermost trench in the termination structure becomes a weak point of the termination structure, and the improvement of the breakdown voltage of the termination region and the reliability of the device are limited, thereby limiting the improvement of the performance of the trench power MOS device as a whole.
Based on the above, the invention provides a trench type power MOS device and a manufacturing method thereof, on the basis of not increasing the width and area of a terminal region, at least one doped region doped with impurities of a second conductivity type is formed in a substrate of a first conductivity type at the periphery of one trench at the outermost side of the terminal region, and the conductivity type of net doping of each doped region is still the first conductivity type, so that the depletion width near one trench at the outermost side of the terminal region and the curvature radius of the boundary line of a depletion region are increased by utilizing the change of the net doping concentration distribution of the first conductivity type at the periphery of one trench at the outermost side, thereby eliminating the weak point of the terminal structure, and improving the withstand voltage of the terminal structure and the reliability of the whole device.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 3, the present invention provides a trench type power MOS device formed on a substrate of a first conductivity type and having a cell structure formed on a cell region I of the substrate and a terminal structure formed on a terminal region II of the substrate.
The substrate may include a base 200 and a semiconductor epitaxial layer 201 formed on the base 200, the base 200 and the semiconductor epitaxial layer 201 are both made of a semiconductor material of a first conductivity type, and the thickness of the base 200 is smaller than that of the semiconductor epitaxial layer 201. The substrate 200 is made of any suitable material such as silicon, silicon-on-insulator, germanium, and the like. The terminal region II is disposed around the cell region I.
In this embodiment, the termination structure includes at least one termination trench 202, a first dielectric layer 204b, a conductive material layer 205b, and at least two doped regions (shown as 201a, 201b, 201c in fig. 3).
Wherein each termination trench 202 is formed in the termination region II of the semiconductor epitaxial layer 201 and has a depth insufficient to penetrate through the semiconductor epitaxial layer 201. A first dielectric layer 204b overlies the inner surface of the termination trench 202 and a layer of conductive material 205b fills the termination trench 202 and is located on the surface of the first dielectric layer 204 b. The conductive material layer 205b may be considered as a floating gate or shield gate structure formed in the termination region II.
One of the terminal trenches 202 located at the outermost side of the terminal region II is defined as an outermost terminal trench 202b, and the outermost terminal trench 202b is located farthest from the boundary of the cell region I with respect to the other terminal trenches 202.
The respective doped regions (such as 201a, 201b, 201c in fig. 3, may be more in number) are formed in the semiconductor epitaxial layer 201 outside the outermost terminal trench 202b and are arranged in order from top to bottom along the depth extension direction (i.e., in the longitudinal direction) from the outermost terminal trench 202 b. Each doped region is laterally spaced apart from the outer sidewall of the outermost termination trench 202b by a distance d, and the top surface of the uppermost doped region (e.g., 201c in fig. 3) is lower than the top surface of the outermost termination trench 202b, i.e., the distance between the top surface of the uppermost doped region (e.g., 201c in fig. 3) and the top surface of the semiconductor epitaxial layer 201 is h, and h > 0.
More importantly, each doping region (such as 201a, 201b, 201c in fig. 3, may be a greater number) is doped with impurities of a first conductivity type and a second conductivity type, the impurities of the first conductivity type in each doping region are the impurities of the first conductivity type originally contained in the semiconductor epitaxial layer 201 outside the outermost terminal trench 202b, the impurities of the second conductivity type in each doping region are the impurities of the second conductivity type additionally implanted into the semiconductor epitaxial layer 201 outside the outermost terminal trench 202b, the content of the impurities of the second conductivity type in each doping region is lower than the content of the impurities of the first conductivity type originally contained in the semiconductor epitaxial layer 201 of the doping region, so that the net-doped conductivity type of each doping region (such as 201a, 201b, 201c in fig. 3, may be a greater number) is still the first conductivity type, thereby, the net doping concentration of the semiconductor epitaxial layer 201 of each doping region (such as 201a, 201b, 201c in fig. 3, which can be more), is lighter (i.e. reduced) relative to the net doping concentration of the semiconductor epitaxial layer 201 of other regions.
Referring to fig. 3, after simulation tests are performed on the conventional trench power MOS device and the trench power MOS device of the present invention obtained under the condition that other structures and process conditions are not changed, it is found that a depletion region boundary line L1 near the outermost terminal trench 202b of the terminal structure of the trench power MOS device of the present invention is expanded from a depletion region boundary line L0 of the conventional trench power MOS device. This shows that the depletion width near the outermost termination trench 202b and the radius of curvature of the depletion region boundary line L1 can be optimized by the action of these doped regions (as shown in fig. 3 as 201a, 201b, 201c, in larger numbers) of the present invention, so that the distance of the depletion boundary line L1 from the outermost termination trench 202b of the termination region II is sufficient, the electric field distribution near the outermost termination trench 202b is changed, and the impact ionization rate near the outermost termination trench 202b is reduced, so that the vicinity of the outermost termination trench 202b is no longer the weak point of the termination structure, thereby improving the withstand voltage of the termination structure of the device and the reliability of the entire device.
Alternatively, all the doped regions (e.g., 201a, 201b, 201c in fig. 3, in a larger number) are aligned and connected one above the other along the depth extension direction (i.e., in the longitudinal direction) of the outermost terminal trench 202b, and the width and the final net doping concentration of each doped region (e.g., 201a, 201b, 201c in fig. 3, in a larger number) are substantially the same, and at this time, the distance d between the doped regions and the outer sidewall of the outermost terminal trench 202b is the same in the lateral direction. Thus, the depletion region boundary line L1 near the outermost termination trench 202b may extend approximately vertically from top to bottom in the semiconductor epitaxial layer 201 from the top surface of the semiconductor epitaxial layer 201 to the bottom of the outermost termination trench 202 b. At this time, all the doped regions connected in sequence from top to bottom are equivalent to one doped region with a large longitudinal extension length, and the top surface of the doped region is separated from the top surface of the semiconductor epitaxial layer 201 by a distance h and is separated from the outer sidewall of the outermost terminal trench 202b by a distance d. Based on this, in other embodiments of the present invention, it is allowed to provide only one doped region doped with impurities of the second conductivity type and net-doped with impurities of the first conductivity type in the semiconductor epitaxial layer 201 outside the outermost terminal trench 202b, so as to utilize the doped region to optimize the depletion width and the radius of curvature of the depletion region boundary line L1 at a specific position near the outermost terminal trench 202b, so that the distance from the depletion boundary line L1 at the specific position to the outermost terminal trench 202b of the terminal region II is sufficient, change the electric field distribution near the outermost terminal trench 202b, reduce the impact ionization rate near the outermost terminal trench 202b, so that the specific position near the outermost terminal trench 202b is no longer the weak point of the terminal structure, thereby improving the withstand voltage of the device terminal structure and the reliability of the entire device.
It should be appreciated that in other embodiments of the present invention, when the effect of the respective doping regions (e.g., 201a, 201b, 201c in fig. 3, in greater numbers) is such that the depletion boundary line L1 is a sufficient distance from the outermost terminal trench 202b, the width and/or resulting net doping concentration of at least some of the doping regions are also allowed to be non-uniform, at least some of the doping regions are also allowed to be offset above and below, and at least some of the doping regions are allowed to be spaced above and below (i.e., not touching) each other. At this time, these doped regions are not the same in the lateral direction as the spacing d between the outer sidewalls of the outermost termination trench 202 b. Specifically, for example, the net doping concentration of each doped region 201a, 201b, 201c gradually increases from top to bottom along the depth extension direction of the outermost terminal trench 202b to accommodate the voltage difference between the floating gate or the shielding gate (i.e., the conductive material layer 205b in fig. 3) in the terminal region II and the substrate 200. In addition, the distance d between each doped region and the outer sidewall of the outermost terminal trench 202b is allowed to be greater than or equal to 0, and preferably, the distance is greater than 0 (which may be the minimum distance allowed by the process), so that the formation process of the doped region is prevented from adversely affecting the internal structure of the outermost terminal trench 202 b.
It should be understood that the depth positions of the respective doped regions (such as 201a, 201b, 201c in fig. 3, and may be more numerous) may be designed according to the optimization degree required for the depletion region boundary line L1 outside the outermost terminal trench 202b at each position, and the present invention is not limited thereto. For example, when there are three doped regions 201a, 201b, 201c, the doped region 201a may be disposed near the bottom of the conductor material layer 205b (the length of which is indicated by LSP) of the outermost termination trench 202b, the doped region 201b may be disposed near the bottom of the conductor material layer 205b of the outermost termination trench 202b at a distance LSP 1/3, and the doped region 201c may be disposed near the bottom of the conductor material layer 205b of the outermost termination trench 202b at a distance LSP 2/3.
In addition, it should be understood that the depletion widths of the upper and lower doped regions are equal, and the non-connected doped regions will result in a large electric field at the non-connection position of the upper and lower adjacent doped regions, and the depletion region boundary line L1 is recessed toward the non-connection position of the upper and lower adjacent doped regions. Therefore, in the present invention, when a plurality of the doped regions are sequentially connected one above another, the shape of the depletion boundary line L1 near the outermost terminal trench 202b can be continuously optimized, and the breakdown voltage of the device terminal structure and the reliability of the entire device can be improved to the maximum extent. When at least a partial number of the doped regions of the plurality of doped regions do not meet each other, the depletion boundary line L1 can be substantially optimized only for a specific region in the vicinity of the outermost terminal trench 202b, thereby achieving an effect of further reducing the ion implantation cost for forming the doped region (i.e., the impurity implantation of the second conductivity type is not required where there is a break) while improving the withstand voltage of the device terminal structure and the reliability of the entire device.
Optionally, the termination structure may further include a guard ring 203 of the second conductivity type, the guard ring 203 being disposed in the semiconductor epitaxial layer 201 below the bottom of the corresponding termination trench 202, and the guard ring 203 being in contact with the termination trench 202. In the termination region II, only a part of the number of the protection rings 203 corresponding to the bottom of the termination trenches 202 may be provided, and the bottom of each of the outermost termination trenches 202b in fig. 3, for example, has no protection ring, and the bottoms of the remaining termination trenches 202b are provided with corresponding protection rings 203; a corresponding guard ring 203 may be provided below the bottom of each termination trench 202, including the outermost termination trench 202 b.
In this embodiment, the cell structure includes at least one cell trench 202', a second dielectric layer 204a, a source conductive layer 205a, a gate 206, a body region (body) 207 of the second conductivity type, and a source region 208 of the first conductivity type.
Optionally, each cell trench 202' in the cell region I and the terminal trench 202 are formed by the same etching process, thereby avoiding additional process steps in the manufacturing process of the terminal structure and reducing the cost. The line width and the slot pitch of the cell trenches 202' may be different from those of the terminal trenches 202.
Alternatively, the cell trenches 202' may be arranged in parallel stripes, and the terminal trench 202 may be a ring-shaped trench surrounding the cell region I. The slot pitch between adjacent cell trenches 202' may be smaller than the slot pitch between adjacent terminal trenches 202.
In this embodiment, the second dielectric layer 204a is formed on the inner surface of the cell trench 202 ', and the source conductive layer 205a is filled in the cell trench 202' and formed on the surface of the second dielectric layer 204 a. A gate 206 is formed in the top of the cell trench 202' and is insulated and isolated from the semiconductor epitaxial layer 201 and the source conductive layer 205a by a second dielectric layer 204a, respectively. The gate 206 and the source conductive layer 205a in the same cell trench 202' may form an upper-lower structure or a left-right structure. In this embodiment, fig. 3 shows only a case where the gate electrode 206 and the source conductive layer 205a form a left-right structure. The body region 207 is formed in the semiconductor epitaxial layer 201 on both sides of the cell trench 202', and the source region 208 is formed in the top of the body region 207.
It should be understood that the second dielectric layer 204a is typically a stacked structure of multiple dielectric films, in which the second dielectric layer 204a sandwiched between one side wall of the gate 206 and the semiconductor epitaxial layer 201 functions as a gate dielectric layer, the second dielectric layer 204a sandwiched between the other side wall of the gate 206 and the source conductive layer 205a functions as a shielding dielectric layer, the second dielectric layer 204a above the top of the gate 206 functions as a gate isolation layer (isolating the gate 206 from the film layer above the gate 206), and the second dielectric layer 204a below the bottom of the gate 206 functions as a field oxide layer (isolating the semiconductor epitaxial layer 201 from the source conductive layer 205 a).
Therefore, the second dielectric layer 204a at least below the bottom of the gate 206 and the first dielectric layer 204b in the termination trench 202 may be formed by the same film deposition process. The first dielectric layer 204b and the second dielectric layer 204a are made of silicon oxide, for example.
The source conductive layer 205a in the cell trench 202' and the conductive material layer 205b in the termination trench 202 may both be doped polysilicon and may be formed by the same polysilicon deposition process.
In this embodiment, the trench power MOS device further includes an interlayer dielectric layer 210, conductive contact holes 211a to 211c, a source metal 212, and a drain metal 213. Wherein, the interlayer dielectric layer 210 covers the top surface of the semiconductor epitaxial layer 201 and buries the cell structure and the terminal structure. The source metal 212 is formed on the interlayer dielectric layer 210 and electrically connected to the source conductive layer 205a in the corresponding cell trench 202' through the conductive contact hole 211a penetrating the interlayer dielectric layer 210, electrically connected to the corresponding body region 207 and the source region 208 at the top of the body region 207 through the conductive contact hole 211b penetrating the interlayer dielectric layer 210, and electrically connected to the conductive material layer 205b in the corresponding terminal trench 202 through the conductive contact hole 211c penetrating the interlayer dielectric layer 210. The conductive contact hole 211b shorts the corresponding body region 207 and the source region 208 at the top of the body region 207, so that the body region and the source region are equipotential. The source metal 212 extends continuously from the surface of the interlayer dielectric layer 210 in the cell region I to a portion of the top surface of the interlayer dielectric layer 210 outside the outermost terminal trench 202b in the terminal region II.
Optionally, the width w2 of each doped region 201a, 201b, 201c in the termination region II is the same as the length w1 of the source metal 212 beyond the outermost termination trench 202b, respectively.
In this embodiment, for the n-type trench power MOS device, the first conductivity type is n-type, and the second conductivity type is p-type, and for the p-type trench power MOS device, the first conductivity type is p-type, and the second conductivity type is n-type.
It should be understood that the trench type power MOS device of the present invention may be manufactured by any suitable process flow, and compared to the existing manufacturing process flow, one photomask for forming each doped region may be added, and then, at a suitable process flow node, photolithography and impurity implantation are performed by using the photomask, and then, impurity implantation of different depths is performed on the semiconductor epitaxial layer from the same position region of the top surface of the semiconductor epitaxial layer for multiple times, and after corresponding annealing activation, a corresponding doped region may be formed in the semiconductor epitaxial layer outside the outermost terminal trench of the terminal region, so that net doping of the semiconductor epitaxial layer of the doped region becomes lighter.
Specifically, referring to fig. 4, an embodiment of the invention provides a method for manufacturing a trench type power MOS device, which includes:
s1, providing a substrate of a first conduction type, and forming at least one terminal groove in a terminal area of the substrate, wherein one terminal groove located at the outermost side of the terminal area is the outermost terminal groove;
s2, forming a first dielectric layer and a conductive material layer, the first dielectric layer covering the inner surface of the terminal trench, the conductive material layer being filled in the terminal trench and formed on the first dielectric layer;
and S3, forming a patterned mask layer on the surface of the substrate, and taking the patterned mask layer as a mask to implant impurities of the second conductivity type with required depth into the substrate outside the outermost terminal trench so as to form at least one doped region, wherein the net doped conductivity type of the doped region is the first conductivity type.
Referring to fig. 5, in step S1, first, a substrate 200 is provided and a semiconductor epitaxial layer 201 is formed on the substrate 200 by an epitaxial growth process, wherein the thickness of the semiconductor epitaxial layer 201 is greater than that of the substrate 200; then, a patterned hard mask layer (not shown) capable of defining the cell trench 202' and the terminal trench 202 is formed on the semiconductor epitaxial layer 201 by hard mask layer deposition, photolithography and etching, which is well known to those skilled in the art and will not be described herein; then, taking the patterned hard mask layer as a mask, performing trench etching on the semiconductor epitaxial layer 201 until the depth of the trench meets the requirement, thereby forming a cell trench 202' in the semiconductor epitaxial layer 201 of the cell region I and forming a terminal trench 202 in the semiconductor epitaxial layer 201 of the terminal region II; then, the patterned hard mask layer is removed as a mask, the cell trench 202' of the cell region I, the outermost terminal trench 202b of the terminal region II and the semiconductor epitaxial layer 201 of the corresponding region are masked through corresponding processes such as photolithography or sacrificial layer filling and masking, impurities of the second conductivity type are selectively implanted into the semiconductor epitaxial layer 201 at the bottom of the other terminal trenches 202 in the terminal region II, annealing activation processing is performed, and a guard ring 203 connected with the bottom of the terminal trench 202 is formed below the bottom of the other terminal trenches 202 in the terminal region II.
Of course, the process of forming the guard ring 203 may be performed by other processes known to those skilled in the art as needed, and will not be described herein.
Referring to fig. 6, in step S2, a dielectric layer is first formed on the inner surfaces of the cell trench 202 'and the terminal trench 202, and polysilicon deposition and top planarization are performed to form a second dielectric layer 204a on the inner surface of the cell trench 202' and filled with the source conductive layer 205a, and a first dielectric layer 204b on the inner surface of the terminal trench 202 and filled with the conductive material layer 205 b. The first dielectric layer 204b and the second dielectric layer 204a may be formed by a thermal oxidation process or a chemical vapor deposition process, and the thicknesses of the first dielectric layer 204b and the second dielectric layer 204a are determined by the voltage withstanding specification of the device and the doping concentration of the semiconductor epitaxial layer 201, which are well known to those skilled in the art and will not be described herein again.
In step S2, referring to fig. 6, the termination region II is masked, the second dielectric layer 204a in the cell trench 202 'is etched, and a gate trench 206a is formed in the upper portion of the cell trench 202'; then, referring to fig. 7, polysilicon is deposited into the gate trench 206a and etched back to form a gate 206; a dielectric layer is then deposited and a back etch or top surface planarization of the dielectric layer is performed to fill the cell trench 202' and to bury the top of the gate 206. Before depositing polysilicon into the gate trench 206a, a gate dielectric layer is formed in the gate trench 206a by thermal oxidation or deposition process, and at this time, the remaining second dielectric layer 204a when the second dielectric layer 204a is etched to form the gate trench 206a, the gate dielectric layer formed in the gate trench 206a, and the dielectric layer burying the top of the gate 206 together form a new second dielectric layer 204a in the cell trench 202.
With reference to fig. 7, in step S3, a photo-etching and masking process is performed through a photo-mask to form a corresponding patterned mask layer to mask the cell region I and expose a region of the semiconductor epitaxial layer 201 outside the outermost terminal trench 202 of the terminal region II for forming a doped region; then, with the patterned mask layer as a mask, impurity implantation of the second conductivity type is performed for a plurality of times at different depths into the semiconductor epitaxial layer 201 outside the outermost terminal trench 202 of the exposed terminal region II, and annealing activation processing is performed to form a plurality of corresponding doped regions 201a to 201 c. And each of the doped regions 201 a-201 c has a distance d from the outermost terminal trench 202b, all of the doped regions 201 a-201 c are sequentially arranged from top to bottom along a depth extending direction from the outermost terminal trench 202b, and the net doped conductivity type of each of the doped regions 201 a-201 c is the first conductivity type. That is, the net doping concentration of the semiconductor epitaxial layer 201 at each of the doped regions 201 a-201 c is smaller than the net doping concentration of the semiconductor epitaxial layer 201 at the periphery (including the upper, lower and outer directions) of the doped regions 201 a-201 c. The doped regions 201 a-201 c may be sequentially connected to each other in an up-down manner or not connected to each other in an up-down manner, and the widths of the doped regions 201 a-201 c may be the same or different.
It should be understood that in step S3, after forming the gate 206 and before forming the doped regions 201a to 201c, or after forming the doped regions 201a to 201c, the second conductive type impurity may be selectively implanted into the semiconductor epitaxial layer 201 on both sides of the cell trench 202' of the cell region I to form the body region 207, and further, the first conductive type source/drain impurity implantation may be selectively performed on the top of the body region 207 to form the source region 208. The process of forming the body region 207 and the source region 208 is well known to those skilled in the art and will not be described herein.
After step S3, referring to fig. 3, an interlayer dielectric layer 210 may be deposited on the semiconductor epitaxial layer 201, and contact hole etching and metal material filling are performed on the interlayer dielectric layer 210 at the corresponding position, so as to form conductive contact holes 211a to 211 c; then, a source metal material is deposited and etched on the interlayer dielectric layer 210 and the conductive contact hole to form a source metal 212, and further, a drain metal material is deposited and etched on the back surface of the substrate 200 to form a drain metal 213. The length w1 of the source metal 212 beyond the outermost termination trench 202b may be consistent with the width w2 of each of the doped regions 201 a-201 c.
It should be noted that the above embodiment is only an example of the manufacturing method of the present invention, and those skilled in the art may modify the manufacturing method of the above embodiment as needed to obtain the manufacturing method of other embodiments of the present invention. For example, the implementation stages of the doped regions 201 a-201 c may be adjusted to any suitable node in the fabrication process of the trench power MOS device.
Referring to fig. 8, in another embodiment of the present invention, in step S1, after providing the substrate and before forming the cell trench 202' and the termination trench 202, the semiconductor epitaxial layer 201 is subjected to a plurality of impurity implantations of the second conductivity type at different depths to form the desired doped regions 201 a-201 c.
Referring to fig. 9, in another embodiment of the present invention, after the cell structures (i.e., the cell trenches, the source conductive layer 205a, the gate 206, the body region 207 and the source region 208) of the cell region and other structures of the terminal structure (i.e., the terminal trench 202, the first dielectric layer 204b, the conductive material layer 205b and the guard ring 203) are formed, and before the interlayer dielectric layer is covered, impurity implantation of the second conductivity type is performed for a plurality of times at different depths into the semiconductor epitaxial layer 201 outside the outermost terminal trench 202b to form the desired doped regions 201a to 201 c.
In summary, according to the technical solution of the present invention, at least one doped region doped with the second conductive type impurity is added in the required depth of the substrate outside the outermost terminal trench of the terminal region, and the width of the device terminal is not additionally increased, so that the depletion width near the outermost terminal trench and the radius of curvature of the boundary line of the depletion region can be optimized, the distance from the depletion boundary line to the outermost terminal trench of the terminal region is sufficient, the electric field distribution is changed, the impact ionization rate is reduced, and the withstand voltage of the device terminal structure and the reliability of the entire device are improved. Avoiding increasing the area of the device. In addition, a photomask can be added, second-conductivity-type impurity implantation is carried out for several times in the substrate on the outer side of the terminal groove on the outermost side of the terminal area, annealing activation is carried out, and a plurality of required doping areas which are longitudinally arranged are formed.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A trench-type power MOS device having a termination structure formed on a termination region of a substrate of a first conductivity type, the termination structure comprising:
at least one terminal trench formed in the terminal region of the substrate, wherein one terminal trench located at the outermost side of the terminal region is the outermost terminal trench;
a first dielectric layer covering the inner surface of the terminal trench;
the conductive material layer is filled in the terminal groove and formed on the first dielectric layer;
at least one doped region formed in the substrate of the termination region outside the outermost termination trench and doped with impurities of a second conductivity type, and the net doped conductivity type of the doped region being the first conductivity type.
2. The trench power MOS device of claim 1 wherein the trench power MOS device has at least two of the doped regions, and each of the doped regions is arranged sequentially from top to bottom along a depth extension from the outermost terminal trench; the concentration of net doping of each doping region is consistent, or the concentration of net doping of each doping region is gradually increased from top to bottom along the depth extending direction of the outermost terminal trench.
3. The trench power MOS device of claim 2 wherein at least a portion of the number of doped regions are contiguous.
4. The trench power MOS device of claim 2 wherein each of the doped regions is spaced apart from the outermost terminal trench, and wherein the lowermost doped region is located outside the bottom of the outermost terminal trench and the uppermost doped region has a top that is lower than the top of the outermost terminal trench.
5. The trench power MOS device of claim 1, wherein the termination structure further comprises a guard ring of the second conductivity type disposed in the substrate below the bottom of the respective termination trench.
6. The trench power MOS device of any of claims 1-5, further comprising a cell structure, an interlayer dielectric layer, and a source metal; the cell structure is formed on a cell area of the substrate, and the terminal area is positioned at the periphery of the cell area; the source metal extends to the upper part of the terminal area at the outer side of the terminal groove at the outermost side from the upper part of the cellular area, and is respectively and electrically isolated from the conductive material layer and the substrate of the terminal area through the interlayer dielectric layer; the width of each doped region is the same as the length of the source metal beyond the outermost terminal trench.
7. The trench power MOS device of claim 6, wherein the cell structure comprises at least one cell trench, and a gate and source conductive layer formed in each of the cell trenches; the grid electrode and the source electrode conducting layer are arranged in the cell groove to form an upper-lower structure or a left-right structure; the source metal is electrically connected with the source conducting layer and part of the conducting material layer in the terminal groove at the same time.
8. The trench power MOS device of claim 7 wherein the substrate comprises a base of a first conductivity type and a semiconductor epitaxial layer of the first conductivity type, the termination trench, the cell trench and each of the doped regions being formed in the semiconductor epitaxial layer.
9. A method for manufacturing a trench type power MOS device is characterized by comprising the following steps:
providing a substrate of a first conductive type, and forming at least one terminal groove in a terminal area of the substrate, wherein one terminal groove located at the outermost side of the terminal area is the outermost terminal groove;
forming a first dielectric layer and a conductive material layer, wherein the first dielectric layer covers the inner surface of the terminal groove, and the conductive material layer is filled in the terminal groove and is formed on the first dielectric layer;
wherein, before or after forming the termination trench, the manufacturing method further comprises: and forming a patterned mask layer on the surface of the substrate, and taking the patterned mask layer as a mask to implant impurities of a second conductivity type into the substrate outside the outermost terminal trench so as to form at least one doped region, wherein the net doped conductivity type of the doped region is the first conductivity type.
10. The method of claim 9 wherein the substrate outside of the outermost terminal trench is implanted at least twice with different depths of impurities of the second conductivity type to form at least two of the doped regions, and each of the doped regions is arranged sequentially from top to bottom along a depth extending from the outermost terminal trench.
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