JP2016189368A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a power semiconductor device having high withstand voltage.SOLUTION: A semiconductor device comprises: floating electrodes (electrodes in the grooves) 37 which are formed in grooves 34 on an outer peripheral region Y and set at a floating potential; and floating p-type layers (embedded semiconductor layers) 38 which are formed around bottoms of the grooves 34 and each of which has a substantially circular cross sectional shape and set at a floating potential. The occurrence of local electric field concentration from a cell region X to the outer peripheral region Y in OFF time is inhibited by the floating electrode 37 and the floating p-type layer 38. The size (diameter) of the floating p-type layers 38 decreases with the decreasing distance from the right side. That is, the floating p-type layer 381 closest to the cell region X is largest and the sizes of the floating p-type layer 382 and the floating p-type layer 383 on the right side of the floating p-type layer 381 become gradually small.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a structure of a trench gate type semiconductor device that performs a switching operation.

  A power MOSFET, an insulated gate bipolar transistor (IGBT), or the like is used as a switching element (power semiconductor element) that performs a large current switching operation. In such a switching element, a trench gate type in which an oxide film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is used.

FIG. 5 is a sectional view showing an example of the configuration of such a trench gate type power MOSFET (semiconductor device). In plan view, the semiconductor device 100 surrounds the cell region X in which an operating current flows when turned on, and the cell region X outside the cell region X in order to ensure a breakdown voltage when the operating current does not flow but is turned off. There are two areas, the outer peripheral area Y provided in the area. In FIG. 5, in this semiconductor substrate 80, an n ⁻ layer 82 and a p ⁻ layer 83 are sequentially formed on an n ⁺ layer 81 serving as a drain layer.

In the cell region X, a structure that operates as a MOSFET is formed in the semiconductor substrate 80. First, a groove (cell region groove: trench) 84 penetrating the p ⁻ layer 83 is formed on the surface side of the semiconductor substrate 80. A plurality of grooves 84 (two in the illustrated range) are formed in parallel to extend in a direction perpendicular to the paper surface in FIG. An oxide film 86 is uniformly formed on the inner surface of each trench 84, and a gate electrode 87 is formed so as to fill the trench 84. The gate electrode 87 is usually formed of polycrystalline silicon doped at a high concentration.

Further, on the surface side of the semiconductor substrate 80, n ⁺ layers 85 serving as source regions are formed on both sides of the groove 84. A source electrode (first main electrode) 89 is formed on the surface of the semiconductor substrate 80. On the other hand, a drain electrode 90 (second main electrode) is formed on the entire back surface of the semiconductor substrate 80 in contact with the n ⁺ layer (drain layer) 81. On the other hand, since the interlayer insulating layer 88 is formed so as to cover the groove 84 on the surface side of the semiconductor substrate 80, the source electrode 89 is in contact with both the n ⁺ layer 85 and the p ⁻ layer 83, and the gate electrode 87. Is insulated. On the surface side outside the range shown in FIG. 5, for example, all the gate electrodes 87 are connected on the end side in the extending direction (perpendicular to the paper surface) of the groove 84 and connected to a common gate wiring. The gate wiring and the source electrode 89 are formed separately. Therefore, for each groove 84, a channel is formed in the p ⁻ layer 83 on the side surface of the groove 84 by the voltage applied to the gate wiring (gate electrode 87), and n between the n ⁻ layer 82 and the n ⁺ layer 85. It operates as a type MOSFET and this MOSFET is turned on. That is, current switching between the source electrode 89 and the drain electrode 90 can be controlled by the voltage applied to the gate electrode 87. Since the MOSFETs formed for each groove 84 are all connected in parallel, a large current can flow between the source electrode 89 and the drain electrode 90.

The outer peripheral region Y is provided to increase the breakdown voltage between the source electrode 89 and the drain electrode 90 when the MOSFET formed in the cell region X is off. When this is off, a depletion layer is formed between the p ⁻ layer 83, the groove (cell region groove) 84 and the n ⁻ layer 82, and the width of the depletion layer is locally narrowed so that the electric field strength is increased. Destruction occurs. Since such a region having a high local electric field strength is particularly likely to occur at the end of the element, the outer peripheral region Y is provided so as to surround the cell region X, and such a region is not provided on the outer periphery. It is done. However, since the outer peripheral region Y and the cell region X are simultaneously manufactured, the basic structure of the outer peripheral region Y is configured to be similar to the cell region X.

  The structure of the outer peripheral region Y in FIG. 5 is the same as that described in Patent Document 1. In the outer peripheral region Y, like the cell region X, a groove (outer peripheral region groove) 94 and an oxide film 96 are formed on the inner surface thereof. Since the groove in the cell region X (cell region groove) 84 and the groove in the outer peripheral region Y (outer peripheral region groove) 94 are formed at the same time, the depth is the same. The same applies to the oxide films 86 and 96 inside, and the thicknesses thereof are the same.

  However, while the gate electrode 87 is formed in the cell region X, a floating electrode (in-groove electrode) 97 having a floating potential (not connected to another electrode) is provided instead. Since the floating electrode 97 is formed of the same material as the gate electrode 87, it can be formed at the same time as the gate electrode 87. Although no potential is applied to the floating electrode 97 from the outside, the potential inside the floating electrode 97 is automatically made uniform, so that the potential distribution in the semiconductor substrate 80 in the outer peripheral region Y when off is greatly affected.

As described in Patent Document 1, a floating p-type layer (embedded semiconductor layer) 98 is formed around the bottom of the groove 94 in the outer peripheral portion Y. Since the floating p-type layer 98 is not connected to the p ^- layer 83 on the upper side and is not connected to other electrodes, the floating p-type layer 98 is set to a floating potential similarly to the floating electrode 97. When the floating p-type layer 98 is not provided, the depletion layer is formed immediately below the trench 94 when off, whereas when the floating p-type layer 98 is provided, the floating p-type layer 98 Formed around. As a result, as shown in FIG. 15 of Patent Document 1, the concentration of the electric field locally at the ends between the grooves 94 in the outer peripheral region Y is suppressed, and a high breakdown voltage at the time of OFF is obtained. The floating p-type layer 98 can be formed, for example, by locally ion-implanting the bottom of the groove 94 after the formation of the groove 94 and then performing thermal diffusion through a heat treatment process. Therefore, in the cross section shown in FIG. 5, the floating p-type layer 98 has a substantially circular shape centered around the bottom of the groove 94 and is formed along the groove 94.

  In FIG. 5, three sets of the groove 94, the floating p-type layer 98, and the like in the outer peripheral region Y are provided, but in practice, this number is appropriately set. In the cell region X, the grooves 84 are formed in parallel in a straight line, whereas in the outer peripheral region Y, the groove 94, the floating p-type layer 98, and the like are annular so as to surround the cell region X. Formed.

FIG. 5 shows the structure of the power MOSFET, but the same structure can be applied to the IGBT. In this case, for example, the n ⁺ layer 81 in FIG. 5 may be a p ⁺ layer serving as a collector layer, the source electrode 89 may be replaced with an emitter electrode, and the drain electrode 90 may be replaced with a collector electrode.

Special table 2011-512676 gazette

  Although the breakdown voltage can be increased as described above by providing the outer peripheral region Y outside the cell region X, the groove 94 and the floating p-type layer are formed outside the outermost groove 94 in the outer peripheral region Y. Since 98 and the like do not exist, the depletion layer has a sharply curved shape in this portion. In this case, electric field concentration is likely to occur at the curved portion, causing a decrease in breakdown voltage.

  That is, it has been difficult to obtain a power semiconductor device having a high breakdown voltage.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention is a semiconductor substrate including a first semiconductor layer having a first conductivity type, and is formed on the surface side of the semiconductor substrate with respect to the first conductivity type. A second semiconductor layer having a reverse second conductivity type, a cell region groove which is a groove formed so as to reach the first semiconductor layer from the surface side of the semiconductor substrate, and an interior of the cell region groove And a first main electrode formed on the surface side of the semiconductor substrate and a first electrode connected to the first semiconductor layer by a voltage applied to the gate electrode. A cell region in which a current flowing between the two main electrodes is controlled, and is formed so as to be adjacent to the cell region in the semiconductor substrate in plan view and reach the first semiconductor layer from the surface side of the semiconductor substrate Perimeter area that is a groove A plurality of grooves, and an outer peripheral region having no structure for controlling the current, wherein the outer peripheral region surrounds a bottom of each outer peripheral region groove, and the second conductivity type is A buried semiconductor layer is provided for each of the outer peripheral region grooves in the first semiconductor layer, and a maximum depth of each embedded semiconductor layer from the bottom of each corresponding outer peripheral region groove is from the cell region. It is characterized by being made shallower with increasing distance.
The semiconductor device according to the present invention is characterized in that, in a cross-sectional view perpendicular to the extending direction of the outer peripheral region groove, the embedded semiconductor layer has a circular shape centered at one point at the bottom of the corresponding outer peripheral region groove. To do.
The semiconductor device of the present invention is characterized in that the diameter of each embedded semiconductor layer in the cross-sectional view is reduced as the distance from the cell region increases.
In the semiconductor device of the present invention, an inner electrode in the groove that is not directly connected to any of the first main electrode, the second main electrode, and the gate electrode is provided in the outer peripheral region groove. And
In the semiconductor device of the present invention, the embedded semiconductor layer is not directly connected to any of the first main electrode, the second main electrode, and the gate electrode.
In the semiconductor device of the present invention, the plurality of outer peripheral region grooves have the same depth.
The semiconductor device according to the present invention is characterized in that the cell region grooves and the plurality of outer peripheral region grooves have the same depth.
The semiconductor device of the present invention is a power MOSFET in which the first main electrode is a source electrode and the second main electrode is a drain electrode.

  Since the present invention is configured as described above, a power semiconductor device having a high breakdown voltage can be obtained.

It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the shape of the depletion layer formed at the time of OFF of the conventional trench gate type semiconductor device. It is a figure which shows the shape of the depletion layer formed at the time of OFF of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the modification of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of an example of the conventional trench gate type semiconductor device.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is a trench gate type power MOSFET in which on / off of a channel is controlled by a gate voltage and current switching is controlled. The gate electrode is formed in a plurality of grooves (trench) formed in parallel to the surface of the semiconductor substrate, and the gate electrodes are connected in parallel. Each gate electrode is formed inside the trench after an oxide film is formed on the surface in the trench.

FIG. 1 is a sectional view showing the structure of the semiconductor device 10 corresponding to FIG. The region of the semiconductor device 10 in plan view is also provided in order to improve the withstand voltage of the semiconductor device 10 without actually performing the switching operation and the cell region X in which the current switching operation is performed. Is roughly divided into an outer peripheral region Y provided adjacent to the outer peripheral region Y. In the semiconductor substrate 20, an n ⁻ layer (first semiconductor layer) 22 and a p ⁻ layer (second semiconductor layer) 23 to be a drift layer are sequentially formed on an n ⁺ layer 21 to be a drain layer. Is the same. Further, a plurality of grooves 24 are formed in the cell region X and a plurality of grooves 34 are formed in the outer peripheral region Y, and oxide films 26 and 36 are formed in the inside thereof. In the cell region X, it is assumed that the grooves 24 and the like are formed in the same manner outside the range shown (left side in FIG. 1). On the other hand, in the outer peripheral region Y, only the three grooves 34 shown in the figure are formed, and the rightmost groove 34 in FIG. 1 is located on the outermost periphery.

In the cell region X, an n ⁺ layer 25 serving as a source region is formed on both sides of the trench 24 in FIG. 1, and a gate electrode 27 is formed inside the trench 24. A source electrode (first main electrode) 29 is formed on the upper surface of the semiconductor substrate 20 so as to be insulated from the gate electrode 27 by the interlayer insulating layer 28. A drain electrode (second main electrode) 30 in contact with the n ⁺ layer 21 is formed on the lower surface side of the semiconductor substrate 20. This configuration is the same as that in the cell region X of the semiconductor device 100 described above.

  Further, in the outer peripheral region Y, a floating electrode (intra-groove electrode) 37 having a floating potential is formed in the groove 34, and a floating having a substantially circular cross-sectional shape around the bottom of the groove 34. Similarly, the p-type layer (embedded semiconductor layer) 38 is formed. For this reason, the floating electrode 37 and the floating p-type layer 38 suppress the occurrence of local electric field concentration in the off state from the cell region X to the outer peripheral region Y. Here, the floating potential is not in direct contact with any of the source electrode (first main electrode) 29, the drain electrode (second main electrode) 30, and the gate electrode 27 used in the power MOSFET. Means that.

  However, in the configuration of FIG. 1, the size (diameter) of the floating p-type layer 38 becomes smaller toward the right side in FIG. 1. That is, the floating p-type layer 381 closest to the cell region X in FIG. 1 is the largest, and the floating p-type layer 382 and the floating p-type layer 383 on the right side thereof are gradually made smaller. With this configuration, the breakdown voltage between the source electrode 29 and the drain electrode 30 when the semiconductor device 10 is turned off can be increased. This point will be described below.

FIG. 2 is a diagram schematically showing the shape of the depletion layer end D on the n ⁻ layer 82 side in the conventional semiconductor device 100 shown in FIG. 5. As described above, the depletion layer is formed in the cell region X along the interface between the p ⁻ layer 83 and the trench 84 and the n ⁻ layer 82, and the direction of the electric field therein is mainly the vertical direction in FIG. Become. This depletion layer is also formed in the outer peripheral region Y so as to be connected to the adjacent trench 94 and the floating p-type layer 98 and continuously spreads in the cell region X and the outer peripheral region Y.

However, as shown in FIG. 2, the depletion layer is formed along the interface between the p ⁻ layer 83 and the n ⁻ layer 82 on the outermost (right side) groove 94 and further outside the floating p-type layer 98. Therefore, the depletion layer has a shape that curves sharply upward. In this case, electric field concentration tends to occur at a greatly curved portion. That is, in the conventional semiconductor device 100, electric field concentration is likely to occur at a location where the outermost trench 94 and the floating p-type layer 98 are present.

On the other hand, FIG. 3 is a diagram similarly showing the shape of the depletion layer end D on the n ⁻ layer 22 side in the semiconductor device 10 of FIG. 1. In this case, the floating p-type layer 38 is made smaller as the distance from the cell region X increases. For this reason, the depletion layer end portion D is located on the upper side as the distance from the cell region X increases, and the curvature of the depletion layer at the outermost (right side) groove 34 and the floating p-type layer 383 is reduced. For this reason, the occurrence of electric field concentration at this point is suppressed, and the breakdown voltage can be further increased as compared with the conventional semiconductor device 100.

  For example, in the structure of FIG. 5, the same effect can be obtained by decreasing the depth of the groove 94 toward the outside (right side in FIG. 5). However, as described above, in the configuration of FIG. 1, the groove 24 in the cell region X and the groove 34 in the outer peripheral region Y can be formed at the same time. In this case, the depth of the groove 94 is made shallower outside. For this, it is necessary to form each groove 94 individually. Thereafter, since it is necessary to form each floating electrode so as to fill each groove 94 having a different depth, the manufacturing process becomes extremely complicated, and it is difficult to manufacture this at a low cost.

  On the other hand, as described above, in the floating p-type layer 38, for example, after the trench 34 is formed with a uniform depth, an acceptor species is ion-implanted at the bottom thereof, and then the acceptor species is diffused by a heat treatment process. Can be formed. In this case, the floating p-type layer 38 has a substantially circular shape centering on one place (one point) at the bottom of the groove 34 in FIG. At this time, if the width of the region to be ion-implanted into the bottom of the groove 34 is made wider at the left groove 34 and narrowed at the right groove 34 in FIG. Thus, the floating p-type layers 381 to 383 having different circular diameters can be formed at the same time. 1 and 3, even if the cross-sectional shape of the floating p-type layer is not circular, the same effect can be obtained if the maximum depth becomes shallower as the distance from the cell region X increases.

  Further, in the above example, the in-groove electrode (floating electrode) 37 that is set to the floating potential in the groove 34 in the outer peripheral region Y, and the embedded semiconductor layer (floating p-type layer) 38 (381) that is set to the floating potential in the lower portion thereof. ~ 383) were provided. However, as long as the electric field concentration can be suppressed in the same manner as described above, the in-groove electrode and the embedded semiconductor layer can be set at the source potential, for example. In this case, as in the case where the gate electrode 27 is connected to the gate wiring at the end of the groove 24 in the cell region X, the in-groove electrode or the embedded semiconductor layer is formed at the end of the groove 34 in the outer peripheral region Y or at one position thereof. What is necessary is just to connect with a source electrode.

  An outer peripheral region Y having a similar structure can also be provided in a semiconductor device other than the structure of FIG. 4 is a cross-sectional view showing a structure of a semiconductor device 40 which is a modification of the semiconductor device 10 of FIG. The structure in the groove 24 in the cell region X of the semiconductor device 40 is the same as that described in Japanese Patent Laid-Open No. 2013-069852. In this structure, since the capacitance between the gate electrode 27 and the drain electrode 30 serving as the feedback capacitance Crss can be reduced, the semiconductor device 40 can be operated at high speed. In the structure of FIG. 4, the gate electrode 27 is thinly separated only on the left and right sides of the groove 24 and is formed only on the upper side of the groove 24. In the groove 24, a trench source electrode (shield electrode) 41 is embedded between the left and right gate electrodes 27. Since the trench source electrode 41 is made of polycrystalline silicon doped at a high concentration, like the gate electrode 27, the trench source electrode 41 is formed in the trench 24 by a separate process using the same formation method as the gate electrode 27. Since the trench source electrode 41 is connected to the source electrode 29 outside the illustrated range, the potential thereof is maintained at the source potential. For this reason, the trench source electrode 41 functions as a shield electrode that maintains the potential of this portion at the source potential.

On the other hand, in this structure, a capacitance between the gate electrode 27 and the source electrode 29 is generated between the trench source electrode 41 connected to the source electrode 29 and the gate electrode 27 on both sides thereof. However, the width of the trench source electrode 41 in the drawing is narrower on the upper side than on the lower side, and the oxide film 26 between the gate electrode 27 and the sidewall of the trench 24 (the oxidation on the left side of the left gate electrode 27 in FIG. 4). Compared with the film 26 and the oxide film 26 on the right side of the right gate electrode 27), the oxide film 26 between the trench source electrode 41 and the gate electrodes 27 on both sides thereof can be made sufficiently thick. Such a structure has an oxidation rate at the time of thermal oxidation of the trench source electrode 41 made of polycrystalline silicon highly doped so as to function as an electrode, as described in JP 2013-069852. The p ^- layer 23 and the n ^- layer 22 constituting the inner surface of the groove 24 can be easily manufactured by utilizing the fact that it is larger than the oxidation rate. For this reason, the capacitance between the gate electrode 27 and the source electrode 29 can be kept small.

According to this structure, the feedback capacitance Crss can be reduced. On the other hand, in this structure, since the oxide film 26 on the p ⁻ layer 23 (side surface) on the side surface of the groove 24 where the channel is formed in the MOSFET is thinned, a power MOSFET having good characteristics can be obtained. .

  Also in the semiconductor device 40 using such a shield electrode, the structure related to the groove 34 in the outer peripheral region Y can be the same as that of the semiconductor device 10 described above. Thereby, the withstand voltage between the source electrode 29 and the drain electrode 30 at the time of OFF can be improved. That is, the semiconductor device 40 can operate at high speed and has a high breakdown voltage. In this case, the trench source electrode 41 and the gate electrode 27 in the groove 24 are formed in separate steps, and the floating electrode 37 can be formed simultaneously with the trench source electrode 41 or the gate electrode 27. The method of forming the floating p-type layer 381 is the same as that of the semiconductor device 10 described above.

Although the above configuration is an n-channel power MOSFET, the conductivity type (p-type, n-type) can be reversed in all cases, and a p-channel element can be obtained in the same manner. That is, the n ⁻ layer 22 is a first semiconductor layer having a first conductivity type, and the p ⁻ layer 23 is a second semiconductor having a second conductivity type opposite to the first conductivity type. In the case of a layer, it is obvious that the same structure as described above can be formed and the same effect can be obtained. It is also clear that the same configuration can be applied to a trench gate type IGBT. In the above example, the number of outer peripheral region grooves is three and the number of cell region grooves is two. However, the configuration described above is effective when two or more outer peripheral region grooves are used regardless of the number of these.

  In the above example, the cell region grooves and the outer peripheral region grooves have the same depth, but the depths do not have to be uniform. For example, the cell region groove diameter and depth may be set to a plurality of types, and if the outer periphery region groove diameter and depth are set accordingly, the cell region X and the outer region Y can be formed simultaneously. .

10, 40, 100 Semiconductor device (power MOSFET)
20, 80 Semiconductor substrate 21, 25, 81, 85 n ⁺ layer 22, 82 n ⁻ layer (first semiconductor layer)
23, 83 p ^- layer (second semiconductor layer)
24, 84 groove (cell region groove)
26, 36, 86, 96 Oxide film 27, 87 Gate electrode 28, 88 Interlayer insulating layer 29, 89 Source electrode (first main electrode)
30, 90 Drain electrode (second main electrode)
34, 94 groove (outer peripheral area groove)
37, 97 Floating electrode (electrode in groove)
38, 98, 381, 382, 383 Floating p-type layer (embedded semiconductor layer)
41 Trench source electrode (shield electrode)
X Cell area Y Perimeter area

Claims (8)

In a semiconductor substrate comprising a first semiconductor layer having a first conductivity type,
A second semiconductor layer formed on the surface side of the semiconductor substrate from the first semiconductor layer and having a second conductivity type opposite to the first conductivity type; and the first semiconductor layer from the surface side of the semiconductor substrate. A cell region groove, which is a groove formed to reach the semiconductor layer, and a gate electrode formed in the cell region groove, and a voltage applied to the gate electrode causes the semiconductor substrate A cell region in which a current flowing between the first main electrode formed on the surface side and the second main electrode connected to the first semiconductor layer is controlled;
A plurality of outer peripheral region grooves, which are grooves adjacent to the cell region in the semiconductor substrate in plan view and formed so as to reach the first semiconductor layer from the surface side of the semiconductor substrate, are provided to control the current. An outer peripheral region having no structure; and
A semiconductor device provided with
In the outer peripheral region,
An embedded semiconductor layer having the second conductivity type surrounding the bottom of each outer peripheral region groove is provided for each outer peripheral region groove in the first semiconductor layer;
The semiconductor device according to claim 1, wherein the maximum depth from the bottom of each of the corresponding outer peripheral region grooves of each of the embedded semiconductor layers is made shallower as the distance from the cell region increases. In a cross-sectional view perpendicular to the extending direction of the outer peripheral region groove,
2. The semiconductor device according to claim 1, wherein the embedded semiconductor layer has a circular shape centering on one point at a bottom portion of the corresponding outer peripheral region groove.   The semiconductor device according to claim 2, wherein a diameter of each embedded semiconductor layer in the cross-sectional view is reduced as the distance from the cell region increases.   2. An in-groove electrode that is not directly connected to any of the first main electrode, the second main electrode, and the gate electrode is provided in the outer peripheral region groove. 4. The semiconductor device according to any one of items up to item 3.   5. The device according to claim 1, wherein the embedded semiconductor layer is not directly connected to any of the first main electrode, the second main electrode, and the gate electrode. Semiconductor device.   6. The semiconductor device according to claim 1, wherein the plurality of outer peripheral region grooves have the same depth.   The semiconductor device according to claim 6, wherein the cell region groove and the plurality of outer peripheral region grooves have the same depth.   8. The semiconductor device according to claim 1, wherein the first main electrode is a power MOSFET in which a source electrode is used and the second main electrode is a drain electrode. 9.

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