CN115966594B - MOSFET device for protecting grid electrode charge balance and manufacturing method thereof - Google Patents
MOSFET device for protecting grid electrode charge balance and manufacturing method thereof Download PDFInfo
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Abstract
The application relates to a MOSFET device for protecting grid charge balance, which comprises a substrate, a first epitaxial structure for forming a multi-layer isolation grid well, a second epitaxial structure for forming a shielding electric field and a third epitaxial structure which forms a space charge region together with the second epitaxial structure. A plurality of grid grooves are formed in the third epitaxial structure. And forming a shielding electric field through the second epitaxial structure to protect the position with higher electric field line density at the bottom surface of the grid electrode groove. Meanwhile, the second epitaxial structure and the third epitaxial structure are combined to form a space charge region, so that an electric field part at the bottom of the grid electrode groove is transferred into the space charge region, the electric field at the bottom of the grid electrode groove is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized. And finally, reducing the JFET effect in the MOSFET through the isolated gate well, and jointly acting with a space charge region formed by the second epitaxial structure and the third epitaxial structure to reduce the conduction loss of the MOSFET.
Description
Technical Field
The present disclosure relates to the field of semiconductor devices, and more particularly, to a MOSFET device for protecting gate charge balance and a method for fabricating the same.
Background
The MOSFET is a short for metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor), which is a field effect transistor widely used in analog circuits and digital circuits. The MOSFET includes a source, a gate and a drain, and the charge balance of the gate affects the gate voltage, which in turn determines the on or off state between the source and the drain, and also affects the on performance and operational reliability of the entire MOSFET.
Chinese patent publication No. CN113851524a discloses a multi-source MOS transistor common gate charge balance chip structure and a method for manufacturing the same, the structure mainly includes a drain substrate, a common gate filler, a charge balance filler, a plurality of contact hole structures, and source and gate cover layers. The source electrode cover layer receives the drive conduction of a common gate filling body communicated with the gate electrode cover layer to the back surface of the drain electrode substrate; the charge balance filling body is provided with a balance part positioned below the bottom of the common gate filling body and a source contact part integrally connected and positioned in the balance groove, so that the top surface height difference is formed. In the primary hole opening process after slotting, when the gate electrode contact hole structure is drilled in the common gate electrode filling body, the balance gate electrode contact hole structure is also drilled in the source contact part, so that the field effect transistor structure has the effect of balancing charges at the bottom of the common gate electrode of the MOS transistor, the resistance of the drift layer is stably reduced, the densification of the trench type MOS transistor is realized, and the surface contact hole process is in place in one step.
Chinese patent publication No. CN114242768A discloses a silicon carbide MOSFET device with improved gate bottom charge balance and a method of fabrication, the device comprising an epitaxial wafer structure having charge balance columns, a buried gate structure, a source structure at the top layer and a drain structure at the bottom layer, the epitaxial wafer structure having a channel compliant layer formed on the silicon carbide epitaxial layer after trenching. And forming non-planar ohmic contact between the source electrode structure and the epitaxial wafer structure by utilizing contact grooves on two sides of the gate electrode structure. The charge balance column is arranged below the grid groove and the contact groove and is basically formed by a preset laminated well, so that the charge balance column is prevented from penetrating into the silicon carbide substrate of the epitaxial wafer structure. The method has the effect of standardizing the bottom depth and the appearance of the grid bottom charge balance junction to be better in cross section column shape, so as to solve the defects that the charge balance junction cannot adjust the injection concentration and cannot form the electric property instability of the junction side column shape and the junction bottom depth along with the change of the groove depth on the basis of the arrangement of the channel compliant layer.
Disclosure of Invention
Based on this, it is necessary to provide a MOSFET device for protecting the charge balance of the gate electrode to improve the reliability and the turn-on performance of the MOSFET device.
A MOSFET device that protects gate charge balance, comprising:
a substrate;
the first epitaxial structure is formed on the substrate, and a multi-layer isolation gate well is formed in the first epitaxial structure;
a second epitaxial structure formed on the first epitaxial structure; the second epitaxial structure is provided with a connecting junction with the bottom end connected with the multi-layer isolation gate well, and the width of the connecting junction is smaller than that of the multi-layer isolation gate well;
a third epitaxial structure formed on the second epitaxial structure; the top end of the connecting structure is connected with the active layer of the third epitaxial structure; the third epitaxial structure is provided with a plurality of gate trenches, the multi-layer isolation gate well is positioned between the gate trenches, the gate trenches penetrate through the third epitaxial structure, and the bottom surface of the gate trench and corners on two sides of the bottom surface are positioned in the second epitaxial structure; a source electrode field layer is formed in the surface layer of the third epitaxial structure, and the source electrode field layer is positioned on the active layer;
the grid filling body is arranged in the grid groove;
an interlayer film disposed on the third epitaxial structure to cover the source region layer;
the third epitaxial structure is provided with a contact groove for filling a source electrode, the contact groove is aligned to the connection and penetrates through the interlayer film, the source electrode field layer is exposed on the side wall of the contact groove, and the bottom surface of the contact groove and corners on two sides of the bottom surface are located in the active layer of the third epitaxial structure.
Through the technical scheme, the second epitaxial structure can form a shielding electric field, the unfolded shielding electric field can protect the grid electrode positioned in the grid electrode groove so as to relieve electron tunneling effect generated by dense electric field lines on the bottom surface of the grid electrode and the corners of two sides of the bottom surface, and therefore charges are led to cross potential energy barriers from the bottom of the grid electrode to generate leakage current, and MOSFET power consumption is increased. The third epitaxial structure and the second epitaxial structure are combined to form a space charge region, so that an electric field part at the bottom of the grid electrode groove is transferred into the space charge region, the electric field at the bottom of the grid electrode groove is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized. The isolated gate well can reduce the JFET effect in the MOSFET, and the isolated gate well and the space charge region formed by the second epitaxial structure and the third epitaxial structure cooperate to reduce the conduction loss of the MOSFET.
In one embodiment, the first epitaxial structure is formed by stacking a plurality of epitaxial layers, and the second epitaxial structure has a thickness less than the thickness of the epitaxial layers.
Through the technical scheme, the first epitaxial structure is formed by stacking multiple layers of epitaxial layers, and the problems that the isolation gate well in the first epitaxial structure is unstable in electric performance and cannot be adjusted in concentration due to the fact that the thickness of the isolation gate well at the bottom is deeper, and the accuracy of the isolation gate well at the bottom cannot be controlled are solved. The thickness of the second epitaxial structure is less than the thickness of the epitaxial layer such that the second epitaxial structure is relatively more depleted to form a shielded electric field.
In one embodiment, the ion doping concentration in the second epitaxial structure is less than the ion doping concentration of the epitaxial layer, but not less than 20% of the ion doping concentration of the epitaxial layer.
By the technical scheme, the ion doping concentration of the second epitaxial structure is controlled to be 20% of the ion doping concentration in the epitaxial layer, so that majority carriers in the second epitaxial structure can be rapidly exhausted to form a shielding electric field, and meanwhile, the concentration is enough to maintain the carrier requirement when the second epitaxial structure is conducted.
In one embodiment, a gate oxide layer is formed on the inner wall of the gate trench, and the thickness of the bottom surface of the gate oxide layer is greater than the thickness of the side surface.
Through the technical scheme, the electric field line density at the bottom surface of the grid electrode groove and the corners at the two sides of the bottom surface is high, and electron tunneling is relatively easy to occur. Thickening the gate oxide layer at the bottom of the gate trench can prevent charge from crossing there to generate leakage current, thereby reducing the conduction loss of the MOSFET.
In one embodiment, the source electrode includes a source contact layer and a source pad layer, which are sequentially disposed on the interlayer film.
By the technical scheme, the source electrode liner layer is used for forming a contact electrode so as to conduct an external circuit. The source contact layer is filled between the contact groove and the third epitaxial structure and the source liner layer so as to prevent metal atoms of the source liner layer from diffusing towards the third epitaxial structure while ohmic contact is formed.
In one embodiment, a protection region is formed on the bottom surface of the contact trench, and the ion doping concentration of the protection region is greater than that of the surrounding region.
According to the technical scheme, the contact groove is used for directly electrically contacting with the source electrode, so that the high ion doping concentration of the protection area ensures that enough carriers exist at the contact position of the source electrode in the contact groove for carrying out charge transfer, and the problem of poor conduction of the contact point due to insufficient carrier quantity caused by diffusion of ions at the bottom of the contact groove to the periphery is prevented.
In one embodiment, the ratio of the width of the connection junction to the isolation gate well is in the range of 0.2-1.
Through the technical scheme, the third epitaxial structure is connected to the isolation gate well through the connection, the width of the connection is set to be 0.2 of the width of the isolation gate well, the electric connection between the third epitaxial structure and the isolation gate well can be ensured, the space of the second epitaxial structure is also prevented from being occupied, and the formation of a shielding electric field is prevented from being influenced.
The application also provides a manufacturing method of the MOSFET device for protecting the charge balance of the grid electrode, which comprises the following steps:
providing a substrate;
forming a first epitaxial structure for arranging isolation gates on the substrate, and forming a multi-layer isolation gate well in the first epitaxial structure;
forming a second epitaxial structure for shielding an electric field on the first epitaxial structure; the second epitaxial structure is provided with a connecting junction with the bottom end connected with the multi-layer isolation gate well, and the width of the connecting junction is smaller than that of the multi-layer isolation gate well;
forming a third epitaxial structure for providing a channel on the second epitaxial structure; the top end of the connecting structure is connected with the active layer of the third epitaxial structure;
a plurality of gate trenches are formed in the upper surface of the third epitaxial structure, the multi-layer isolation gate well is located between the gate trenches, the gate trenches penetrate through the third epitaxial structure, and the bottom surface of the gate trenches and corners on two sides of the bottom surface are located in the second epitaxial structure;
setting a gate filling body in the gate trench;
forming a source electrode field layer in the surface layer of the third epitaxial structure, wherein the source electrode field layer is positioned on the active layer;
disposing an interlayer film on the third epitaxial structure to cover the source region layer;
and forming a contact groove in the third epitaxial structure for filling the source electrode layer, wherein the contact groove is aligned to the connection and penetrates through the interlayer film, the source electrode field layer is exposed on the side wall of the contact groove, and the bottom surface of the contact groove and the corners on two sides of the bottom surface are positioned in the active layer of the third epitaxial structure.
Through the technical scheme, the multi-layer isolation gate well is arranged in the first epitaxial structure, the second epitaxial structure is formed on the first epitaxial structure to generate the shielding electric field, the unfolded shielding electric field can protect the grid electrode positioned in the grid electrode groove, so that electron tunneling effect generated by electric field lines densely arranged on the bottom surface of the grid electrode and the corners of the two sides of the bottom surface is relieved, and leakage current generated by charges crossing potential energy barriers from the bottom of the grid electrode is increased, and MOSFET power consumption is increased. The third epitaxial structure and the second epitaxial structure are combined to form a space charge region, so that an electric field part at the bottom of the grid electrode groove is transferred into the space charge region, the electric field at the bottom of the grid electrode groove is reduced, and the working reliability of the MOSFET is improved. The isolated gate well can reduce the JFET effect in the MOSFET, and the isolated gate well and the space charge region formed by the second epitaxial structure and the third epitaxial structure cooperate to reduce the conduction loss of the MOSFET.
In one embodiment, the step of forming the first epitaxial structure specifically includes:
growing an epitaxial layer to form an upper surface of the first epitaxial structure;
an injection window is formed on the upper surface of the epitaxial layer;
implanting ions into the epitaxial layer through the implantation window to form a single-layer isolated gate well in the epitaxial layer;
and sequentially repeating the steps of growing the epitaxial layer, opening the implantation window and implanting ions until the thickness of the first epitaxial structure formed by stacking a plurality of epitaxial layers reaches a set value.
According to the technical scheme, the first epitaxial structure is formed by stacking the multiple layers of epitaxial layers, and the multiple layers of isolation gate wells are formed by injecting ions for multiple times along with the growth of the epitaxial layers.
In one embodiment, the thickness of the isolation gate well is smaller than the thickness of the epitaxial layer, and the plurality of layers of isolation gate wells are disposed separately from each other, and after the step of forming the first epitaxial structure, the method further includes the steps of:
implanting ions from the implantation window;
and heating the epitaxial region at high temperature to enable the plurality of layers of isolation gate traps to be integrated through ion diffusion connection.
Through the technical scheme, ions in the isolation gate wells are spontaneously diffused by high-temperature heating, so that multiple layers of originally separated isolation gate wells are uniformly connected together to form a whole, and the connection consistency of each layer of isolation gate wells is ensured.
In summary, the present application at least includes one of the following beneficial technical effects:
1. a MOSFET device having high reliability, high on-state performance and high switching performance is provided.
2. The second epitaxial structure can form a shielding electric field, and the unfolded shielding electric field can protect a grid filling body positioned in the grid groove so as to relieve electron tunneling effect generated by dense electric field lines on the bottom surface of the grid and the corners of two sides of the bottom surface, so that charges cross potential energy barriers from the bottom of the grid to generate leakage current to increase MOSFET power consumption.
3. The third epitaxial structure and the second epitaxial structure are combined to form a space charge region, so that an electric field part at the bottom of the grid electrode groove is transferred into the space charge region, the electric field at the bottom of the grid electrode groove is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized.
4. The isolated gate well can reduce the JFET effect in the MOSFET, and the isolated gate well and the space charge region formed by the second epitaxial structure and the third epitaxial structure cooperate to reduce the conduction loss of the MOSFET.
Drawings
Fig. 1 is a schematic structural cross-section of a MOSFET device according to an embodiment of the present application;
fig. 2 is a schematic structural cross-section of a MOSFET device of step S1 in an embodiment of the present application;
fig. 3 is a schematic structural cross-section of a MOSFET device of step S2 in an embodiment of the present application;
fig. 4 is a schematic structural cross-section of a MOSFET device of step S3 in an embodiment of the present application;
fig. 5 is a schematic structural cross-section of a MOSFET device of step S3 in an embodiment of the present application;
fig. 6 is a schematic structural cross-section of a MOSFET device of step S3 in an embodiment of the present application;
fig. 7 is a schematic structural cross-section of the final state of the MOSFET device of step S3 in an embodiment of the present application;
fig. 8 is a schematic structural cross-section of a MOSFET device of step S4 in an embodiment of the present application;
fig. 9 is a schematic structural cross-section of a MOSFET device of step S5 in an embodiment of the present application;
fig. 10 is a schematic structural cross-section of a MOSFET device of step S6 in an embodiment of the present application;
fig. 11 is a schematic structural cross-section of a MOSFET device in step S7 in an embodiment of the present application;
fig. 12 is a schematic structural cross-section of a MOSFET device of step S8 in an embodiment of the present application;
fig. 13 is a schematic structural cross-section of a MOSFET device of step S9 in an embodiment of the present application;
fig. 14 is a schematic structural cross-sectional view of a MOSFET device of step S10 in an embodiment of the present application;
fig. 15 is a schematic structural cross-section of a MOSFET device in step S11 according to an embodiment of the present application;
fig. 16 is a schematic structural cross-section of the MOSFET device of step S12 in an embodiment of the present application;
fig. 17 is a schematic structural cross-section of a MOSFET device in step S13 in an embodiment of the present application.
Reference numerals illustrate:
10. a substrate; 20. a first epitaxial structure; 21. an isolation gate well; 22. an epitaxial layer; 23. an oxide film; 23A, an injection window; 30. a second epitaxial structure; 31. connecting; 40. a third epitaxial structure; 41. an active layer; 42. a source electrode field layer; 43. a gate trench; 43A, gate oxide; 44. a contact trench; 44A, a guard zone; 50. a gate filler; 60. an interlayer film; 70. a source electrode; 71. a source contact layer; 72. a source liner layer; 73. a passivation layer; 80. a drain electrode; 900. and (3) masking.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is, however, susceptible of embodiment in many other forms than those described herein and similar modifications can be made by those skilled in the art without departing from the spirit of the application, and therefore the application is not to be limited to the specific embodiments disclosed below.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a MOSFET device according to an embodiment of the present application. The MOSFET device includes a substrate 10, a first epitaxial structure 20, a second epitaxial structure 30, a third epitaxial structure 40, a gate filler 50, an interlayer film 60, a source 70, and a drain 80. The first epitaxial structure 20, the second epitaxial structure 30 and the third epitaxial structure 40 are sequentially disposed on the substrate 10, a multi-layer isolation gate well 21 is formed in the first epitaxial structure 20, and a connection junction 31 connecting the isolation gate well 21 and the active layer 41 of the third epitaxial structure 40 is formed in the second epitaxial structure 30. The third epitaxial structure 40 includes an active layer 41 and a source region layer 42, and a gate trench 43 and a contact trench 44 are further formed on the third epitaxial structure 40, where the gate trench 43 penetrates through the third epitaxial structure 40 until the bottom is located in the second epitaxial structure 30. An interlayer film 60 is further provided on the source region layer 42, and the contact trench 44 passes through the interlayer film 60 and the source region layer 42.
The first epitaxial structure 20 is formed on the upper side of the substrate 10 and is grown in a homogeneous manner with the substrate 10. Specifically, the substrate 10 is a heavily n-doped wafer, and the first epitaxial structure 20 is a lightly n-doped wafer to collectively form an n-type drift region of the MOSFET device. In this embodiment, the first epitaxial structure 20 is formed by stacking multiple epitaxial layers 22, and the total thickness is 1um-6um, so that the problems of unstable electrical performance and unadjustable concentration caused by uncontrollable precision of the bottom isolation gate well 21 due to deeper thickness of the isolation gate well 21 in the first epitaxial structure 20 can be avoided. The drain electrode 80 is disposed on the bottom surface of the substrate 10 and has the same width as the substrate 10 to facilitate parallel connection of the drain electrode 80.
An isolation gate well 21 is disposed within the first epitaxial structure 20 to isolate the gates on both sides. Specifically, the isolation gate well 21 includes a plurality of layers, each layer of isolation gate well 21 is formed in synchronization with the corresponding epitaxial layer 22, and the plurality of layers of isolation gate wells 21 are integrally connected with the superposition of the epitaxial layers 22. The bottom surface of the isolation gate well 21 does not penetrate the bottom surface of the first epitaxial structure 20 to avoid direct conduction between the substrate 10 and the isolation gate well 21. Specifically, in this embodiment, the width of the isolation gate well 21 is 1um-5um, and the ion type implanted therein is p-type ion.
The second epitaxial structure 30 is formed on the first epitaxial structure 20 for forming a shield electric field. Specifically, the thickness of the second epitaxial structure 30 is less than the thickness of the single epitaxial layer 22 and the ion doping concentration is less than the ion doping concentration of the first epitaxial structure 20, so that the second epitaxial structure 30 is relatively more prone to depleting carriers, and ions left after carrier depletion generate a shielding electric field to prevent further diffusion of carriers.
In particular, in this embodiment, the second epitaxial structure 30 is doped with n-type ions at a doping concentration of 20% of the first epitaxial structure 20, so that the majority carriers in the second epitaxial structure 30 are rapidly depleted to form a shielding electric field, while the concentration is sufficient to maintain the carrier requirements at conduction.
The second epitaxial structure 30 further has a connection structure 31 therein, and the connection structure 31 connects the isolation gate well 21 on the bottom surface and the active layer 41 on the top surface. Specifically, the connection junction 31 penetrates through the second epitaxial structure 30, and has a width smaller than that of the isolation gate well 21, so as to ensure electrical connection between the third epitaxial structure 40 and the isolation gate well 21, and avoid occupying space of the second epitaxial structure 30 and affecting formation of the shielding electric field. In particular, in the present embodiment, the width of the connection 31 is preferably 0.2 of the width of the isolation gate well 21.
The third epitaxial structure 40 includes an active layer 41 and a source field layer 42. Specifically, the active layer 41 is disposed on the upper side of the second epitaxial structure 30, the source field layer 42 is disposed on the upper side of the active layer 41 in a covering manner, and different types of doping ions are respectively injected into the active layer 41 and the source field layer 42 to form a space charge region. Specifically, in this embodiment, the source field layer 42 is doped with n-type ions, the active layer 41 is doped with p-type ions, and the combination of the n-type ion doped second epitaxial structure 30 forms an npn-type space charge region.
The gate trench 43 is opened on the third epitaxial structure 40 for disposing the gate filler 50. The opening of the gate trench 43 is located on the upper surface of the source region layer 42, through the source region layer 42 and the active layer 41, until the bottom of the gate trench 43 is located in the second epitaxial structure 30. Specifically, the bottom surface and the corners on two sides of the bottom surface of the gate trench 43 are located in the second epitaxial structure 30, so that the shielding electric field developed in the second epitaxial structure 30 can protect the position where the electric field lines at the bottom surface of the gate trench 43 are denser, preventing charges from leaking from the bottom of the gate trench 43 to form leakage current, and increasing the power consumption of the MOSFET. Specifically, in this embodiment, the gate filler 50 is formed by polysilicon deposition.
In some embodiments, a gate oxide layer 43A is further formed on the inner wall of the gate trench 43 for protecting the gate filler 50. Specifically, the bottom surface of the gate oxide layer 43A has a thickness greater than the thickness of the side surface, so as to further protect the bottom surface of the gate trench 43 and prevent the charges from generating electron tunneling effect at the bottom of the gate trench 43 to form leakage current.
The interlayer film 60 is disposed on the third epitaxial structure 40 to cover the source region layer 42 and electrically isolate the source 70 located on the upper side of the interlayer film 60 from the third epitaxial structure 40 located on the lower side of the interlayer film 60.
The interlayer film 60 is provided with a contact trench 44, the contact trench 44 penetrates through the interlayer film 60 and the source region layer 42, and the bottom is located in the active layer 41 for filling the source 70, so that the source 70 is electrically connected with the third epitaxial structure 40 through the contact trench 44.
In some embodiments, the bottom of the contact trench 44 is formed with a guard region 44A, the guard region 44A being ion doped with a greater ion doping concentration than the surrounding region. Specifically, the protection region 44A ensures that the contact position of the source 70 in the contact trench 44 has enough carriers for charge transfer by using the high p-type ion doping concentration, so that the problem of poor conduction of the contact point due to insufficient number of carriers caused by diffusion of ions at the bottom of the contact trench 44 to the periphery is prevented.
The source electrode 70 includes a source contact layer 71 and a source liner layer 72. The source liner layer 72 is used to form a contact electrode to conduct an external circuit. The source contact layer 71 is filled between the contact trench 44 and the source liner layer 72 of the third epitaxial structure 40 to prevent metal atoms of the source liner layer 72 from diffusing toward the third epitaxial structure 40 while ohmic contact is being formed. Specifically, in the present embodiment, the source pad layer 72 is made of an Al metal material, and the source contact layer 71 is made of a Ti metal material.
In other embodiments, the top surface of the source liner layer 72 is also formed with a passivation layer 73 to protect the source 70 from the outside air. Specifically, the passivation layer 73 may be dense Al2O3 formed by oxidizing Al, and may be capable of preventing air corrosion. The passivation layer 73 can be adaptively adjusted by a person skilled in the art according to common general knowledge in the art.
In addition, the application also provides a manufacturing method of the MOSFET device for protecting the charge balance of the grid electrode, and the process steps are described below.
Referring to fig. 2, a substrate 10 is provided and a first epitaxial structure 20 is formed on the substrate 10 in accordance with step S1. The method comprises the following specific steps: first, a layer of a concentration 10 is grown on a substrate 10 heavily doped with n-type ions 15 ions/cm 2 To 10 17 ions/cm 2 The thickness of the epitaxial layer 22 is 1um to 6um. An oxide film 23 with a thickness of 300A-500A is then grown on the surface of the epitaxial layer 22 for protecting the wafer from scratches and contamination during processing and for implantation masking during ion doping. Finally, a mask 900 is provided on the surface of the oxide film 23 to etch the oxide film 23 to open the implantation window 23A.
Referring to fig. 3, ions are implanted from the implantation window 23A to form the isolation gate well 21 in accordance with step S2. Specifically, p-type ions are implanted into the epitaxial layer 22 through the implantation window 23A, the width of the implantation region is 1um-5um, and the implantation dose is 10 12 ions/cm 2 To 10 14 ions/cm 2 The implantation energy is 60keV-1000keV. The isolation gate well 21 formed by implanting ions is located inside the epitaxial layer 22.
Referring to fig. 4, the first two steps of growing the epitaxial layer 22, opening the implantation window 23A, and implanting ions are repeated in step S3. The method comprises the following steps: the oxide film 23 on the surface is removed on the original epitaxial layer 22, then a new epitaxial layer 22 is grown again on the original epitaxial layer 22, and the oxide film 23 is grown on the new epitaxial layer 22 and the implantation window 23A is opened using the mask 900.
It should be noted that the thickness of each epitaxial layer 22, the ion doping concentration, the position of the implantation window 23A, and other parameters are all fixed, so as to ensure that each epitaxial layer 22 has the same properties, and the first epitaxial structure 20 formed by stacking the multiple epitaxial layers 22 has better uniformity.
Referring to fig. 5 and 6, the following steps of growing the epitaxial layer 22, opening the implantation window 23A, and implanting ions are repeated in accordance with step S3. The p-type ions are injected into the latest epitaxial layer 22 again through the injection window 23A to form the isolation gate well 21, so that the corresponding isolation gate well 21 is formed in each epitaxial layer 22. The multi-layered isolation gate wells 21 are aligned in the same vertical region and are disposed apart from each other.
Referring to fig. 7, fig. 7 shows the final state of the MOSFET device in step S3 in an embodiment of the present application, when the thickness of the first epitaxial structure 20 formed by stacking the repeatedly grown epitaxial layers 22 of the MOSFET device reaches the set value, the growth is stopped for the next step.
Referring to fig. 8, a second epitaxial structure 30 is formed corresponding to step S4. The method comprises the following steps: the wafer is continued to be epitaxially grown on the first epitaxial structure 20 and the ion doping concentration of the grown second epitaxial structure 30 is controlled to be less than the ion doping concentration of the first epitaxial structure 20. In addition, the thickness of the second epitaxial structure 30, which is controlled to be grown, is smaller than the thickness of the epitaxial layer 22. In particular, in this embodiment, the second epitaxial structure 30 is doped with n-type ions having an ion doping concentration of 20% of the first epitaxial structure 20.
Referring to fig. 9, a connection 31 is formed corresponding to step S5. The method comprises the following steps: an oxide film 23 is also formed on the surface of the second epitaxial structure 30, and then an implantation window 23A is formed on the oxide film 23 using a mask 900, and p-type ions are implanted from the implantation window 23A to form the connection 31. The connection junction 31 is aligned to the isolation gate well 21, and the implantation width of the connection junction 31 is smaller than the isolation gate well 21. In particular, in the present embodiment, the width of the connection junction 31 is one fifth of the isolation gate well 21.
Referring to fig. 10, a third epitaxial structure 40 is formed corresponding to step S6. The method comprises the following steps: epitaxial layer 22 is again grown to a thickness of 1um-3um on the surface of second epitaxial structure 30 and p-type ions are implanted to form active layer 41 of third epitaxial structure 40. Then, by heating the MOSFET device, the p-type ions are subjected to ion diffusion at a high temperature, so that the isolation gate wells 21 originally arranged separately are uniformly connected together to form a whole, and the consistency of connection of each layer of isolation gate wells 21 is ensured.
Referring to fig. 11, a gate trench 43 is formed by etching in step S7. The method comprises the following steps: an oxide film 23 is formed on the surface of the active layer 41, and a photolithography region is defined using a mask 900. Thereafter, the photoresist region is etched to form a gate trench 43. Specifically, the gate trench 43 is a U-shaped trench, and the bottom surface of the gate trench 43 is etched to the second epitaxial structure 30.
Referring to fig. 12, a gate oxide layer 43A is formed corresponding to step S8. The method comprises the following steps: the oxide film 23 on the surface of the active layer 41 is first removed, and then a new oxide layer is formed on the surface of the active layer 41 and the surface of the gate trench 43, wherein the oxide layer grown on the inner wall surface of the gate trench 43 is the gate oxide layer 43A. The growth thickness of the gate oxide layer 43A at the bottom surface of the control gate trench 43 is greater than the growth thickness of the gate oxide layer 43A at the side surface, so as to achieve better protection of the bottom surface of the gate trench 43.
Referring to fig. 13, a gate filling body 50 is formed corresponding to step S9. The method comprises the following steps: polysilicon is deposited by chemical vapor deposition over the gate trench 43 and the active layer 41 to form a gate filler 50. Chemical vapor deposition is a common technical means in the art, and is not the focus of the process in this application, and those skilled in the art can also perform the process without description, so it is not repeated here.
Referring to fig. 14, the surface of the polysilicon is planarized in step S10. The method comprises the following steps: the unnecessary gate filler 50 on the surface of the active layer 41 is removed using a chemical mechanical polishing process (Chemical Mechanical Polishing, abbreviated as CMP) so that the gate filler 50 is filled only inside the gate trench 43 and so that the gate filler 50 is on the same flat level as the active layer 41. The CMP process is also common general knowledge in the art and is not the focus of the process of the present application, and is not described here in detail.
Referring to fig. 15, a source region layer 42 and a dielectric film are formed corresponding to step S11. The method comprises the following steps: a mask 900 is provided on the surface of the active layer 41 to perform patterning, and high-concentration n-type ions are implanted into the surface of the active layer 41 according to a pattern preset by the mask 900 to perform doping, so as to form an n-type source region layer 42. Finally, an insulating interlayer film 60 is formed over the entire source region layer 42 and the gate pad 50 to isolate the source 70 from the third epitaxial structure 40 on both sides of the interlayer film 60.
Referring to fig. 16, a contact trench 44 is formed corresponding to step S12. The method comprises the following steps: a contact trench 44 region is defined and patterned on the surface of the interlayer film 60, and then etching is performed on the contact trench 44 region to form a U-shaped contact trench 44. The contact trench 44 penetrates the interlayer film 60 and the source region layer 42, and is used for communicating the source electrode 70 and the third epitaxial structure 40. The bottom surface of the contact trench 44 is etched into the active layer 41, and then p-type ions with high concentration are implanted into the bottom surface of the contact trench 44 to form a protection region 44A, and the ion doping concentration of the protection region 44A is made to be greater than that of the peripheral region, so as to prevent the problem of poor conduction of the contact point due to insufficient number of carriers caused by diffusion of ions at the bottom of the contact trench 44 to the periphery. Finally, at N 2 And (3) carrying out annealing heat treatment in the atmosphere of protective gas to restore the structure of the crystal and eliminate lattice defects.
Referring to fig. 17, the source electrode 70 is filled in step S13. The method comprises the following steps: the source contact layer 71 is filled on the interlayer film 60 and in the contact trench 44, and then the source contact layer 71 is annealed to reduce residual stress of the source contact layer 71 and eliminate structural defects of metal. Then, a source liner layer 72 is formed on the source contact layer 71 by a sputtering process on the source contact layer 71. Thereafter, an etching region is defined and etched on the surface of the source pad layer 72 using a mask 900, and a contact electrode is formed.
Specifically, in the present embodiment, the source contact layer 71 is made of a metal Ti material, and the source liner layer 72 is made of a metal Al material.
Referring to fig. 1 again, a passivation layer 73 is formed corresponding to step S14. The method comprises the following steps: metal passivation is performed on the back of the source liner layer 72 to form a passivation layer 73 that protects the source electrode 70 and other structures from the outside air.
The implementation principle of the MOSFET device of the embodiment of the application is as follows: a shield electric field is formed by the second epitaxial structure 30 to protect the location of the gate trench 43 where the electric field line density is high. Meanwhile, the second epitaxial structure 30 and the third epitaxial structure 40 are combined to form a space charge region, so that an electric field part at the bottom of the gate trench 43 is transferred into the space charge region, the electric field at the bottom of the gate trench 43 is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized. Finally, the JFET effect in the MOSFET is reduced by isolating the gate well 21, which cooperates with the space charge region formed by the second epitaxial structure 30 and the third epitaxial structure 40 to reduce the on-loss of the MOSFET.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A MOSFET device for protecting gate charge balance, comprising:
a substrate (10);
a first epitaxial structure (20) formed on the substrate (10), a multi-layer isolation gate well (21) being formed within the first epitaxial structure (20);
a second epitaxial structure (30) formed on the first epitaxial structure (20); the second epitaxial structure (30) is provided with a connecting junction (31) with the bottom end connected with the multi-layer isolation gate well (21), and the width of the connecting junction (31) is smaller than that of the multi-layer isolation gate well (21);
a third epitaxial structure (40) formed on the second epitaxial structure (30); the top end of the connecting junction (31) is connected with an active layer (41) of the third epitaxial structure (40); the third epitaxial structure (40) is provided with a plurality of gate trenches (43), the multi-layer isolation gate well (21) is positioned between the gate trenches (43), the gate trenches (43) penetrate through the third epitaxial structure (40), and the bottom surface and two side corners of the bottom surface of the gate trenches (43) are positioned in the second epitaxial structure (30); a source electrode (70) field layer (42) is formed in the surface layer of the third epitaxial structure (40), and the source electrode field layer (42) is located on the active layer (41);
a gate filler (50) disposed in the gate trench (43);
an interlayer film (60) provided on the third epitaxial structure (40) so as to cover the source region layer (42);
the third epitaxial structure (40) is provided with a contact groove (44) for filling the source (70), the contact groove (44) is aligned to the connecting junction (31) and penetrates through the interlayer film (60), the source field layer (42) is exposed on the side wall of the contact groove (44), and the bottom surface and the corners of the two sides of the bottom surface of the contact groove (44) are located in the active layer (41) of the third epitaxial structure (40).
2. The protective gate charge balanced MOSFET device of claim 1, wherein the first epitaxial structure (20) is formed by stacking a plurality of epitaxial layers (22), and the second epitaxial structure (30) has a thickness less than a thickness of the epitaxial layers (22).
3. The protection gate charge balanced MOSFET device of claim 2, wherein the ion doping concentration in the second epitaxial structure (30) is less than the ion doping concentration of the epitaxial layer (22) but not less than 20% of the ion doping concentration of the epitaxial layer (22).
4. The MOSFET device of claim 1, wherein a gate oxide layer (43A) is formed on an inner wall of the gate trench (43), and wherein a bottom surface thickness of the gate oxide layer (43A) is greater than a side surface thickness.
5. The MOSFET device of claim 1, wherein the source (70) comprises a source contact layer (71) and a source liner layer (72), the source contact layer (71) and the source liner layer (72) being disposed in sequence on the interlayer film (60).
6. The protective gate charge balanced MOSFET device of claim 1, wherein a protective region (44A) is formed on a bottom surface of the contact trench (44), the protective region (44A) having a greater ion doping concentration than surrounding regions.
7. A MOSFET device with balanced protection gate charge according to any of claims 1 to 6, characterized in that the width ratio of the connection junction (31) to the isolation gate well (21) is in the range of 0.2-1.
8. A method of fabricating a MOSFET device for protecting gate charge balance, comprising:
providing a substrate (10);
forming a first epitaxial structure (20) for providing isolation gates on the substrate (10), and forming a multi-layer isolation gate well (21) in the first epitaxial structure (20);
forming a second epitaxial structure (30) for shielding an electric field on the first epitaxial structure (20); the second epitaxial structure (30) is provided with a connecting junction (31) with the bottom end connected with the multi-layer isolation gate well (21), and the width of the connecting junction (31) is smaller than that of the multi-layer isolation gate well (21);
forming a third epitaxial structure (40) for providing a channel on the second epitaxial structure (30); the top end of the connecting junction (31) is connected with an active layer (41) of the third epitaxial structure (40);
a plurality of gate trenches (43) are formed in the upper surface of the third epitaxial structure (40), the multi-layer isolation gate well (21) is located between the gate trenches (43), the gate trenches (43) penetrate through the third epitaxial structure (40), and the bottom surface and two side corners of the bottom surface of the gate trenches (43) are located in the second epitaxial structure (30);
disposing a gate filler (50) within the gate trench (43);
-forming a source field layer (42) in a surface layer of the third epitaxial structure (40), the source field layer (42) being located on the active layer (41);
-providing an interlayer film (60) on the third epitaxial structure (40) to cover the source field layer (42);
and forming a contact trench (44) in the third epitaxial structure (40) for filling a source electrode (70) layer, wherein the contact trench (44) is aligned to the connection junction (31) and penetrates through the interlayer film (60), the source electrode field layer (42) is exposed on the side wall of the contact trench (44), and the bottom surface and the corners of the two sides of the bottom surface of the contact trench (44) are positioned in the active layer (41) of the third epitaxial structure (40).
9. The method of manufacturing a MOSFET device for protecting gate charge balance according to claim 8, wherein said step of forming a first epitaxial structure (20) comprises:
growing an epitaxial layer (22) to form an upper surface of the first epitaxial structure (20);
an injection window (23A) is formed on the upper surface of the epitaxial layer (22);
implanting ions into the epitaxial layer (22) through the implantation window (23A) to form a single-layer isolated gate well (21) in the epitaxial layer (22);
and sequentially repeating the steps of growing the epitaxial layer (22), forming the implantation window (23A) and implanting ions until the thickness of the first epitaxial structure (20) formed by stacking multiple epitaxial layers (22) reaches a set value.
10. The method of manufacturing a MOSFET device according to claim 9, wherein the thickness of the isolation gate well (21) is smaller than the thickness of the epitaxial layer (22), and wherein a plurality of layers of the isolation gate well (21) are arranged spaced apart from each other, further comprising, after the step of forming the first epitaxial structure (20), the steps of:
implanting ions from the implantation window (23A);
and heating the epitaxial layer (22) to form a plurality of layers of isolation gate wells (21) into a whole through ion diffusion connection.
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| CN110676320A (en) * | 2018-07-03 | 2020-01-10 | 无锡华润华晶微电子有限公司 | Trench MOSFET and method of manufacturing the same |
| WO2020135735A1 (en) * | 2018-12-27 | 2020-07-02 | 无锡华润华晶微电子有限公司 | Trench mosfet and manufacturing method for trench mosfet |
| CN113990919A (en) * | 2021-10-12 | 2022-01-28 | 松山湖材料实验室 | Silicon carbide semiconductor structure, device and preparation method |
| CN114242768A (en) * | 2021-11-18 | 2022-03-25 | 深圳真茂佳半导体有限公司 | Silicon carbide MOSFET device with improved gate bottom charge balance and manufacturing method thereof |
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| US7893488B2 (en) * | 2008-08-20 | 2011-02-22 | Alpha & Omega Semiconductor, Inc. | Charged balanced devices with shielded gate trench |
| TWI405270B (en) * | 2009-01-07 | 2013-08-11 | Niko Semiconductor Co Ltd | Method for manufacturing trench mosfet device with low gate charge and the structure thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110676320A (en) * | 2018-07-03 | 2020-01-10 | 无锡华润华晶微电子有限公司 | Trench MOSFET and method of manufacturing the same |
| WO2020135735A1 (en) * | 2018-12-27 | 2020-07-02 | 无锡华润华晶微电子有限公司 | Trench mosfet and manufacturing method for trench mosfet |
| CN113990919A (en) * | 2021-10-12 | 2022-01-28 | 松山湖材料实验室 | Silicon carbide semiconductor structure, device and preparation method |
| CN114242768A (en) * | 2021-11-18 | 2022-03-25 | 深圳真茂佳半导体有限公司 | Silicon carbide MOSFET device with improved gate bottom charge balance and manufacturing method thereof |
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