CN114564426B - Embedded multi-interface data conversion device - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G06F2213/38—Universal adapter
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Abstract
The invention belongs to the technical field of multi-interface conversion equipment, and particularly relates to an embedded multi-interface data conversion device, which comprises: the embedded hardware comprises an embedded hardware main board and an embedded hardware platform arranged on the embedded hardware main board; the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of power supply and signals; the central processor is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for the connection of external equipment; the central processing unit is also connected with an EEPROM chip with an I2C interface; the central processing unit is also connected with a Flash chip with a QSPI interface; the central processing unit is also connected with a first connector which is convenient for the connection of external equipment; the CPU is also connected with a second connector which is convenient for the connection of external equipment.
Description
Technical Field
The invention belongs to the technical field of multi-interface conversion equipment, and particularly relates to an embedded multi-interface data conversion device.
Background
Currently, the manufacturing industry is in the key period of transformation and upgrading, the new generation of information technology is being tightly fused with the production and manufacturing technology, various Internet of things are widely applied, and the realization of the interconnection and the intercommunication of production equipment has become the development trend of industrial automation. The production equipment is used as information sensing nodes, tens of thousands of data nodes are distributed in the Internet of things environment, and each node is used for data updating in working time. Because the data information is completely dispersed, the node support data transmission protocols are different, and great difficulty is brought to data acquisition and data query.
In the fields of industrial automation, automobile electronics, sensor networks and the like, the method has functional requirements on calculation and control, data acquisition, inter-equipment communication and the like, and various different application requirements generally require customized hardware design, for example, the communication interfaces of the industrial control equipment commonly used at present comprise RS-232, RS-485, RS-422, CAN and networks, and as different interface protocols, protocols of various communication structures are incompatible, the operation and information interaction between heterogeneous networks are difficult to carry out, the improvement of manufacturing cost is brought, and the iterative upgrading speed of hardware products is reduced.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the prior art, the present invention provides an embedded multi-interface data conversion device, which includes: the embedded hardware comprises an embedded hardware main board and an embedded hardware platform arranged on the embedded hardware main board;
The embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of power supply and signals;
The central processor is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for the connection of external equipment and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
The CPU is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
The central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the running process;
The central processing unit is also connected with a first connector which is convenient for the connection of external equipment and is used for providing a UART interface, an I2C interface and an SPI interface; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector;
The central processing unit is also connected with a second connector which is convenient for the connection of external equipment and is used for providing a UART interface, an SPI interface and an RMII interface; and a UART interface, an SPI interface, an RMII interface and a plurality of GPIO pins of the TTL level of the central processing unit are led out to the second connector.
As one of the improvements of the above technical solutions, the RS232-RS485-RS422 centralized communication interface includes a multifunctional interface chip and a third connector, where pins having TTL levels on the signal side of the multifunctional interface chip are configured on the interface side to implement any one of the RS232, RS485, and RS422 interface levels.
As one of the improvements of the above technical solutions, the multifunctional interface chip provides any one of interface levels including an RS232 interface mode, an RS485 interface mode, or an RS422 interface mode through pin configuration of a signal side connected to the central processor, and USARTn represents an nth group of interfaces when the central processor has a plurality of USART interfaces; the specific configuration structure is as follows:
Function configuration structure of RS232 interface mode: the CPU configures an eleventh pin of the multifunctional interface chip to be at a low level through the GPIO pin, at this time, a logic output USARTn _TX pin and a logic input USARTn _RX pin of the CPU are respectively connected to a sixteenth pin and a seventh pin of the multifunctional interface chip correspondingly, and a fifth pin and a fourteenth pin of the multifunctional interface chip are respectively used as output and input of an RS232 interface level;
Function configuration structure of RS485 interface mode: the CPU configures an eleventh pin of the multifunctional interface chip to be high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip to be high level through the GPIO pin, and at the moment, a logic output USARTn _TX pin and a logic input USARTn _RX pin of the CPU are respectively connected to the sixteenth pin and the eighth pin of the multifunctional interface chip correspondingly; the USARTn _DE pin of the central processing unit is used as an input/output control signal of the RS485 interface to be connected to the fifteenth pin of the multifunctional interface chip, and the sixth pin and the fifth pin of the multifunctional interface chip are used as the positive and negative of the differential input/output of the RS485 interface level;
Functional configuration structure of RS422 interface mode: the CPU configures an eleventh pin of the multifunctional interface chip to be high level through a GPIO pin, configures a twelfth pin of the multifunctional interface chip to be low level through the GPIO pin, at the moment, a logic output USARTn _TX pin and a logic input USARTn _RX pin of the CPU are respectively connected into a sixteenth pin and an eighth pin of the multifunctional interface chip, a thirteenth pin and a fourteenth pin of the multifunctional interface chip are respectively a differential input positive and a differential input negative of an RS422 level, and a sixth pin and a fifth pin of the multifunctional interface chip are respectively used as a differential output positive and a differential output negative of the RS422 level;
The central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn _RX logic input function, and the two pins are respectively connected with a seventh pin and an eighth pin of the multifunctional interface chip.
As one of the improvements of the above technical solutions, the multi-functional interface chip needs to perform interface mode configuration by the central processing unit by providing an interface level of the RS232 interface mode through pin configuration of a signal side connected with the central processing unit, which specifically includes:
The EEPROM chip is read, and the current working mode of the centralized interface is determined to be an RS232 interface mode according to the configuration parameters of the RS232 interface mode;
configuring a central processor pin connected with an eleventh pin of the multifunctional interface chip as a GPIO function, and outputting a low level;
configuring a central processor pin connected with a sixteenth pin of the multifunctional interface chip as USARTn _TX function as logic output of the USART;
and configuring a central processor pin connected with a seventh pin of the multifunctional interface chip as USARTn _RX function as logic input of the USART.
As one of the improvements of the above technical solutions, the multifunctional interface chip provides an interface level of an RS485 interface mode through pin configuration of a signal side connected with a central processing unit, and the specific process is as follows:
the EEPROM chip is read, and the current centralized interface working mode is determined to be an RS485 mode according to the RS485 interface mode configuration parameters;
configuring a central processor pin connected with an eleventh pin of the multifunctional interface chip as a GPIO function, and outputting a high level;
Configuring a central processor pin connected with a twelfth pin of the multifunctional interface chip as a GPIO function, and outputting a high level;
configuring a central processor pin connected with a sixteenth pin of the multifunctional interface chip as USARTn _TX function as logic output of the USART;
configuring a central processor pin connected with an eighth pin of the multifunctional interface chip as USARTn _RX function as logic input of USART;
And configuring a CPU pin connected with a fifteenth pin of the multifunctional interface chip as USARTn _DE function as RS485 driving enable of USART.
As one of the improvements of the above technical solutions, the multifunctional interface chip provides an interface level of an RS422 interface mode through pin configuration of a signal side connected with a central processing unit, and the specific process is as follows:
The EEPROM chip is read, and the current centralized interface working mode is determined to be an RS422 mode according to the RS422 interface mode configuration parameters;
configuring a central processor pin connected with an eleventh pin of the multifunctional interface chip as a GPIO function, and outputting a high level;
Configuring a central processor pin connected with a twelfth pin of the multifunctional interface chip as a GPIO function, and outputting a low level;
configuring a central processor pin connected with a sixteenth pin of the multifunctional interface chip as USARTn _TX function as logic output of the USART;
The CPU pin connected with the eighth pin of the multifunctional interface chip is configured to be USARTn _RX function and used as the logic input of the USART.
As one of the improvements of the above technical solutions, the power supply is divided into two power supply domains by DC/DC conversion, which includes: an interface power domain and a platform power domain;
the interface power domain and the platform power domain are electrically isolated and not grounded, and the adopted power supply mode is isolated power supply.
As one of the improvements of the technical scheme, the central processing unit is connected with the Flash chip through a QSPI interface; the central processing unit is connected with the EEPROM chip through the I2C interface, and the Flash chip and the EEPROM chip are both used for storing data.
Compared with the prior art, the invention has the beneficial effects that:
The conversion device can support multiple interface expansion and interface function conversion, can provide any one of the interface functions of RS232, RS485 and RS422 through one centralized interface, optimizes the interface and reduces the complexity of the interface.
Drawings
FIG. 1 is a schematic diagram of an embedded multi-interface data conversion device according to the present invention;
FIG. 2 (a) is a schematic diagram of the CAN-FD bus interface chip interface power domain supply;
FIG. 2 (b) is a schematic diagram of an isolated conversion of an interface power domain to a platform power domain;
FIG. 3 is a schematic diagram of CAN-FD bus interface chip power/signal dual isolation;
FIG. 4 is a schematic diagram of the electrical connections of a multi-function interface chip;
FIG. 5 (a) is a diagram showing a multi-function interface chip having an interference connection mode with a CPU;
fig. 5 (b) is a non-interference connection mode of the multifunctional interface chip and the cpu.
Fig. 6 is a flow chart of a configuration method of the RS232-RS485-RS422 centralized communication interface and the central processing unit.
Reference numerals:
1. First pin 2, second pin
3. Third pin 4 and fourth pin
5. Fifth pin 6, sixth pin
7. Seventh pin 8, eighth pin
9. Ninth pin 10, tenth pin
11. Eleventh pin 12, twelfth pin
13. Thirteenth pin 14, fourteenth pin
15. Fifteenth pin 16, sixteenth pin
17. Seventeenth pin 18, eighteenth pin
19. Nineteenth pin 20, twentieth pin
25. Twenty-fifth pin 86, eighty-sixth pin
87. Eighty-seventh pin
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides an embedded multi-interface data conversion device, which includes: the embedded hardware comprises an embedded hardware main board and an embedded hardware platform arranged on the embedded hardware main board;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of power supply and signals, which is used for realizing remote anti-interference communication;
The central processor is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for the connection of external equipment and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
The CPU is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
The central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the running process;
The central processing unit is also connected with a first connector which is convenient for the connection of external equipment and is used for providing a UART interface, an I2C interface, an SPI interface and a plurality of GPIOs; the UART interface, the SPI interface, the I2C interface and a plurality of GPIO pins of the TTL level of the central processing unit are led out to the first connector, interface function expansion is provided for the outside, and interface function expansion capacity and interface conversion capacity are improved;
the central processing unit is also connected with a second connector which is convenient for the connection of external equipment and is used for providing a UART interface, an SPI interface, an RMII interface and a plurality of GPIOs; the UART interface, the SPI interface, the RMII interface and a plurality of GPIO pins of the TTL level of the central processing unit are led out to the second connector, interface function expansion is provided for the outside, and interface function expansion capacity and interface conversion capacity are improved. Wherein +5v and +3.3v and corresponding GND are also extended out onto the first and second connectors as shown in fig. 1 and 2 for power supply of the extension circuit.
The first connector and the second connector can realize function expansion and provide multi-interface type conversion, so that different data can be collected conveniently. The UART interfaces, the SPI interfaces, the I2C interfaces and the RMII interfaces are used as expansion interfaces, so that the function expansion capability and the interface conversion capability of the embedded hardware platform are improved.
The CPU is an ARM Cortex-M7 architecture singlechip STM32H743VI with a main frequency up to 480MHz, has a double-precision floating point operation unit and a DSP instruction, integrates 2MB Flash and 1MB RAM internally, and can meet various application requirements including data processing. The central processor is a control and processing core of the embedded hardware platform, and functions provided by the embedded hardware platform are realized through on-chip programs of the singlechip.
The CAN-FD bus communication interface with double isolation of the power supply and the signal adopts an ISO1042DW chip which has 5000VRMS internal isolation conforming to UL 1577 standard and reaching 1 minute, CAN prevent noise current on a data bus or other circuits from entering the local and interfering or damaging sensitive circuits, and CAN effectively improve the anti-interference capability of an embedded hardware platform by matching with the design of an isolated power supply of the embedded hardware platform.
The model of the Flash chip with the QSPI interface is GD25S512MDFx, provides a storage space of up to 512Mbits, and can be used for recording state data and log data of an embedded hardware platform in the running process.
The EEPROM chip with the I2C interface is BL24C512A-PA, provides 512kbits storage space, and can be used for storing parameter configuration data of an embedded hardware platform or recording relatively less data.
The RS232-RS485-RS422 centralized communication interface comprises: a multi-functional interface chip and a third connector; the model of the multifunctional interface chip is MAX3160EEAP, any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode is provided on the interface side through the pin configuration of the signal side of the multifunctional interface chip with TTL level, so that the interface integration level of a hardware platform is improved, and the circuit structure can be more compact;
The RS232-RS485-RS422 centralized communication interface also adopts the same third connector to match with a multifunctional interface chip to meet the external connection requirements of the RS232 interface, the RS485 interface and the RS422 interface.
The centralized communication interface of the RS232-RS485-RS422 is realized through a multifunctional interface chip MAX3160EEAP and a connector thereof, the function configuration method is provided by a central processing unit, and the interface design multifunctional interface chip MAX3160EEAP is optimized to provide any one interface level including an RS232 interface mode, an RS485 interface mode or an RS422 interface mode through pin configuration of a signal side connected with a central processing unit STM32H743 VI. As shown in fig. 4, the specific configuration structure is as follows:
Function configuration structure of RS232 interface mode: the central processing unit stm32H743VI configures the eleventh pin 11 of the multi-functional interface chip MAX3160EEAP to be at a low level through a pd2_rs_mode network signal (i.e., a PCB trace connected through a GPIO pin), at this time, a usart2_tx signal and a usart2_rx_232 signal are respectively used as a TTL level logic output and a logic input of the central processing unit stm32H743VI, and are respectively and correspondingly connected to the sixteenth pin 16 and the seventh pin 7 of the multi-functional interface chip, and the fifth pin 5 and the fourteenth pin 14 of the multi-functional interface chip MAX3160EEAP are respectively used as an output and an input of an RS232 interface level;
Function configuration structure of RS485 interface mode: the central processing unit stm32H743VI configures the eleventh pin 11 of the multi-functional interface chip MAX3160EEAP to be at a high level through a pd2_rs_mode network signal (i.e., a PCB trace connected through a GPIO pin), and configures the twelfth pin 12 of the multi-functional interface chip MAX3160EEAP to be at a high level through a HDPLX network signal, and at this time, the usart2_tx signal and the usart2_rx422 signal are respectively used as a TTL level logic output and a logic input of the central processing unit stm32H743VI, and are respectively connected to the sixteenth pin 16 and the eighth pin 8 of the multi-functional interface chip correspondingly; the USART2_DE signal is used as an input/output control signal of the RS485 interface, and is connected to the fifteenth pin 15 of the multifunctional interface chip, and the sixth pin 6 and the fifth pin 5 of the multifunctional interface chip MAX3160EEAP form differential signals of the RS485 interface level, namely the positive and negative of the differential input/output;
Functional configuration structure of RS422 interface mode: the central processing unit stm32H743VI configures the eleventh pin 11 of the multi-functional interface chip MAX3160EEAP to be at a high level through a pd2_rs_mode network signal (i.e., a PCB trace connected through a GPIO pin), configures the twelfth pin 12 of the multi-functional interface chip MAX3160EEAP to be at a low level through a HDPLX network signal, at this time, usart2_tx and usart2_rx422 signals serve as a TTL level logic output and a logic input of the central processing unit STM32H743VI, respectively, to be connected to the sixteenth pin 16 and the eighth pin 8 of the multi-functional interface chip, respectively, the thirteenth pin 13 and the fourteenth pin 14 of the multi-functional interface chip MAX3160EEAP are respectively a differential input positive and a differential input negative of the RS422 level, and the sixth pin 6 and the fifth pin 5 of the multi-functional interface chip MAX3160EEAP are respectively serve as a differential output positive and a differential output negative of the RS422 level.
IN each of the modes RS232, RS485, and RS422, the TTL level logic input of the multi-function interface chip MAX3160EEAP is T1IN, corresponding to the sixteenth pin 16 of the multi-function interface chip MAX3160 EEAP. Multifunction interface chip as shown in fig. 5, the sixteenth pin 16 of the multifunction interface chip MAX3160EEAP is connected to the eighty-six pin 86 of the central processor STM32H743VI, and the eighty-six pin 86 of STM32H743VI is configured as a usart2_tx function. However, in different modes, the TTL level logic output pins of the multi-functional interface chip MAX3160EEAP are different, and when the multi-functional interface chip MAX3160EEAP is configured in the RS232 interface mode, the TTL level output is 7 pins R1OUT, and when the multi-functional interface chip MAX3160EEAP is configured in the RS485 or RS422 interface mode, the TTL level output is 8 pins R2OUT.
If the connection mode of the multifunctional interface chip and the central processing unit circuit shown in fig. 5 (a) is adopted, since the 7-pin R1OUT and the 8-pin R2OUT are both outputs, the two outputs correspond to the same usart2_rx signal input, which would affect the normal operation of the central processing unit STM32H743 VI. In the invention, the characteristic that the pin functions of the central processing unit STM32H743VI can be multiplexed is skillfully utilized to solve the problem of conflict caused by that a plurality of outputs are connected with the same input, and particularly, as shown in fig. 5 (b), as the pin 87 of the central processing unit STM32H743VI can be configured as the USART2_RX function like the pin 25, in the circuit structure, the pin 7R 1OUT is connected with the pin 25 of the central processing unit STM32H743VI, and the pin 8R 2OUT is connected with the pin 87 of the central processing unit STM32H743 VI. According to configuration parameters in the EEPROM, when the RS232 interface mode function is used, configuring the 25 pin of the central processing unit STM32H743VI as a USART2_RX function, and configuring the 87 pin of the central processing unit STM32H743VI as a GPIO input; when using the RS485 or RS422 interface mode functions, the 25 pin of the central processor STM32H743VI is configured as a GPIO input and the 87 pin of the central processor STM32H743VI is configured as a usart2_rx function. So far, through the functional configuration of the central processing unit, the centralized interfaces of RS232, RS485 and RS422 are realized;
As shown in fig. 6, the multi-functional interface chip provides the interface level of the RS232 interface mode through the pin configuration of the signal side connected with the central processing unit, and further needs to perform the interface mode configuration through the central processing unit, which specifically includes the following steps:
The EEPROM chip is read, and the current working mode of the centralized interface is determined to be an RS232 interface mode according to the configuration parameters of the RS232 interface mode;
configuring a central processor pin connected with an eleventh pin 11 of the multifunctional interface chip as a General Purpose Input Output (GPIO) function and outputting a low level;
configuring a central processor pin connected with a sixteenth pin 16 of the multifunctional interface chip as USARTn _TX function, namely USART logic output;
The central processor pin connected with the seventh pin 7 of the multifunctional interface chip is configured as USARTn _RX function, i.e. USART logic input.
As shown in fig. 6, the multifunctional interface chip provides an interface level of an RS485 interface mode through pin configuration of a signal side connected with a central processing unit, and the specific process is as follows:
the EEPROM chip is read, and the current centralized interface working mode is determined to be an RS485 mode according to the RS485 interface mode configuration parameters;
Configuring a central processor pin connected with an eleventh pin 11 of the multifunctional interface chip as a GPIO function, and outputting a high level;
configuring a central processor pin connected with a twelfth pin 12 of the multifunctional interface chip as a GPIO function and outputting a high level;
configuring a central processor pin connected with a sixteenth pin 16 of the multifunctional interface chip as USARTn _TX function, namely USART logic output;
Configuring a central processor pin connected with an eighth pin 8 of the multifunctional interface chip as USARTn _RX function, namely USART logic input;
The CPU pin connected with the fifteenth pin 15 of the multifunctional interface chip is configured to be USARTn _DE function, namely RS485 driving enable of USART.
As shown in fig. 6, the multifunctional interface chip provides an interface level of an RS422 interface mode through pin configuration of a signal side connected with a central processing unit, and the specific process is as follows:
The EEPROM chip is read, and the current centralized interface working mode is determined to be an RS422 mode according to the RS422 interface mode configuration parameters;
Configuring a central processor pin connected with an eleventh pin 11 of the multifunctional interface chip as a GPIO function, and outputting a high level;
Configuring a central processor pin connected with a twelfth pin 12 of the multifunctional interface chip as a GPIO function and outputting a low level;
configuring a central processor pin connected with a sixteenth pin 16 of the multifunctional interface chip as USARTn _TX function, namely USART logic output;
the central processor pin connected with the eighth pin 8 of the multifunctional interface chip is configured as USARTn _RX function, namely USART logic input.
The power supply is divided into two power domains by DC/DC (i.e., direct current to direct current) conversion, comprising: an interface power domain, or external power domain; a platform power domain, or internal power domain;
the interface power domain and the platform power domain are electrically isolated and not commonly grounded, and the adopted power supply mode is isolated power supply, so that external power supply noise is avoided being introduced or reduced.
Specifically, as shown in fig. 2 (a) and 2 (b), VIN/+5VCAN and its corresponding AGND (i.e., the triangle symbol in fig. 2 (a) and 2 (b)) are interface power domains, i.e., external power domains; +5v/+3.3v and its corresponding GND are platform power domains, i.e., internal power domains, which are not commonly grounded and electrically isolated in the circuit.
Wherein +5V is the external power source VIN converted by the DC/DC isolated power source U7, and +3.3V is +5V converted by the linear power source U8; +5VCAN is the conversion of VIN by the linear power supply U6.
As shown in fig. 3, +5vcan supplies power to interface side pin 8 of CAN-FD bus interface chip ISO1042DW (i.e., U4), and signal side pin 1 of U4 supplies power at +3.3v, which is the same as STM32H743 VI.
The CAN-FD bus communication interface circuit shown in figures 2 (a) and 2 (b) and figure 3 realizes power supply and signal double isolation, and cooperates with the filter design of the CAN-FD bus communication interface signal, thereby effectively improving the anti-interference capability of the embedded hardware platform.
The central processing unit STM32H743VI is connected with the Flash chip GD25S512MDFx through a QSPI interface; the central processing unit STM32H743VI is connected with the EEPROM chip BL24C512A-PA through the I2C interface, and the Flash chip and the EEPROM chip are both used for storing data.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.
Claims (6)
1. An embedded multi-interface data conversion device, comprising: the embedded hardware comprises an embedded hardware main board and an embedded hardware platform arranged on the embedded hardware main board;
The embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of power supply and signals;
The central processor is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for the connection of external equipment and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
The CPU is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
The central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the running process;
The central processing unit is also connected with a first connector which is convenient for the connection of external equipment and is used for providing a UART interface, an I2C interface and an SPI interface; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector;
The central processing unit is also connected with a second connector which is convenient for the connection of external equipment and is used for providing a UART interface, an SPI interface and an RMII interface; a UART interface, an SPI interface, an RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector;
the RS232-RS485-RS422 centralized communication interface comprises a multifunctional interface chip and a third connector, wherein pins with TTL levels on the signal side of the multifunctional interface chip are configured on the interface side to realize any one of the RS232, RS485 and RS422 interface levels;
The multifunctional interface chip provides any one interface level including an RS232 interface mode, an RS485 interface mode or an RS422 interface mode through pin configuration of a signal side connected with the central processing unit, and USARTn represents an nth group of interfaces when the central processing unit is provided with a plurality of USART interfaces; the specific configuration structure is as follows:
Function configuration structure of RS232 interface mode: the CPU configures an eleventh pin of the multifunctional interface chip to be at a low level through the GPIO pin, at this time, a logic output USARTn _TX pin and a logic input USARTn _RX pin of the CPU are respectively connected to a sixteenth pin and a seventh pin of the multifunctional interface chip correspondingly, and a fifth pin and a fourteenth pin of the multifunctional interface chip are respectively used as output and input of an RS232 interface level;
Function configuration structure of RS485 interface mode: the CPU configures an eleventh pin of the multifunctional interface chip to be high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip to be high level through the GPIO pin, and at the moment, a logic output USARTn _TX pin and a logic input USARTn _RX pin of the CPU are respectively connected to the sixteenth pin and the eighth pin of the multifunctional interface chip correspondingly; the USARTn _DE pin of the central processing unit is used as an input/output control signal of the RS485 interface to be connected to the fifteenth pin of the multifunctional interface chip, and the sixth pin and the fifth pin of the multifunctional interface chip are used as the positive and negative of the differential input/output of the RS485 interface level;
Functional configuration structure of RS422 interface mode: the CPU configures an eleventh pin of the multifunctional interface chip to be high level through a GPIO pin, configures a twelfth pin of the multifunctional interface chip to be low level through the GPIO pin, at the moment, a logic output USARTn _TX pin and a logic input USARTn _RX pin of the CPU are respectively connected into a sixteenth pin and an eighth pin of the multifunctional interface chip, a thirteenth pin and a fourteenth pin of the multifunctional interface chip are respectively a differential input positive and a differential input negative of an RS422 level, and a sixth pin and a fifth pin of the multifunctional interface chip are respectively used as a differential output positive and a differential output negative of the RS422 level;
The central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn _RX logic input function, and the two pins are respectively connected with a seventh pin and an eighth pin of the multifunctional interface chip.
2. The embedded multi-interface data conversion device according to claim 1, wherein the interface level of the RS232 interface mode provided by the multi-function interface chip through pin configuration of a signal side connected with the central processing unit needs to be configured through the central processing unit, and the specific process is as follows:
The EEPROM chip is read, and the current working mode of the centralized interface is determined to be an RS232 interface mode according to the configuration parameters of the RS232 interface mode;
configuring a central processor pin connected with an eleventh pin of the multifunctional interface chip as a GPIO function, and outputting a low level;
configuring a central processor pin connected with a sixteenth pin of the multifunctional interface chip as USARTn _TX function as logic output of the USART;
and configuring a central processor pin connected with a seventh pin of the multifunctional interface chip as USARTn _RX function as logic input of the USART.
3. The embedded multi-interface data conversion device according to claim 1, wherein the multi-function interface chip provides an interface level of an RS485 interface mode through pin configuration of a signal side connected with a central processing unit, and the specific process is as follows:
the EEPROM chip is read, and the current centralized interface working mode is determined to be an RS485 mode according to the RS485 interface mode configuration parameters;
configuring a central processor pin connected with an eleventh pin of the multifunctional interface chip as a GPIO function, and outputting a high level;
Configuring a central processor pin connected with a twelfth pin of the multifunctional interface chip as a GPIO function, and outputting a high level;
configuring a central processor pin connected with a sixteenth pin of the multifunctional interface chip as USARTn _TX function as logic output of the USART;
configuring a central processor pin connected with an eighth pin of the multifunctional interface chip as USARTn _RX function as logic input of USART;
And configuring a CPU pin connected with a fifteenth pin of the multifunctional interface chip as USARTn _DE function as RS485 driving enable of USART.
4. The embedded multi-interface data conversion device according to claim 1, wherein the multi-function interface chip provides an interface level of an RS422 interface mode through pin configuration of a signal side connected with a central processing unit, and the specific process is as follows:
The EEPROM chip is read, and the current centralized interface working mode is determined to be an RS422 mode according to the RS422 interface mode configuration parameters;
configuring a central processor pin connected with an eleventh pin of the multifunctional interface chip as a GPIO function, and outputting a high level;
Configuring a central processor pin connected with a twelfth pin of the multifunctional interface chip as a GPIO function, and outputting a low level;
configuring a central processor pin connected with a sixteenth pin of the multifunctional interface chip as USARTn _TX function as logic output of the USART;
The CPU pin connected with the eighth pin of the multifunctional interface chip is configured to be USARTn _RX function and used as the logic input of the USART.
5. The embedded multi-interface data conversion device of claim 1, wherein the power supply is divided into two power domains by DC/DC conversion, comprising: an interface power domain and a platform power domain;
the interface power domain and the platform power domain are electrically isolated and not grounded, and the adopted power supply mode is isolated power supply.
6. The embedded multi-interface data conversion device according to claim 1, wherein the central processor is connected with the Flash chip through a QSPI interface; the central processing unit is connected with the EEPROM chip through the I2C interface, and the Flash chip and the EEPROM chip are both used for storing data.
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