CN213934868U - Embedded multi-interface data conversion device - Google Patents
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Abstract
The utility model belongs to the technical field of many interfaces conversion equipment, specifically speaking relates to an embedded many interfaces data conversion equipment, include: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard; the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal; the central processor is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected; the central processor is also connected with an EEPROM chip with an I2C interface; the central processor is also connected with a Flash chip with a QSPI interface; the central processor is also connected with a first connector which is convenient for external equipment to connect; the central processor is also connected with a second connector which is convenient for external equipment to connect.
Description
Technical Field
The utility model belongs to the technical field of many interfaces conversion equipment, specifically speaking relates to an embedded many interfaces data conversion equipment.
Background
Currently, the manufacturing industry is in the key period of transformation and upgrading, a new generation of information technology is being closely integrated with a production and manufacturing technology, various internet of things are widely applied, and the realization of interconnection and intercommunication of production equipment becomes a development trend of industrial automation. Production equipment is used as nodes for information perception, tens of thousands of data nodes are distributed in the environment of the Internet of things, and each node updates data in working time. Because the data information is completely dispersed, the nodes support different data transmission protocols, and great difficulty is brought to data acquisition and data query.
In the fields of industrial automation, automotive electronics, sensor networks and the like, functional requirements on calculation and control, data acquisition, inter-device communication and the like are required, and various different types of application requirements generally need customized hardware design, for example, currently, commonly used communication interfaces of industrial control devices comprise RS-232, RS-485, RS-422, CAN and networks, and because various interface protocols are different and protocols of various communication structures are incompatible, operation and information interaction between heterogeneous networks are difficult to perform, so that the manufacturing cost is improved, and the iterative upgrade speed of hardware products is reduced.
SUMMERY OF THE UTILITY MODEL
For solving the above-mentioned defect that prior art exists, the utility model provides an embedded many interfaces data conversion equipment, the device includes: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal;
the central processing unit is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
the central processing unit is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
the central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the operation process;
the central processor is also connected with a first connector which is convenient for external equipment to connect and is used for providing a UART interface, an I2C interface and an SPI interface; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector;
the central processor is also connected with a second connector which is convenient for external equipment to connect and is used for providing a UART interface, an SPI interface and an RMII interface; and a UART interface, an SPI interface, an RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector.
As one improvement of the above technical solution, the RS232-RS485-RS422 centralized communication interface includes a multifunctional interface chip and a third connector, and a pin with a TTL level on a signal side of the multifunctional interface chip is configured on an interface side to implement any one of interface levels of RS232, RS485, and RS 422.
As an improvement of the above technical solution, the multifunctional interface chip provides any one of interface levels including an RS232 interface mode, an RS485 interface mode, or an RS422 interface mode through a pin configuration on a signal side connected to the central processing unit, and when the central processing unit has a plurality of USART interfaces, USARTn denotes an nth group of interfaces; the specific configuration structure is as follows:
function configuration structure of RS232 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a low level through the GPIO pin, at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected to a sixteenth pin and a seventh pin of the multifunctional interface chip, and a fifth pin and a fourteenth pin of the multifunctional interface chip are respectively used as output and input of an RS232 interface level;
function configuration structure of RS485 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip into a high level through the GPIO pin, and at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected into a sixteenth pin and an eighth pin of the multifunctional interface chip; the USARTn _ DE pin of the central processing unit is used as an input/output control signal of the RS485 interface and is connected into the fifteenth pin of the multifunctional interface chip, and the sixth pin and the fifth pin of the multifunctional interface chip are used as the positive and negative of differential input/output of the RS485 interface level;
function configuration structure of RS422 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip into a low level through the GPIO pin, at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively connected into a sixteenth pin and an eighth pin of the multifunctional interface chip, a thirteenth pin and a fourteenth pin of the multifunctional interface chip are respectively a differential input positive and a differential input negative of an RS422 level, and a sixth pin and a fifth pin of the multifunctional interface chip are respectively used as a differential output positive and a differential output negative of the RS422 level;
the central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn _ RX logic input function, and the two pins are respectively connected with a seventh pin and an eighth pin of the multifunctional interface chip.
As an improvement of the above technical solution, the power supply is divided into two power domains by DC/DC conversion, and includes: an interface power domain and a platform power domain;
the interface power domain and the platform power domain are electrically isolated from each other and are not grounded, and the adopted power supply mode is isolated power supply.
As one improvement of the technical scheme, the central processing unit is connected with the Flash chip through a QSPI interface; the central processing unit is connected with the EEPROM chip through an I2C interface, and the Flash chip and the EEPROM chip are used for storing data.
Compared with the prior art, the utility model beneficial effect be:
the utility model discloses a conversion equipment can support multiple interface extension and interface function conversion, through a centralized interface, can provide an arbitrary interface function of RS232, RS485, RS422, has optimized the interface, has reduced the interface complexity.
Drawings
Fig. 1 is a schematic structural diagram of an embedded multi-interface data conversion device according to the present invention;
FIG. 2(a) is a schematic diagram of CAN-FD bus interface chip interface power domain power supply;
FIG. 2(b) is a schematic diagram of the isolated conversion of the interface power domain to the platform power domain;
FIG. 3 is a schematic diagram of CAN-FD bus interface chip power/signal double isolation;
FIG. 4 is a schematic diagram of the electrical connections of the multi-function interface chip;
FIG. 5(a) shows an interference connection mode between the multi-function interface chip and the CPU;
FIG. 5(b) shows the mode of non-interference connection between the multi-function interface chip and the CPU.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
As shown in fig. 1, the utility model provides an embedded many interfaces data conversion equipment, the device includes: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal and is used for realizing remote anti-interference communication;
the central processing unit is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
the central processing unit is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
the central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the operation process;
the central processing unit is also connected with a first connector which is convenient for external equipment to connect and is used for providing a UART interface, an I2C interface, an SPI interface and a plurality of GPIOs; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector, so that interface function expansion is provided to the outside, and interface function expansion capability and interface conversion capability are improved;
the central processing unit is also connected with a second connector which is convenient for external equipment to connect and is used for providing a UART interface, an SPI interface, an RMII interface and a plurality of GPIOs; the UART interface, the SPI interface, the RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector, interface function expansion is provided for the outside, and interface function expansion capability and interface conversion capability are improved. As shown in fig. 1 and 2, the +5V and +3.3V and the corresponding GND are extended and led out to the first connector and the second connector for supplying power to the extension circuit.
The first connector and the second connector can realize function expansion and provide multi-interface type conversion, and different data can be collected conveniently. The UART interfaces, the SPI interfaces, the I2C interface and the RMII interface are used as expansion interfaces, so that the function expansion capability and the interface conversion capability of the embedded hardware platform are improved.
The central processing unit is an ARM Cortex-M7 architecture singlechip STM32H743VI with the main frequency of 480MHz, has a double-precision floating point arithmetic unit and DSP instructions, integrates 2MB Flash and 1MB RAM inside, and can meet various application requirements including data processing. The central processing unit is a control and processing core of the embedded hardware platform, and functions provided by the embedded hardware platform are all realized through an on-chip program of the single chip microcomputer.
The CAN-FD bus communication interface with double isolation of the power supply and the signals adopts an ISO1042DW chip, has 5000VRMS internal isolation which accords with UL 1577 standard and is as long as 1 minute, CAN prevent noise current on a data bus or other circuits from entering the local and interfering or damaging sensitive circuits, and CAN effectively improve the anti-interference capability of an embedded hardware platform by matching with the isolation power supply design of the embedded hardware platform.
The model of the Flash chip with the QSPI interface is GD25S512MDFx, a storage space of 512Mbits is provided, and the Flash chip can be used for recording state data and log data of an embedded hardware platform in the running process.
The model of the EEPROM chip with the I2C interface is BL24C512A-PA, and the EEPROM chip provides 512kbits of storage space, and can be used for storing parameter configuration data of an embedded hardware platform or recording relatively less data.
The RS232-RS485-RS422 centralized communication interface comprises: a multifunctional interface chip and a third connector; the type of the multifunctional interface chip is MAX3160EEAP, any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode is provided on the interface side through the configuration of a pin with TTL level on the signal side of the multifunctional interface chip, so that the interface integration level of a hardware platform is improved, and the circuit structure can be more compact;
the RS232-RS485-RS422 centralized communication interface also adopts the same third connector to match with the multifunctional interface chip to meet the external connection requirements of the RS232 interface, the RS485 interface and the RS422 interface.
The RS232-RS485-RS422 centralized communication interface is realized through a multifunctional interface chip MAX3160EEAP and a connector thereof, and a function configuration method is provided by a central processing unit, so that the interface design is optimized. The multifunctional interface chip MAX3160EEAP provides any one interface level including an RS232 interface mode, an RS485 interface mode or an RS422 interface mode through the pin configuration of the signal side connected with the central processing unit STM32H743 VI. As shown in fig. 4, the specific configuration structure is as follows:
function configuration structure of RS232 interface mode: the central processing unit STM32H743VI configures the eleventh pin of the multifunctional interface chip MAX3160EEAP to be a low level through a PD2_ RS _ MODE network signal (i.e., a PCB trace connected through a GPIO pin), at this time, the USART2_ TX signal and the USART2_ RX _232 signal respectively serve as a TTL level logic output pin and a logic input pin of the central processing unit STM32H743VI and are correspondingly connected to the sixteenth pin and the seventh pin of the multifunctional interface chip, respectively, and the fifth pin and the fourteenth pin of the multifunctional interface chip MAX3160EEAP respectively serve as an output and an input of an RS232 interface level;
function configuration structure of RS485 interface mode: the central processing unit STM32H743VI configures the eleventh pin of the multifunctional interface chip MAX3160EEAP to be high level through the PD2_ RS _ MODE network signal (i.e. the PCB trace connected through the GPIO pin), configures the twelfth pin of the multifunctional interface chip MAX3160EEAP to be high level through the HDPLX network signal, and at this time, the USART2_ TX signal and the USART2_ RX422 signal are respectively used as the sixteenth pin and the eighth pin of the central processing unit STM32H743VI, which are respectively accessed to the multifunctional interface chip, corresponding to the TTL level logic output pin and the logic input pin; the USART2_ DE pin is used as an input/output control signal of the RS485 interface and is connected to the fifteenth pin of the multifunctional interface chip, and the sixth pin and the fifth pin of the multifunctional interface chip MAX3160EEAP form differential signals of the RS485 interface level, namely positive and negative differential input/output;
function configuration structure of RS422 interface mode: the central processing unit STM32H743VI configures the eleventh pin of the multifunctional interface chip MAX3160EEAP to be high level through PD2_ RS _ MODE network signals (i.e. PCB traces connected through GPIO pins), and configures the twelfth pin of the multifunctional interface chip MAX3160EEAP to be low level through HDPLX network signals, at this time, USART2_ TX and USART2_ RX422 signals are respectively used as the TTL level logic output pin and the logic input pin of the central processing unit STM32H743VI to be respectively correspondingly connected to the sixteenth pin and the eighth pin of the multifunctional interface chip, the thirteenth pin and the fourteenth pin of the multifunctional interface chip MAX3160EEAP are respectively positive and negative differential input of RS422 level, and the sixth pin and the fifth pin of the multifunctional interface chip 31max 60EEAP are respectively used as positive and negative differential output of RS422 level.
In the RS232, RS485, and RS422 modes, the TTL level logic input of the multifunctional interface chip MAX3160EEAP is T1IN, corresponding to the sixteenth pin of the multifunctional interface chip MAX3160 EEAP. As shown in fig. 5, the sixteenth pin of the multifunction interface chip MAX3160EEAP is connected to the eighty-sixth pin of the central processing unit STM32H743VI, and the eighty-sixth pin of STM32H743VI is configured as the USART2_ TX function. However, in different modes, the TTL level logic output pins of the multifunctional interface chip MAX3160EEAP are different, when the multifunctional interface chip MAX3160EEAP is configured in the RS232 interface mode, the TTL level output is 7 pins R1OUT, and when the multifunctional interface chip MAX3160EEAP is configured in the RS485 or RS422 interface mode, the TTL level output is 8 pins R2 OUT.
If the multifunctional interface chip shown in fig. 5(a) is connected with the central processing unit circuit, the 7-pin R1OUT and the 8-pin R2OUT are both outputs, and the two outputs correspond to the same USART2_ RX signal input, which will affect the normal operation of the central processing unit STM32H743 VI. The utility model discloses in, the ingenious characteristics that have utilized central processing unit STM32H743VI pin function to multiplex have solved the problem of a plurality of data connection same inputs, particularly, as shown in fig. 5(b), because central processing unit STM32H743 VI's 87 feet also can be configured into USART2_ RX function like the 25 feet, consequently in circuit structure, with 7 feet R1OUT connection central processing unit STM32H743 VI's 25 feet, with 8 feet R2OUT connection central processing unit STM32H743 VI's 87 feet. According to configuration parameters in the EEPROM, when an RS232 interface mode function is used, a pin 25 of the central processing unit STM32H743VI is configured to be a USART2_ RX function, and a pin 87 of the central processing unit STM32H743VI is configured to be GPIO input; when the RS485 or RS422 interface mode function is used, the pin 25 of the central processor STM32H743VI is configured as GPIO input, and the pin 87 of the central processor STM32H743VI is configured as USART2_ RX function. So far, the centralized interfaces of RS232, RS485 and RS422 are realized through the functional configuration of the central processing unit.
The power supply is divided into two power domains by DC/DC conversion, which includes: an interface power domain, otherwise known as an external power domain; platform power domains, otherwise known as internal power domains;
the interface power domain and the platform power domain are electrically isolated and not grounded, and the adopted power supply mode is isolated power supply, so that external power supply noise is avoided or reduced.
Specifically, as shown in fig. 2(a) and 2(b), VIN/+5VCAN and its corresponding AGND (i.e., the triangular symbol in fig. 2(a) and 2 (b)) are interface power domains, i.e., external power domains; the +5V/+3.3V and its corresponding GND are platform power domains, i.e. internal power domains, which are not common in the circuit and are electrically isolated.
Wherein +5V of the internal power source is converted from the external power source VIN by the DC/DC isolation power source U7, and +3.3V is +5V converted from the linear power source U8; +5VCAN is VIN converted from the linear power supply U6.
As shown in fig. 3, the +5VCAN supplies power to the interface side pin of the CAN-FD bus interface chip ISO1042DW (i.e., U4), and the signal side pin of U4 supplies power at +3.3V, which is the same as STM32H743 VI.
The CAN-FD bus communication interface circuits shown in the figures 2(a) and 2(b) and 3 realize double isolation of power supply and signals, and are matched with the filtering design of CAN-FD bus communication interface signals, so that the anti-interference capability of the embedded hardware platform CAN be effectively improved.
The central processing unit STM32H743VI is connected with the Flash chip GD25S512MDFx through a QSPI interface; the central processing unit STM32H743VI is connected with an EEPROM chip BL24C512A-PA through an I2C interface, and the Flash chip and the EEPROM chip are used for storing data.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art will understand that modifications and equivalent substitutions can be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all of them shall fall within the scope of the claims of the present invention.
Claims (5)
1. An embedded multi-interface data conversion device, comprising: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal;
the central processing unit is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
the central processing unit is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
the central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the operation process;
the central processor is also connected with a first connector which is convenient for external equipment to connect and is used for providing a UART interface, an I2C interface and an SPI interface; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector;
the central processor is also connected with a second connector which is convenient for external equipment to connect and is used for providing a UART interface, an SPI interface and an RMII interface; and a UART interface, an SPI interface, an RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector.
2. The embedded multi-interface data conversion device according to claim 1, wherein the RS232-RS485-RS422 centralized communication interface comprises a multifunctional interface chip and a third connector, and the pin configuration with TTL level on the signal side of the multifunctional interface chip realizes any interface level of RS232, RS485 and RS422 on the interface side.
3. The embedded multi-interface data conversion device according to claim 2, wherein the multifunctional interface chip provides any one of interface levels including an RS232 interface mode, an RS485 interface mode or an RS422 interface mode through a pin configuration on a signal side connected to the central processor, and when the central processor has a plurality of USART interfaces, USARTn denotes an nth group of interfaces; the specific configuration structure is as follows:
function configuration structure of RS232 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a low level through the GPIO pin, at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected to a sixteenth pin and a seventh pin of the multifunctional interface chip, and a fifth pin and a fourteenth pin of the multifunctional interface chip are respectively used as output and input of an RS232 interface level;
function configuration structure of RS485 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip into a high level through the GPIO pin, and at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected into a sixteenth pin and an eighth pin of the multifunctional interface chip; the USARTn _ DE pin of the central processing unit is used as an input/output control signal of the RS485 interface and is connected into the fifteenth pin of the multifunctional interface chip, and the sixth pin and the fifth pin of the multifunctional interface chip are used as the positive and negative of differential input/output of the RS485 interface level;
function configuration structure of RS422 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip into a low level through the GPIO pin, at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively connected into a sixteenth pin and an eighth pin of the multifunctional interface chip, a thirteenth pin and a fourteenth pin of the multifunctional interface chip are respectively a differential input positive and a differential input negative of an RS422 level, and a sixth pin and a fifth pin of the multifunctional interface chip are respectively used as a differential output positive and a differential output negative of the RS422 level;
the central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn _ RX logic input function, and the two pins are respectively connected with a seventh pin and an eighth pin of the multifunctional interface chip.
4. The embedded multi-interface data conversion device according to claim 1, wherein the power supply is divided into two power domains by DC/DC conversion, comprising: an interface power domain and a platform power domain;
the interface power domain and the platform power domain are electrically isolated from each other and are not grounded, and the adopted power supply mode is isolated power supply.
5. The embedded multi-interface data conversion device according to claim 1, wherein the central processor is connected to the Flash chip through a QSPI interface; the central processing unit is connected with the EEPROM chip through an I2C interface, and the Flash chip and the EEPROM chip are used for storing data.
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| CN114564426A (en) * | 2020-11-27 | 2022-05-31 | 中国科学院声学研究所 | Embedded multi-interface data conversion device |
| CN114564426B (en) * | 2020-11-27 | 2024-05-14 | 中国科学院声学研究所 | Embedded multi-interface data conversion device |
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