CN201522684U

CN201522684U - Power consumption management circuit for embedded system

Info

Publication number: CN201522684U
Application number: CN2009201948491U
Authority: CN
Inventors: 唐振中; 邓廷; 许永平; 史谦; 石强; 马晖; 胡丽萍
Original assignee: ZHUHAI ZHONGHUI MICROELECTRONICS CO Ltd
Current assignee: ZHUHAI ZHONGHUI MICROELECTRONICS CO Ltd
Priority date: 2009-09-16
Filing date: 2009-09-16
Publication date: 2010-07-07
Anticipated expiration: 2019-09-16

Abstract

The utility model relates to a power consumption management circuit for an embedded system, which comprises a power consumption management register, an interrupt interface, at least two clock generating circuits and at least two clock control circuits. The power consumption management register provides at least two modes of selection signals; the interrupt interface is used for switching interrupt wake-up signals in; and the clock control circuits respectively control work, opening and closing or being waken up of the at least two clock generating circuits according to the mode selection signals and the interrupt wake-up signals. The power consumption management circuit is capable of controlling at least two clocks to work simultaneously, one clock to work, or neither of the two clocks to work, namely the clocks work in full power, half power and no power states through a mode switching control system to realize limiting power consumption, simultaneously balancing consideration of requirements for data processing of a system, thereby the system can realize high-level performance under low-level power consumption. The power consumption management circuit has the advantages of complete function, convenient operation, excellent generality and low cost.

Description

The power managed circuit of embedded system

Technical field

The utility model relates to the electronic circuit technology field, is specifically related to the power managed circuit in the embedded system.

Background technology

At present, embedded system has been widely used in consumer electronics, mobile computing device, multimedia, industrial automation instrument, has reached on portable electronic blood glucose meter, portable bedside monitor, the cardioscribe medical instrument equipment such as (ECG).Yet because the restriction of system power dissipation, the continuous working period operating cost of embedded system, reliability etc. are all had a strong impact on, and promptly power consumption has become one of main restricting factor of Embedded System Design.

Therefore, how research improves the power supply utilization rate effectively and just becomes extremely important.From the angle of hardware design, mainly study the technology that reduces system power dissipation at present by the following method: 1. use the assembly integrated technology to reduce electric capacity; 2. multiple clock frequency is provided; 3. reduce operating voltage.Wherein, it is more with the technological means restrictive condition in actual applications that reduces operating voltage to use the assembly integrated technology to reduce electric capacity, unfavorable applying; Though and provide the application of technological means in individual PC of multiple clock frequency more, its cost is higher, is unsuitable for gently little, portable electronic product.

The utility model content

The purpose of this utility model provides a kind of power managed circuit of embedded system, can work under full merit, half merit and idle state by the control system clock.

Above-mentioned purpose is realized by following technical scheme:

A kind of power managed circuit of embedded system is characterized in that, comprising: the power managed register provides the selection signal of at least two kinds of patterns; Interrupt interface is used for inserting the interruption wake-up signal; At least two clock generating circuits; At least two clock control circuits are according to mode select signal and interrupt work that wake-up signal controls described at least two clock generating circuits respectively, close or be waken up.

Described power managed register has to supply a pattern to be selected first of signal to deposit position and second to deposit the position; Described at least two clock generating circuits comprise first clock generating circuit and second clock generation circuit, and described at least two clock control circuits comprise first clock control circuit and second clock control circuit; Described interrupt interface comprises first interrupt interface and second interrupt interface.

Described first clock control circuit by the first phase inverter INV0, the second phase inverter INV1, first and the door AND0 and second or the door OR1 constitute; Described first deposit a signal and second deposit a signal respectively by after the first phase inverter INV0 and the second phase inverter INV1 as first with the input of door AND0, first signal that inserts with the output of door AND0 and by second interrupt interface as second or the input of door OR1, second or a door OR1 export first clock control signal.

Described first clock generating circuit by system clock, the 3rd phase inverter INV2, the first trigger DFF0 and second and a door AND1 constitute; System clock reaches the input of described first clock control signal as the first trigger DFF0 behind the 3rd phase inverter INV2, the output of the first trigger DFF0 and system clock as second with the input of door AND1, second with the output of door AND1 as the output of first clock.

Described second clock control circuit by the second phase inverter INV1, first or the door OR0 and the 3rd or the door OR2 constitute; Described second deposit a signal by behind the second phase inverter INV1 as the 3rd or the input of door OR2, the signal that inserts by first interrupt interface and second interrupt interface by first or door OR0 after as the 3rd or another input of door OR2, the 3rd or door OR2 output second clock control signal.

Described second clock generation circuit is made of with door AND2 system clock, the 3rd phase inverter INV2, the second trigger DFF1 and the 3rd; System clock reaches the input of described second clock control signal as the second trigger DFF1 behind the 3rd phase inverter INV2, the output of the second trigger DFF1 and system clock as the 3rd with the input of door AND2, the 3rd with the output of door AND2 as the output of second clock.

The internal interrupt source of the described first interrupt interface join dependency clock, can be in timer, serial ports, the house dog at least a.

Described second interrupt interface connects the exterior interrupt that does not rely on clock.

The utility model can control that at least two clocks are worked simultaneously, one of them work or two do not work, promptly can under full merit, half merit and idle state, work by the mode switching control system clock, when being implemented in limit dissipation power, the requirement of balanced taking into account system deal with data, thus the realization system realizes high levels of performance with low-level power consumption.The utility model integral body has perfect in shape and function, control conveniently, versatility reaches the low characteristics of cost well.

Description of drawings

Fig. 1 is a module structure drafting of the present utility model;

Fig. 2 is the synoptic diagram of the power managed register that adopts in the utility model;

Fig. 3 is the circuit diagram of clock control circuit and clock generating circuit in the utility model;

Fig. 4 is a formation block diagram of having used portable cardiac supervisory system of the present utility model;

Fig. 5 and Fig. 6 are respectively the Clock management of circuit shown in Figure 3 and the sequential chart that clock wakes up;

Fig. 7 is the clock control circuit of the another kind of embodiment of the utility model and the circuit diagram of clock generating circuit.

Embodiment

As shown in Figure 1, the power managed circuit of the embedded system that provides of present embodiment comprises: first clock generating circuit, second clock generation circuit, first clock control circuit, second clock control circuit, power managed register and interrupt interface.Describe the composition and the annexation of each several part in detail below in conjunction with Fig. 2, Fig. 3.

As shown in Figure 2, in the present embodiment, two kinds of mode of operations that the idle of configuration power managed register deposits the position and stop deposits position (be initially set to 0, effective value is 1) control power managed: idle pattern and stop pattern.Wherein, peripheral hardware clock (being second clock) work but interior nuclear clock (i.e. first clock) are closed under the idle pattern; Peripheral hardware clock and kernel clock signal all are closed under the stop pattern.

In conjunction with shown in Figure 3, the idle of power managed register deposit signal that position and stop deposit the position respectively by after the first phase inverter INV0 and the second phase inverter INV1 as first with the input of door AND0, first exports a stop mode control signal (low level is effective) with door AND0; The signal that stop deposits the position obtains idle mode control signal (low level is effective) after by the second phase inverter INV1.Stop mode control signal and external interrupt wakeup signal (not relying on the external interrupt of clock) as user oriented switch acquisition circuit as second or the door OR1 input, second or the door OR1 export first clock control signal; The idle mode control signal as the 3rd or the door OR2 an input, the internal interrupt wake-up signal (relies on clock, as timer, serial ports, house dog etc.) and external interrupt signal by first or door OR0 after as the 3rd or another input of door OR2, the 3rd or door OR2 output second clock control signal.Described first clock control signal and second clock control signal offer the first trigger DFF0 and the second trigger DFF1 respectively, system clock inputs to the first trigger DFF0 and the second trigger DFF1 behind the 3rd phase inverter INV2, the output of the first trigger DFF0 and system clock as second with the door AND1 input, the output of the second trigger DFF1 and system clock as the 3rd with the input of door AND2, second with the output of door AND1 and the 3rd with the output of door AND2 as the output of first clock and second clock.

When foregoing circuit provides stop and two kinds of mode of operations of idle, provide outside and inner two kinds to interrupt arousal function, be internal interrupt wake-up signal and external interrupt wakeup signal by first or door OR0 after obtain the wake-up signal of peripheral hardware clock, the external interrupt wakeup signal still in the wake-up signal of nuclear clock.Whether (high level is effective) mode control signal effectively all can wake clock up when the clock wake-up signal is effective.In the foregoing circuit, first clock control signal obtains first clock (interior nuclear clock) by the synchronous door control clock circuit of using system clock negative edge, the second clock control signal obtains second clock (peripheral hardware clock) by the synchronous door control clock circuit of using system clock negative edge, and the synchronous door control clock circuit of negative edge can filter the interference that combinational logic brings on the gated clock.

The sequential control that the Clock management of circuit shown in Figure 3 and clock wake up is please respectively referring to Fig. 5 and Fig. 6.

Fig. 4 is a formation block diagram of having used portable cardiac supervisory system of the present utility model.Simply be described below: electrocardiosignal is amplified into the digitalized data that digital to analog converter ADC obtains electrocardiosignal by low noise amplifier LNA, and data are by interrupting being connected power management unit PMU and MCU with serial line interface (as spi etc.); The sample frequency of digital to analog converter is 1khz, and the processing frequency of MCU (perhaps DSP) is more than the 1M, and frequency between the two differs more than 1000 times, causes MCU owing to the data of waiting for ADC are in idle condition, for power managed provides the space.

Because MCU and the frequency distance of ADC more than 1000 times, after MCU handled electrocardiosignal, by command M OV PCON, #01H made the idle position of power managed register (as shown in Figure 2) be configured to 1.The idle position is 1, and by power management unit, nuclear clock stops in making, peripheral hardware clock operate as normal, and the data that MCU finishes dealing with are real-time transmitted to wireless or display module under the peripheral hardware clock, and MCU is in the idle mode of operation; The look-at-me that sign ADC finishes conversion is connected on the external interrupt pin of power management unit, after ADC finishes conversion next time, the look-at-me that ADC produces is waken interior nuclear clock up by power management unit, make MCU withdraw from the idle pattern, MCU detects after this look-at-me simultaneously, by command M OV PCON, #00H makes the power managed register be in normal mode of operation, ADC finishes by serial ports after the transmission of data, and MCU carries out normal data processing under interior nuclear clock.

The practical circuit that the foregoing description provides only is fully open unrestricted the utility model.Be understandable that, based on the utility model thought, provide by the power managed register and more to deposit the position, distribute more interrupt interface, and cooperate more clock control circuit and clock generating circuit, can realize more multimodal power consumption control function.For example, as shown in Figure 7, described power managed register can also have to supply a pattern selects the 3rd of signal to deposit the position; Described interrupt interface comprises the 3rd interrupt interface; Described at least two clock control circuits can also comprise the 3rd clock control circuit; Described at least two clock generating circuits also comprise the 3rd clock generating circuit.Described the 3rd clock control circuit by the 3rd phase inverter INV2, the 4th or the door OR3 constitute, the described the 3rd deposit a signal by after the 3rd phase inverter INV2 as the 4th or the input of door OR3, the signal that the 3rd interrupt interface inserts as the 4th or another input of door OR3, the 4th or a door OR3 export the 3rd clock control signal.Described the 3rd clock generating circuit is made of with door AND3 system clock, the 3rd phase inverter INV2, the 3rd trigger DFF2 and the 4th; System clock reaches the input of described the 3rd clock control signal as the 3rd trigger DFF2 behind the 3rd phase inverter INV2, the output of the 3rd trigger DFF2 and system clock as the 4th with the input of door AND3, the 4th with the output of door AND3 as the output of the 3rd clock.In addition, the stop pattern described in the foregoing description, idle pattern, interior nuclear clock, peripheral hardware clock etc. only are the specific address under the application-specific of present embodiment, should not be used to limit the utility model.

Claims

1. the power managed circuit of an embedded system is characterized in that, comprising:

The power managed register provides the selection signal of at least two kinds of patterns;

Interrupt interface is used for inserting the interruption wake-up signal;

At least two clock generating circuits;

At least two clock control circuits are according to mode select signal and interrupt work that wake-up signal controls described at least two clock generating circuits respectively, close or be waken up.

2. the power managed circuit of embedded system according to claim 1 is characterized in that, described power managed register has to supply a pattern to be selected first of signal to deposit position and second to deposit the position; Described at least two clock generating circuits comprise first clock generating circuit and second clock generation circuit, and described at least two clock control circuits comprise first clock control circuit and second clock control circuit; Described interrupt interface comprises first interrupt interface and second interrupt interface.

3. the power managed circuit of embedded system according to claim 2 is characterized in that, described first clock control circuit by first phase inverter (INV0), second phase inverter (INV1), first and door (AND0) and second or door (OR1) constitute; Described first deposit a signal and second deposit a signal respectively by first phase inverter (INV0) and second phase inverter (INV1) afterwards as first with the input of (AND0), first signal that inserts with the output of door (AND0) and by second interrupt interface is as second or the input of door (OR1), second or door (OR1) output first clock control signal.

4. the power managed circuit of embedded system according to claim 3 is characterized in that, described first clock generating circuit by system clock, the 3rd phase inverter (INV2), first trigger (DFF0) and second and door (AND1) constitute; System clock behind the 3rd phase inverter (INV2) and described first clock control signal as the input of first trigger (DFF0), the output of first trigger (DFF0) and system clock as second with the input of door (AND1), second with the output of door (AND1) as the output of first clock.

5. according to the power managed circuit of claim 2,3 or 4 any described embedded systems, it is characterized in that, described second clock control circuit by second phase inverter (INV1), first or door (OR0) and the 3rd or door (OR2) constitute; Described second deposit a signal by second phase inverter (INV1) back as the 3rd or an input of door (OR2), the signal that inserts by first interrupt interface and second interrupt interface by first or door (OR0) afterwards as the 3rd or another input of door (OR2), the 3rd or door (OR2) output second clock control signal.

6. the power managed circuit of embedded system according to claim 5 is characterized in that, described second clock generation circuit is made of with door (AND2) system clock, the 3rd phase inverter (INV2), second trigger (DFF1) and the 3rd; System clock behind the 3rd phase inverter (INV2) and described second clock control signal as the input of second trigger (DFF1), the output of second trigger (DFF1) and system clock as the 3rd with the input of door (AND2), the 3rd with the output of door (AND2) as the output of second clock.

7. the power managed circuit of embedded system according to claim 2 is characterized in that, the internal interrupt source of the described first interrupt interface join dependency clock.

8. the power managed circuit of embedded system according to claim 7 is characterized in that, described internal interrupt source comprises at least a in timer, serial ports, the house dog.

9. according to the power managed circuit of claim 2 or 7 described embedded systems, it is characterized in that described second interrupt interface connects the exterior interrupt that does not rely on clock.

10. the power managed circuit of embedded system according to claim 2 is characterized in that, described power managed register also has to supply a pattern selects the 3rd of signal to deposit the position; Described interrupt interface also comprises the 3rd interrupt interface; Described at least two clock generating circuits also comprise the 3rd clock generating circuit; Described at least two clock control circuits comprise the 3rd clock control circuit.