CN114564426A - Embedded multi-interface data conversion device - Google Patents
Embedded multi-interface data conversion device Download PDFInfo
- Publication number
- CN114564426A CN114564426A CN202011361743.3A CN202011361743A CN114564426A CN 114564426 A CN114564426 A CN 114564426A CN 202011361743 A CN202011361743 A CN 202011361743A CN 114564426 A CN114564426 A CN 114564426A
- Authority
- CN
- China
- Prior art keywords
- interface
- pin
- processing unit
- central processing
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 26
- 238000012545 processing Methods 0.000 claims abstract description 116
- 238000004891 communication Methods 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 13
- 238000012905 input function Methods 0.000 claims description 2
- 230000006870 function Effects 0.000 description 48
- 230000006872 improvement Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention belongs to the technical field of multi-interface conversion equipment, and particularly relates to an embedded multi-interface data conversion device, which comprises: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard; the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal; the central processor is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected; the central processor is also connected with an EEPROM chip with an I2C interface; the central processing unit is also connected with a Flash chip with a QSPI interface; the central processor is also connected with a first connector which is convenient for external equipment to connect; the central processor is also connected with a second connector which is convenient for external equipment to connect.
Description
Technical Field
The invention belongs to the technical field of multi-interface conversion equipment, and particularly relates to an embedded multi-interface data conversion device.
Background
Currently, the manufacturing industry is in the key period of transformation and upgrading, a new generation of information technology is being closely integrated with a production and manufacturing technology, various internet of things are widely applied, and the realization of interconnection and intercommunication of production equipment becomes a development trend of industrial automation. Production equipment is used as nodes for information perception, tens of thousands of data nodes are distributed in the environment of the Internet of things, and each node updates data in working time. Because the data information is completely dispersed, the nodes support different data transmission protocols, and great difficulty is brought to data acquisition and data query.
In the fields of industrial automation, automotive electronics, sensor networks and the like, functional requirements on calculation and control, data acquisition, inter-device communication and the like are required, and various different types of application requirements generally need customized hardware design, for example, currently, commonly used communication interfaces of industrial control devices comprise RS-232, RS-485, RS-422, CAN and networks, and because various interface protocols are different and protocols of various communication structures are incompatible, operation and information interaction between heterogeneous networks are difficult to perform, so that the manufacturing cost is improved, and the iterative upgrade speed of hardware products is reduced.
Disclosure of Invention
In order to solve the above-mentioned defects existing in the prior art, the present invention provides an embedded multi-interface data conversion device, which comprises: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal;
the central processing unit is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
the central processing unit is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
the central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the operation process;
the central processor is also connected with a first connector which is convenient for external equipment to connect and is used for providing a UART interface, an I2C interface and an SPI interface; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector;
the central processor is also connected with a second connector which is convenient for external equipment to connect and is used for providing a UART interface, an SPI interface and an RMII interface; and a UART interface, an SPI interface, an RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector.
As one improvement of the above technical solution, the RS232-RS485-RS422 centralized communication interface includes a multifunctional interface chip and a third connector, and a pin with a TTL level on a signal side of the multifunctional interface chip is configured on an interface side to implement any one of interface levels of RS232, RS485, and RS 422.
As an improvement of the above technical solution, the multifunctional interface chip provides any one of interface levels including an RS232 interface mode, an RS485 interface mode, or an RS422 interface mode through a pin configuration on a signal side connected to the central processing unit, and when the central processing unit has a plurality of USART interfaces, USARTn denotes an nth group of interfaces; the specific configuration structure is as follows:
function configuration structure of RS232 interface mode: the central processing unit configures the eleventh pin of the multifunctional interface chip into low level through the GPIO pin, at this time, the logic output USARTn _ TX pin and the logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected to the sixteenth pin and the seventh pin of the multifunctional interface chip, and the fifth pin and the fourteenth pin of the multifunctional interface chip are respectively used as the output and the input of RS232 interface level;
function configuration structure of RS485 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip into a high level through the GPIO pin, and at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected into a sixteenth pin and an eighth pin of the multifunctional interface chip; the USARTn _ DE pin of the central processing unit is used as an input/output control signal of the RS485 interface and is connected into the fifteenth pin of the multifunctional interface chip, and the sixth pin and the fifth pin of the multifunctional interface chip are used as the positive and negative of differential input/output of the RS485 interface level;
function configuration structure of RS422 interface mode: the central processing unit configures an eleventh pin of the multifunctional interface chip into a high level through the GPIO pin, configures a twelfth pin of the multifunctional interface chip into a low level through the GPIO pin, at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively connected into a sixteenth pin and an eighth pin of the multifunctional interface chip, a thirteenth pin and a fourteenth pin of the multifunctional interface chip are respectively a differential input positive and a differential input negative of an RS422 level, and a sixth pin and a fifth pin of the multifunctional interface chip are respectively used as a differential output positive and a differential output negative of the RS422 level;
the central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn _ RX logic input function, and the two pins are respectively connected with a seventh pin and an eighth pin of the multifunctional interface chip.
As an improvement of the above technical solution, the multifunctional interface chip provides an interface level of an RS232 interface mode through a pin configuration on a signal side connected to the central processing unit, and needs to perform interface mode configuration through the central processing unit, and the specific process includes:
reading the EEPROM chip, and determining the working mode of the current centralized interface as the RS232 interface mode according to the configuration parameters of the RS232 interface mode;
configuring a central processing unit pin connected with an eleventh pin of the multifunctional interface chip to have a GPIO function and output a low level;
configuring a central processing unit pin connected with a sixteenth pin of the multifunctional interface chip to be a USARTn _ TX function as logic output of the USART;
and configuring a central processing unit pin connected with a seventh pin of the multifunctional interface chip as a USARTn-RX function as a logic input of the USART.
As an improvement of the above technical solution, the multifunctional interface chip provides an interface level of an RS485 interface mode through a pin configuration on a signal side connected to the central processing unit, and the specific process is as follows:
reading an EEPROM chip, and determining that the current centralized interface working mode is the RS485 mode according to the RS485 interface mode configuration parameters;
configuring a central processing unit pin connected with an eleventh pin of the multifunctional interface chip to have a GPIO function and output a high level;
configuring a central processing unit pin connected with a twelfth pin of the multifunctional interface chip to have a GPIO function and output a high level;
configuring a central processing unit pin connected with a sixteenth pin of the multifunctional interface chip to be a USARTn _ TX function as logic output of the USART;
configuring a central processing unit pin connected with an eighth pin of the multifunctional interface chip as a USARTn _ RX function as a logic input of the USART;
and a central processing unit pin connected with the fifteenth pin of the multifunctional interface chip is configured to be a USARTn _ DE function and used as RS485 drive enable of the USART.
As an improvement of the above technical solution, the multifunctional interface chip provides an interface level of an RS422 interface mode through a pin configuration on a signal side connected to the central processing unit, and the specific process is as follows:
reading the EEPROM chip, and determining the current centralized interface working mode as the RS422 mode according to the RS422 interface mode configuration parameters;
configuring a central processing unit pin connected with an eleventh pin of the multifunctional interface chip to have a GPIO function and output a high level;
configuring a central processing unit pin connected with a twelfth pin of the multifunctional interface chip to have a GPIO function and output a low level;
configuring a central processing unit pin connected with a sixteenth pin of the multifunctional interface chip to be a USARTn _ TX function as logic output of the USART;
and configuring a central processing unit pin connected with the eighth pin of the multifunctional interface chip as a USARTn-RX function as a logic input of the USART.
As an improvement of the above technical solution, the power supply is divided into two power domains by DC/DC conversion, and includes: an interface power domain and a platform power domain;
the interface power domain and the platform power domain are electrically isolated from each other and are not grounded, and the adopted power supply mode is isolated power supply.
As one improvement of the technical scheme, the central processing unit is connected with the Flash chip through a QSPI interface; the central processing unit is connected with the EEPROM chip through an I2C interface, and the Flash chip and the EEPROM chip are used for storing data.
Compared with the prior art, the invention has the beneficial effects that:
the conversion device can support various interface extensions and interface function conversion, can provide any interface function of RS232, RS485 and RS422 through a centralized interface, optimizes the interface and reduces the interface complexity.
Drawings
FIG. 1 is a schematic structural diagram of an embedded multi-interface data conversion device according to the present invention;
FIG. 2(a) is a schematic diagram of CAN-FD bus interface chip interface power domain power supply;
FIG. 2(b) is a schematic diagram of the isolated conversion of the interface power domain to the platform power domain;
FIG. 3 is a schematic diagram of CAN-FD bus interface chip power/signal double isolation;
FIG. 4 is a schematic diagram of the electrical connections of the multi-function interface chip;
FIG. 5(a) shows an interference connection mode between the multi-function interface chip and the CPU;
FIG. 5(b) shows the mode of non-interference connection between the multi-function interface chip and the CPU.
FIG. 6 is a flow chart of a method for configuring the centralized communication interface of RS232-RS485-RS422 and the central processing unit.
Reference numerals:
1. a first pin 2 and a second pin
3. Third pin 4 and fourth pin
5. Fifth pin 6 and sixth pin
7. Seventh pin 8, eighth pin
9. Ninth pin 10 and tenth pin
11. Eleventh pin 12 and twelfth pin
13. Thirteenth pin 14, fourteenth pin
15. Fifteenth pin 16, sixteenth pin
17. Seventeenth pin 18 and eighteenth pin
19. Nineteenth pin 20 and twentieth pin
25. Twenty-fifth pin 86 and eighty-sixth pin
87. Eighty-seventh base pin
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides an embedded multi-interface data conversion apparatus, which includes: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal and is used for realizing remote anti-interference communication;
the central processing unit is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
the central processing unit is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
the central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the operation process;
the central processing unit is also connected with a first connector which is convenient for external equipment to connect and is used for providing a UART interface, an I2C interface, an SPI interface and a plurality of GPIOs; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector, so that interface function expansion is provided to the outside, and interface function expansion capability and interface conversion capability are improved;
the central processing unit is also connected with a second connector which is convenient for external equipment to connect and is used for providing a UART interface, an SPI interface, an RMII interface and a plurality of GPIOs; the UART interface, the SPI interface, the RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector, interface function expansion is provided for the outside, and interface function expansion capability and interface conversion capability are improved. As shown in fig. 1 and 2, the +5V and +3.3V and the corresponding GND are extended and led out to the first connector and the second connector for supplying power to the extension circuit.
The first connector and the second connector can realize function expansion and provide multi-interface type conversion, and different data can be collected conveniently. The UART interfaces, the SPI interfaces, the I2C interface and the RMII interface are used as expansion interfaces, so that the function expansion capability and the interface conversion capability of the embedded hardware platform are improved.
The central processing unit is an ARM Cortex-M7 architecture singlechip STM32H743VI with the main frequency of 480MHz, has a double-precision floating point arithmetic unit and DSP instructions, integrates 2MB Flash and 1MB RAM inside, and can meet various application requirements including data processing. The central processing unit is a control and processing core of the embedded hardware platform, and functions provided by the embedded hardware platform are all realized through an on-chip program of the single chip microcomputer.
The CAN-FD bus communication interface with double isolation of the power supply and the signals adopts an ISO1042DW chip, has 5000VRMS internal isolation which accords with UL 1577 standard and is as long as 1 minute, CAN prevent noise current on a data bus or other circuits from entering the local and interfering or damaging sensitive circuits, and CAN effectively improve the anti-interference capability of an embedded hardware platform by matching with the isolation power supply design of the embedded hardware platform.
The model of the Flash chip with the QSPI interface is GD25S512MDFx, a storage space of 512Mbits is provided, and the Flash chip can be used for recording state data and log data of an embedded hardware platform in the running process.
The model of the EEPROM chip with the I2C interface is BL24C512A-PA, and the EEPROM chip provides 512kbits of storage space, and can be used for storing parameter configuration data of an embedded hardware platform or recording relatively less data.
The RS232-RS485-RS422 centralized communication interface comprises: a multifunctional interface chip and a third connector; the type of the multifunctional interface chip is MAX3160EEAP, any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode is provided on the interface side through the configuration of a pin with TTL level on the signal side of the multifunctional interface chip, so that the interface integration level of a hardware platform is improved, and the circuit structure can be more compact;
the RS232-RS485-RS422 centralized communication interface also adopts the same third connector to match with the multifunctional interface chip to meet the external connection requirements of the RS232 interface, the RS485 interface and the RS422 interface.
The RS232-RS485-RS422 centralized communication interface is realized through the multifunctional interface chip MAX3160EEAP and the connector thereof, the function configuration method is provided by the central processing unit, the interface design is optimized, and the multifunctional interface chip MAX3160EEAP provides any one interface level including an RS232 interface mode, an RS485 interface mode or an RS422 interface mode through the pin configuration of the signal side connected with the central processing unit STM32H743 VI. As shown in fig. 4, the specific configuration structure is as follows:
function configuration structure of RS232 interface mode: the central processing unit STM32H743VI configures the eleventh pin 11 of the multifunctional interface chip MAX3160EEAP to be a low level through a PD2_ RS _ MODE network signal (i.e., a PCB trace connected through a GPIO pin), at this time, the USART2_ TX signal and the USART2_ RX _232 signal respectively serve as TTL level logic output and logic input of the central processing unit STM32H743VI, and respectively and correspondingly access the sixteenth pin 16 and the seventh pin 7 of the multifunctional interface chip, and the fifth pin 5 and the fourteenth pin 14 of the multifunctional interface chip MAX3160EEAP respectively serve as output and input of an RS232 interface level;
function configuration structure of RS485 interface mode: the central processing unit STM32H743VI configures the eleventh pin 11 of the multifunctional interface chip MAX3160EEAP to be high level through the PD2_ RS _ MODE network signal (i.e. the PCB trace connected through the GPIO pin), configures the twelfth pin 12 of the multifunctional interface chip MAX3160EEAP to be high level through the HDPLX network signal, at this time, the USART2_ TX signal and the USART2_ RX422 signal are respectively used as TTL level logic output and logic input of the central processing unit STM32H743VI, and correspondingly accesses the sixteenth pin 16 and the eighth pin 8 of the multifunctional interface chip respectively; the USART2_ DE signal is used as an input/output control signal of the RS485 interface and is connected to the fifteenth pin 15 of the multifunctional interface chip, and the sixth pin 6 and the fifth pin 5 of the multifunctional interface chip MAX3160EEAP form differential signals of RS485 interface level, namely positive and negative differential input/output;
function configuration structure of RS422 interface mode: the central processing unit STM32H743VI configures the eleventh pin 11 of the multifunctional interface chip MAX3160EEAP to be high level through PD2_ RS _ MODE network signals (i.e. PCB traces connected through GPIO pins), and configures the twelfth pin 12 of the multifunctional interface chip MAX3160EEAP to be low level through HDPLX network signals, at this time, USART2_ TX and USART2_ RX422 signals respectively serve as TTL level logic output and logic input of the central processing unit STM32H743VI, respectively access the sixteenth pin 16 and the eighth pin 8 of the multifunctional interface chip, respectively corresponding the thirteenth pin 13 and the fourteenth pin 14 of the multifunctional interface chip 3160EEAP are respectively positive and negative differential input of RS422 level, and the sixth pin 6 and the fifth pin 5 of the multifunctional interface chip MAX3160EEAP serve respectively as positive and negative differential output of RS422 level.
In the RS232, RS485, and RS422 modes, the TTL level logic input of the multifunctional interface chip MAX3160EEAP is T1IN, and corresponds to the sixteenth pin 16 of the multifunctional interface chip MAX3160 EEAP. Multifunctional interface chip as shown in fig. 5, the sixteenth pin 16 of the multifunctional interface chip MAX3160EEAP is connected with the eighty-sixth pin 86 of the central processing unit STM32H743VI, and the eighty-sixth pin 86 of STM32H743VI is configured as USART2_ TX function. However, in different modes, the TTL level logic output pins of the multifunctional interface chip MAX3160EEAP are different, when the multifunctional interface chip MAX3160EEAP is configured in the RS232 interface mode, the TTL level output is 7 pins R1OUT, and when the multifunctional interface chip MAX3160EEAP is configured in the RS485 or RS422 interface mode, the TTL level output is 8 pins R2 OUT.
If the multifunctional interface chip shown in fig. 5(a) is connected with the central processing unit circuit, the 7-pin R1OUT and the 8-pin R2OUT are both outputs, and the two outputs correspond to the same USART2_ RX signal input, which will affect the normal operation of the central processing unit STM32H743 VI. In the invention, the problem of conflict caused by the fact that a plurality of outputs are connected with the same input is solved by skillfully utilizing the characteristic that the function of the pin of the central processing unit STM32H743VI can be reused, specifically, as shown in fig. 5(b), as the pin 87 of the central processing unit STM32H743VI can also be configured into a USART2_ RX function like the pin 25, in the circuit structure, the pin 7R 1OUT is connected with the pin 25 of the central processing unit STM32H743VI, and the pin 8R 2OUT is connected with the pin 87 of the central processing unit STM32H743 VI. According to configuration parameters in the EEPROM, when an RS232 interface mode function is used, a pin 25 of the central processing unit STM32H743VI is configured to be a USART2_ RX function, and a pin 87 of the central processing unit STM32H743VI is configured to be GPIO input; when the RS485 or RS422 interface mode function is used, the pin 25 of the central processor STM32H743VI is configured as a GPIO input, and the pin 87 of the central processor STM32H743VI is configured as a USART2_ RX function. So far, the centralized interfaces of RS232, RS485 and RS422 are realized through the functional configuration of the central processing unit;
as shown in fig. 6, the multifunctional interface chip provides an interface level of an RS232 interface mode through a pin configuration on a signal side connected to the central processing unit, and also needs to perform interface mode configuration through the central processing unit, and the specific process includes:
reading the EEPROM chip, and determining the working mode of the current centralized interface as the RS232 interface mode according to the configuration parameters of the RS232 interface mode;
configuring a central processing unit pin connected with an eleventh pin 11 of the multifunctional interface chip to have a general purpose input/output (GPIO) function and output a low level;
configuring a central processing unit pin connected with a sixteenth pin 16 of the multifunctional interface chip to be a USARTn _ TX function, namely USART logic output;
the central processor pin to which the seventh pin 7 of the multifunction interface chip is connected is configured as USARTn _ RX function, i.e., USART logic input.
As shown in fig. 6, the multifunctional interface chip provides an interface level of an RS485 interface mode through a pin configuration on a signal side connected to the central processing unit, and the specific process is as follows:
reading an EEPROM chip, and determining that the current centralized interface working mode is the RS485 mode according to the RS485 interface mode configuration parameters;
configuring a central processing unit pin connected with the eleventh pin 11 of the multifunctional interface chip to have a GPIO function and output a high level;
configuring a central processing unit pin connected with a twelfth pin 12 of the multifunctional interface chip to have a GPIO function and output a high level;
configuring a central processing unit pin connected with a sixteenth pin 16 of the multifunctional interface chip to be a USARTn _ TX function, namely USART logic output;
configuring a central processing unit pin connected with an eighth pin 8 of the multifunctional interface chip as a USARTn _ RX function, namely USART logic input;
the central processor pin connected with the fifteenth pin 15 of the multifunctional interface chip is configured as USARTn _ DE function, that is, RS485 drive enable of USART.
As shown in fig. 6, the multifunctional interface chip provides an interface level of an RS422 interface mode through a pin configuration on a signal side connected to the central processing unit, and the specific process is as follows:
reading the EEPROM chip, and determining the current centralized interface working mode as the RS422 mode according to the RS422 interface mode configuration parameters;
configuring a central processing unit pin connected with the eleventh pin 11 of the multifunctional interface chip to have a GPIO function and output a high level;
configuring a central processing unit pin connected with a twelfth pin 12 of the multifunctional interface chip to have a GPIO function and outputting a low level;
configuring a central processing unit pin connected with a sixteenth pin 16 of the multifunctional interface chip to be a USARTn _ TX function, namely USART logic output;
the central processor pin to which the eighth pin 8 of the multifunctional interface chip is connected is configured as USARTn _ RX function, i.e., USART logic input.
The power supply is divided into two power domains by DC/DC (i.e., direct current to direct current) conversion, which includes: an interface power domain, otherwise known as an external power domain; platform power domains, otherwise known as internal power domains;
the interface power domain and the platform power domain are electrically isolated and not grounded, and the adopted power supply mode is isolated power supply, so that external power supply noise is avoided or reduced.
Specifically, as shown in fig. 2(a) and 2(b), VIN/+5VCAN and its corresponding AGND (i.e., the triangular symbol in fig. 2(a) and 2 (b)) are interface power domains, i.e., external power domains; the +5V/+3.3V and its corresponding GND are platform power domains, i.e. internal power domains, which are not common in the circuit and are electrically isolated.
Wherein +5V of the internal power source is converted from the external power source VIN by the DC/DC isolation power source U7, and +3.3V is +5V converted from the linear power source U8; +5VCAN is VIN converted from the linear power supply U6.
As shown in fig. 3, the +5VCAN supplies power to the interface side pin 8 of the CAN-FD bus interface chip ISO1042DW (i.e., U4), and the signal side pin 1 of U4 supplies power at +3.3V, which is the same as STM32H743 VI.
The CAN-FD bus communication interface circuits shown in the figures 2(a) and 2(b) and 3 realize power supply and signal double isolation, and are matched with the filtering design of the CAN-FD bus communication interface signals, so that the anti-interference capability of the embedded hardware platform CAN be effectively improved.
The central processing unit STM32H743VI is connected with the Flash chip GD25S512MDFx through a QSPI interface; the central processing unit STM32H743VI is connected with an EEPROM chip BL24C512A-PA through an I2C interface, and the Flash chip and the EEPROM chip are used for storing data.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. An embedded multi-interface data conversion device, comprising: the embedded hardware platform comprises an embedded hardware mainboard and an embedded hardware platform arranged on the embedded hardware mainboard;
the embedded hardware platform is provided with a central processing unit, and the central processing unit is provided with a CAN-FD bus communication interface with double isolation of a power supply and a signal;
the central processing unit is also connected with an RS232-RS485-RS422 centralized communication interface which is convenient for external equipment to be connected and is used for providing any one interface level of an RS232 interface mode, an RS485 interface mode or an RS422 interface mode;
the central processing unit is also connected with an EEPROM chip with an I2C interface and used for storing parameter configuration data of the embedded hardware platform;
the central processing unit is also connected with a Flash chip with a QSPI interface and used for storing state data and log data of the embedded hardware platform in the operation process;
the central processor is also connected with a first connector which is convenient for external equipment to connect and is used for providing a UART interface, an I2C interface and an SPI interface; a UART interface, an SPI interface, an I2C interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the first connector;
the central processor is also connected with a second connector which is convenient for external equipment to connect and is used for providing a UART interface, an SPI interface and an RMII interface; and a UART interface, an SPI interface, an RMII interface and a plurality of GPIO pins of TTL level of the central processing unit are led out to the second connector.
2. The embedded multi-interface data conversion device according to claim 1, wherein the RS232-RS485-RS422 centralized communication interface comprises a multifunctional interface chip and a third connector, and a pin configuration with TTL level on the signal side of the multifunctional interface chip implements any one of interface levels of RS232, RS485 and RS422 on the interface side.
3. The embedded multi-interface data conversion device according to claim 1, wherein the multifunctional interface chip provides any one of interface levels including an RS232 interface mode, an RS485 interface mode, or an RS422 interface mode through a pin configuration on a signal side connected to the central processing unit, and when the central processing unit has a plurality of USART interfaces, USARTn denotes an nth group of interfaces; the specific configuration structure is as follows:
function configuration structure of RS232 interface mode: the central processing unit configures an eleventh pin (11) of the multifunctional interface chip into a low level through the GPIO pin, at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively and correspondingly connected into a sixteenth pin (16) and a seventh pin (7) of the multifunctional interface chip, and a fifth pin (5) and a fourteenth pin (14) of the multifunctional interface chip are respectively used as output and input of an RS232 interface level;
function configuration structure of RS485 interface mode: the central processing unit configures an eleventh pin (11) of the multifunctional interface chip to be a high level through the GPIO pin, configures a twelfth pin (12) of the multifunctional interface chip to be the high level through the GPIO pin, and at the moment, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are correspondingly connected to a sixteenth pin (16) and an eighth pin (8) of the multifunctional interface chip respectively; a USARTn _ DE pin of the central processing unit is used as an input/output control signal of the RS485 interface to be accessed into a fifteenth pin (15) of the multifunctional interface chip, and a sixth pin (6) and a fifth pin (5) of the multifunctional interface chip are used as the positive and negative of differential input/output of the RS485 interface level;
function configuration structure of RS422 interface mode: the central processing unit configures an eleventh pin (11) of the multifunctional interface chip to be a high level through the GPIO pin, configures a twelfth pin (12) of the multifunctional interface chip to be a low level through the GPIO pin, at this time, a logic output USARTn _ TX pin and a logic input USARTn _ RX pin of the central processing unit are respectively connected to a sixteenth pin (16) and an eighth pin (8) of the multifunctional interface chip, a thirteenth pin (13) and a fourteenth pin (14) of the multifunctional interface chip are respectively a differential input positive and a differential input negative of an RS422 level, and a sixth pin (6) and a fifth pin (5) of the multifunctional interface chip are respectively used as a differential output positive and a differential output negative of the RS422 level;
the central processing unit has a pin multiplexing function, and at least two pins can be configured as the same USARTn _ RX logic input function, and the two pins are respectively connected with a seventh pin (7) and an eighth pin (8) of the multifunctional interface chip.
4. The embedded multi-interface data conversion device according to claim 3, wherein the multi-functional interface chip provides an interface level of an RS232 interface mode through a pin configuration of a signal side connected to the central processing unit, and the interface mode configuration is required through the central processing unit, and the specific process is as follows:
reading the EEPROM chip, and determining the working mode of the current centralized interface as the RS232 interface mode according to the configuration parameters of the RS232 interface mode;
a central processing unit pin connected with an eleventh pin (11) of the multifunctional interface chip is configured to have a GPIO function and output a low level;
a central processing unit pin connected with a sixteenth pin (16) of the multifunctional interface chip is configured to be a USARTn _ TX function and used as logic output of the USART;
and a central processor pin connected with a seventh pin (7) of the multifunctional interface chip is configured as a USARTn _ RX function and is used as a logic input of the USART.
5. The embedded multi-interface data conversion device according to claim 3, wherein the multi-functional interface chip provides an interface level of an RS485 interface mode through a pin configuration of a signal side connected with the central processing unit, and the specific process is as follows:
reading an EEPROM chip, and determining that the current centralized interface working mode is the RS485 mode according to the RS485 interface mode configuration parameters;
a central processing unit pin connected with an eleventh pin (11) of the multifunctional interface chip is configured to have a GPIO function and output a high level;
a central processing unit pin connected with a twelfth pin (12) of the multifunctional interface chip is configured to have a GPIO function and output a high level;
a central processing unit pin connected with a sixteenth pin (16) of the multifunctional interface chip is configured to be a USARTn _ TX function and used as logic output of the USART;
a central processing unit pin connected with an eighth pin (8) of the multifunctional interface chip is configured to be a USARTn _ RX function and used as logic input of the USART;
and a central processor pin connected with a fifteenth pin (15) of the multifunctional interface chip is configured to be a USARTn _ DE function and used as RS485 drive enable of the USART.
6. The device of claim 3, wherein the multifunctional interface chip provides an interface level of RS422 interface mode through pin configuration of signal side connected with the CPU, and the specific process is as follows:
reading the EEPROM chip, and determining the current centralized interface working mode as the RS422 mode according to the RS422 interface mode configuration parameters;
a central processing unit pin connected with an eleventh pin (11) of the multifunctional interface chip is configured to have a GPIO function and output a high level;
a central processing unit pin connected with a twelfth pin (12) of the multifunctional interface chip is configured to have a GPIO function and output a low level;
a central processing unit pin connected with a sixteenth pin (16) of the multifunctional interface chip is configured to be a USARTn _ TX function and used as logic output of the USART;
and configuring a central processor pin connected with an eighth pin (8) of the multifunctional interface chip as a USARTn _ RX function as a logic input of the USART.
7. The embedded multi-interface data conversion device according to claim 1, wherein the power supply is divided into two power domains by DC/DC conversion, comprising: an interface power domain and a platform power domain;
the interface power domain and the platform power domain are electrically isolated from each other and are not grounded, and the adopted power supply mode is isolated power supply.
8. The embedded multi-interface data conversion device according to claim 1, wherein the central processing unit is connected to a Flash chip through a QSPI interface; the central processing unit is connected with the EEPROM chip through an I2C interface, and the Flash chip and the EEPROM chip are used for storing data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011361743.3A CN114564426B (en) | 2020-11-27 | 2020-11-27 | Embedded multi-interface data conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011361743.3A CN114564426B (en) | 2020-11-27 | 2020-11-27 | Embedded multi-interface data conversion device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114564426A true CN114564426A (en) | 2022-05-31 |
| CN114564426B CN114564426B (en) | 2024-05-14 |
Family
ID=81711084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011361743.3A Active CN114564426B (en) | 2020-11-27 | 2020-11-27 | Embedded multi-interface data conversion device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114564426B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4884287A (en) * | 1988-04-01 | 1989-11-28 | Ncr Corporation | Converter device for interconnecting systems having different communication standards |
| WO2007079660A1 (en) * | 2006-01-06 | 2007-07-19 | Huawei Technologies Co., Ltd. | Processor chip and memory controlling system and method thereof |
| CN101127023A (en) * | 2006-08-17 | 2008-02-20 | 四川维肯电子有限公司 | Universal asynchronous serial extended chip of multi-bus interface |
| TWM374097U (en) * | 2009-07-24 | 2010-02-11 | Sunix Co Ltd | Connector with serial port power output capability |
| US20120246366A1 (en) * | 2011-03-21 | 2012-09-27 | Hon Hai Precision Industry Co., Ltd. | Serial port remote control circuit |
| WO2015014645A1 (en) * | 2013-07-31 | 2015-02-05 | Siemens Aktiengesellschaft | Selection of an interface type |
| CN105512067A (en) * | 2015-11-25 | 2016-04-20 | 上海创功通讯技术有限公司 | Mobile terminal, port reuse circuit thereof and method |
| CN205450640U (en) * | 2015-11-26 | 2016-08-10 | 北京震宇翱翔文化创意有限公司 | Multiple input detects expander circuit |
| CN205786933U (en) * | 2016-07-19 | 2016-12-07 | 湖北广兴通信科技有限公司 | One kind of multiple style interface testing moulds |
| CN107273320A (en) * | 2016-04-08 | 2017-10-20 | 中兴通讯股份有限公司 | A kind of adaptive multiplexer of communication interface hardware and method |
| CN210573287U (en) * | 2019-09-05 | 2020-05-19 | 北京华电众信技术股份有限公司 | Expansion circuit |
| US20200226087A1 (en) * | 2017-07-20 | 2020-07-16 | Hisense Visual Technology Co., Ltd. | Terminal Device And Control Method Thereof |
| CN213934868U (en) * | 2020-11-27 | 2021-08-10 | 中国科学院声学研究所 | Embedded multi-interface data conversion device |
-
2020
- 2020-11-27 CN CN202011361743.3A patent/CN114564426B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4884287A (en) * | 1988-04-01 | 1989-11-28 | Ncr Corporation | Converter device for interconnecting systems having different communication standards |
| WO2007079660A1 (en) * | 2006-01-06 | 2007-07-19 | Huawei Technologies Co., Ltd. | Processor chip and memory controlling system and method thereof |
| CN101127023A (en) * | 2006-08-17 | 2008-02-20 | 四川维肯电子有限公司 | Universal asynchronous serial extended chip of multi-bus interface |
| TWM374097U (en) * | 2009-07-24 | 2010-02-11 | Sunix Co Ltd | Connector with serial port power output capability |
| US20120246366A1 (en) * | 2011-03-21 | 2012-09-27 | Hon Hai Precision Industry Co., Ltd. | Serial port remote control circuit |
| WO2015014645A1 (en) * | 2013-07-31 | 2015-02-05 | Siemens Aktiengesellschaft | Selection of an interface type |
| CN105512067A (en) * | 2015-11-25 | 2016-04-20 | 上海创功通讯技术有限公司 | Mobile terminal, port reuse circuit thereof and method |
| CN205450640U (en) * | 2015-11-26 | 2016-08-10 | 北京震宇翱翔文化创意有限公司 | Multiple input detects expander circuit |
| CN107273320A (en) * | 2016-04-08 | 2017-10-20 | 中兴通讯股份有限公司 | A kind of adaptive multiplexer of communication interface hardware and method |
| CN205786933U (en) * | 2016-07-19 | 2016-12-07 | 湖北广兴通信科技有限公司 | One kind of multiple style interface testing moulds |
| US20200226087A1 (en) * | 2017-07-20 | 2020-07-16 | Hisense Visual Technology Co., Ltd. | Terminal Device And Control Method Thereof |
| CN210573287U (en) * | 2019-09-05 | 2020-05-19 | 北京华电众信技术股份有限公司 | Expansion circuit |
| CN213934868U (en) * | 2020-11-27 | 2021-08-10 | 中国科学院声学研究所 | Embedded multi-interface data conversion device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114564426B (en) | 2024-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110289859A (en) | Parallel time based on multi-disc ADC replaces High Speed Sampling System | |
| CN103220198A (en) | CAN (Controller Area Network) bus gateway controller for tractor | |
| CN209842611U (en) | Multi-communication interface data exchange board card | |
| CN213934868U (en) | Embedded multi-interface data conversion device | |
| CN213934867U (en) | Embedded multi-interface data acquisition and processing device | |
| CN114564426B (en) | Embedded multi-interface data conversion device | |
| CN202058010U (en) | Portable monitoring control means | |
| CN107370651B (en) | Communication method between SPI slave machines | |
| CN114564425A (en) | Embedded multi-interface data acquisition and processing device | |
| CN111147957B (en) | Gas meter data acquisition device with universal communication interface | |
| CN216956722U (en) | Reinforced intelligent multi-channel digital transmitter | |
| CN101500009A (en) | High speed multi-protocol communication board design method suitable for 10G SFP+ optical module | |
| CN115718529A (en) | Reinforced computer mainboard system based on loongson CPU COME module | |
| CN203250191U (en) | Tractor can bus gateway controller | |
| CN203241752U (en) | Digital analog conversion CAN bus control transmit-receive system connected with multipath-sensor | |
| CN216695019U (en) | Acquisition system for multiplexing laser and optical fiber gyroscope | |
| CN220041216U (en) | Water meter data acquisition device based on Bluetooth SOC | |
| CN219018837U (en) | Photoelectric port automatic identification device and Ethernet equipment | |
| CN109257306A (en) | The embedded L3 Switching device of low-power consumption | |
| CN113541974B (en) | Multi-channel high-frequency digital signal synchronous processing device | |
| CN211319038U (en) | Multi-rocker switch input control panel | |
| CN212933293U (en) | Embedded data processing core board | |
| CN215186786U (en) | Network communication circuit board based on SOC | |
| CN211264137U (en) | Modularization air conditioner electrical system | |
| CN221262911U (en) | Locomotive switching circuit and switching box |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |