CN215895449U - Module and server based on FPGA control peripheral hardware - Google Patents
Module and server based on FPGA control peripheral hardware Download PDFInfo
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- CN215895449U CN215895449U CN202122310046.1U CN202122310046U CN215895449U CN 215895449 U CN215895449 U CN 215895449U CN 202122310046 U CN202122310046 U CN 202122310046U CN 215895449 U CN215895449 U CN 215895449U
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Abstract
The utility model discloses a module and a server based on FPGA control peripheral equipment, wherein the module comprises the following components: the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with the peripheral, the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is in communication with the peripheral through the plurality of interfaces. The utility model can fully utilize input and output resources, reduce the use of internal resources of the FPGA and improve the read-write efficiency of external equipment.
Description
Technical Field
The present invention relates to the field of servers, and more particularly, to a module and a server for controlling peripherals based on an FPGA.
Background
Various Universal sensors and chip devices have various interfaces, such as SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver/Transmitter), I2C (Inter-Integrated Circuit), USB (Universal Serial Bus), and the like, which are used to save Bus and connect with a general-purpose CPU. Each of these interfaces has features that facilitate connection to a conventional CPU, but has disadvantages if controlled by a Field-Programmable Gate Array (FPGA). The FPGA may generate circuit control by itself, or may control the peripheral device by using an IP (Internet Protocol) core of each device, as shown in fig. 1, but these controls all need to consume various software and hardware resources such as an I2C core and a UART core inside the FPGA.
SUMMERY OF THE UTILITY MODEL
In view of this, an embodiment of the present invention provides a module and a server based on an FPGA for controlling peripherals, where an internal bus in the FPGA is connected to a first on-board connector through a first input/output (IO) interface, a processing chip is connected to a second on-board connector through a second IO interface, and the first on-board connector and the second on-board connector are communicatively connected, so as to fully utilize input/output resources and reduce the use of internal resources of the FPGA.
Based on the above object, an aspect of the embodiments of the present invention provides a module for controlling a peripheral device based on an FPGA, including the following components: the system comprises a main core, a first bus and a second bus, wherein the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with peripheral equipment, the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is communicated with the peripheral equipment through the interfaces.
In some embodiments, the first on-board connector and the second on-board connector communicatively coupling comprises: the main core and the coprocessor communicate in a bus read and write separated manner.
In some embodiments, half of the first input/output interfaces of the internal bus of the FPGA connected to the first on-board connector are configured to transmit data of peripheral devices to the FPGA, and the other half are configured to transmit data of the FPGA to corresponding peripheral devices.
In some embodiments, the first input output interface is configured to transmit provisioning information, completion information, data information, type information, device exception notification information, and device exception confirmation information.
In some embodiments, the type information is communicated concurrently with the data information in the form of a bus.
In another aspect of the embodiments of the present invention, a server is provided, which includes a module for controlling a peripheral device based on an FPGA, and the module includes: the system comprises a main core, a first bus and a second bus, wherein the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with peripheral equipment, the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is communicated with the peripheral equipment through the interfaces.
In some embodiments, the first on-board connector and the second on-board connector communicatively coupling comprises: the main core and the coprocessor communicate in a bus read and write separated manner.
In some embodiments, half of the first input/output interfaces of the internal bus of the FPGA connected to the first on-board connector are configured to transmit data of peripheral devices to the FPGA, and the other half are configured to transmit data of the FPGA to corresponding peripheral devices.
In some embodiments, the first input output interface is configured to transmit provisioning information, completion information, data information, type information, device exception notification information, and device exception confirmation information.
In some embodiments, the type information is communicated concurrently with the data information in the form of a bus.
The utility model has the following beneficial technical effects:
the internal bus in the FPGA is connected with the connector on the first board through the first input/output interface, the processing chip is connected with the connector on the second board through the second input/output interface, and the connector on the first board is in communication connection with the connector on the second board, so that input/output resources are fully utilized, and the use of the internal resources of the FPGA is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art FPGA-based peripheral control module;
FIG. 2 is a schematic diagram of an embodiment of a module for controlling peripherals based on an FPGA according to the present invention;
fig. 3 is a schematic diagram of communication signals according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
Some embodiments of the present invention provide an embodiment of a module for controlling a peripheral device based on an FPGA. Fig. 2 is a schematic diagram illustrating an embodiment of the module for controlling peripherals based on an FPGA according to the present invention. As shown in fig. 2, an embodiment of the present invention includes the following components: the system comprises a main core, a first bus and a second bus, wherein the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with peripheral equipment, the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is communicated with the peripheral equipment through the interfaces.
The ASIC processor of the multi-IO 51 core or the ARM core is low in price and has various ready-made software and hardware resources. If the ASIC processor is only used as a coprocessor, the rest IO is very abundant, and the IO is often more sufficient in the use of the FPGA, so the IO of the FPGA can be fully utilized, and the internal resources of the FPGA are reduced. The A-series FPGA of Intel and the TMS-series ARM of TI are used in the embodiment, IO resources are very rich, but the FPGA and the coprocessor are not limited, and if other FPGAs and coprocessors are used, buses can be increased or decreased according to the resources.
In some embodiments, the first on-board connector and the second on-board connector communicatively coupling comprises: the main core and the coprocessor communicate in a bus read and write separated manner. The bus read and write separation can be realized by adopting a part of input and output ports to carry out read operation and the other part of input and output ports to carry out write operation, and the bus read and write separation can also be realized by adopting a mode of reading before writing or writing before reading. Bus read and write separation can improve read and write efficiency to external devices.
In some embodiments, half of the first input/output interfaces of the internal bus of the FPGA connected to the first on-board connector are configured to transmit peripheral data to the FPGA, that is, the peripheral data transmitted from the second on-board connector is transmitted to the FPGA, and the other half of the first input/output interfaces are configured to transmit the FPGA data to the corresponding peripheral, that is, the FPGA data is transmitted to the first on-board connector and then transmitted to the corresponding peripheral through the second on-board connector. In the embodiment of the utility model, 32 IO interconnections are adopted, and the data of the peripheral equipment can be transmitted to the FPGA through 16 IOs, and the data of the FPGA can also be transmitted to the corresponding peripheral equipment through 16 IOs. However, this is not a limitation on the number of IOs, and other numbers of IOs may be employed in other embodiments.
In some embodiments, the first input output interface is configured to transmit preparation, completion, data, type, device exception notification, and device exception acknowledgement information. The first input/output interface may be configured to transmit read preparation, read completion, read data, read type, read device exception notification, and read device exception confirmation information, and the first input/output interface may also be configured to transmit write preparation, write completion, write data, write type, write device exception notification, and write device exception confirmation information.
In some embodiments, the type information is communicated concurrently with the data information in the form of a bus. The bus is a public communication trunk line for transmitting information among various functional components of the computer, and is a transmission line bundle consisting of wires, and the bus of the computer can be divided into a data bus, an address bus and a control bus according to the type of information transmitted by the computer, and the data bus, the address bus and the control bus are respectively used for transmitting data, data addresses and control signals. The bus transmission mode is fast and is convenient for expanding peripheral equipment.
The bit number of each kind of information in this embodiment is as follows: the prepared digit is 1 bit; the number of bits completed is 1 bit; the digit of the data is 8 bits; the number of bits of the type is 4 bits; the number of bits of the exception notification is 1bit, and the number of bits of the exception confirmation is 1 bit. Fig. 3 is a schematic diagram of communication signals according to an embodiment of the present invention. In fig. 3, "master" refers to the master core and "slave" refers to the coprocessor.
As shown in fig. 3, the direction of the read operation is from slave to master, i.e., from the coprocessor to the master core. The read exception notification and the read exception acknowledgement are both low indicating normal and high indicating notification or acknowledgement, but the directions of the read exception notification and the read exception acknowledgement are different, the direction of the read exception notification is from slave to master and the direction of the read exception acknowledgement is from master to slave. That is, the coprocessor sends a read exception notification to the primary core, which sends a read exception acknowledgement to the coprocessor. In read preparation, high prepares valid data for reading, and low indicates that the last valid data is maintained. In the reading completion process, the high data is idle FPGA and can read effective data, and the low data represents the FPGA data processing. The read data bus comprises 8-bit data, the device type and the 8-bit data are simultaneously transmitted in a bus form, and each device has a fixed master-slave data format.
The write operation is in the opposite direction of the read operation, i.e., from the primary core to the coprocessor. The write exception notification and the write exception acknowledgement are both low indicating normal and high indicating notification or acknowledgement, but the direction of the write exception notification and the write exception acknowledgement are different, the direction of the write exception notification being from master to slave and the direction of the write exception acknowledgement being from slave to master. That is, the primary core sends a write exception notification to the coprocessor, which returns a write exception acknowledgement. In write preparation, high is to write valid data, and low is to keep the last valid data. In the write completion, the high order coprocessor is idle, and valid data can be written, and the low order indicates that the coprocessor is in processing. The data bus for writing data includes 8 bits of data, the device type and the 8 bits of data are transmitted in the form of bus at the same time, and each device has a fixed master-slave data format.
The device types in this embodiment include an I2C brightness sensor, an I2C temperature sensor, I2C parameter storage data, UART communication, infrared remote control data, a foreign key value, and the like. Each device has a corresponding ID number, for example, the ID number of an I2C luminance sensor is 0X01 and the ID number of an I2C temperature sensor is 0X 02. The ID number may also be added during data transmission.
In view of the above, a second aspect of the embodiments of the present invention provides a server, including a module for controlling a peripheral device based on an FPGA, where the module includes: the system comprises a main core, a first bus and a second bus, wherein the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with peripheral equipment, the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is communicated with the peripheral equipment through the interfaces.
In some embodiments, the first on-board connector and the second on-board connector communicatively coupling comprises: the main core and the coprocessor communicate in a bus read and write separated manner.
In some embodiments, half of the first input/output interfaces of the internal bus of the FPGA connected to the first on-board connector are configured to transmit data of peripheral devices to the FPGA, and the other half are configured to transmit data of the FPGA to corresponding peripheral devices.
In some embodiments, the first input output interface is configured to transmit preparation, completion, data, type, device exception notification, and device exception acknowledgement information.
In some embodiments, the type information is communicated concurrently with the data information in the form of a bus.
Those skilled in the art should understand that the above description of the module for controlling the peripheral device based on the FPGA is applicable to the server, and for brevity of the description, the description is omitted here.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the utility model may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the utility model is limited to these examples; within the idea of an embodiment of the utility model, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the utility model as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. The utility model provides a module based on FPGA control peripheral hardware which characterized in that includes following part:
the system comprises a main core, a first bus and a second bus, wherein the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; and
the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with peripheral equipment, wherein the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is communicated with the peripheral equipment through the interfaces.
2. The module of claim 1, wherein the first on-board connector and the second on-board connector communicatively couple comprises:
the main core and the coprocessor communicate in a bus read and write separated manner.
3. The module of claim 2, wherein half of the first input/output interfaces of the internal bus of the FPGA connected to the first on-board connector are configured to transmit peripheral data to the FPGA, and the other half are configured to transmit the data of the FPGA to a corresponding peripheral.
4. The module of claim 3, wherein the first I/O interface is configured to transmit prepare information, completion information, data information, type information, device exception notification information, and device exception confirmation information.
5. The module of claim 4, wherein the type information and the data information are simultaneously transmitted in a bus.
6. The utility model provides a server, its characterized in that includes the module based on FPGA control peripheral hardware, the module includes:
the system comprises a main core, a first bus and a second bus, wherein the main core comprises an FPGA and a first on-board connector, and an internal bus in the FPGA is connected with the first on-board connector through a first input/output interface; and
the coprocessor comprises a processing chip, a second on-board connector and a plurality of interfaces connected with peripheral equipment, wherein the processing chip is connected with the second on-board connector through a second input/output interface, the first on-board connector is in communication connection with the second on-board connector, and the processing chip is communicated with the peripheral equipment through the interfaces.
7. The server of claim 6, wherein the first on-board connector and the second on-board connector communicatively couple comprises:
the main core and the coprocessor communicate in a bus read and write separated manner.
8. The server according to claim 7, wherein half of the first input/output interfaces of the internal bus of the FPGA connected to the first on-board connector are configured to transmit data of peripheral devices to the FPGA, and the other half are configured to transmit data of the FPGA to corresponding peripheral devices.
9. The server according to claim 8, wherein the first i/o interface is configured to transmit preparation information, completion information, data information, type information, device exception notification information, and device exception confirmation information.
10. The server according to claim 9, wherein the type information is transferred in a bus form simultaneously with the data information.
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| CN202122310046.1U CN215895449U (en) | 2021-09-23 | 2021-09-23 | Module and server based on FPGA control peripheral hardware |
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| CN202122310046.1U CN215895449U (en) | 2021-09-23 | 2021-09-23 | Module and server based on FPGA control peripheral hardware |
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