CN114561675B - Method for controlling copper thickness of electroplating hole filling surface of printed circuit - Google Patents
Method for controlling copper thickness of electroplating hole filling surface of printed circuit Download PDFInfo
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- CN114561675B CN114561675B CN202210323016.0A CN202210323016A CN114561675B CN 114561675 B CN114561675 B CN 114561675B CN 202210323016 A CN202210323016 A CN 202210323016A CN 114561675 B CN114561675 B CN 114561675B
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/38—Coating with copper
- C23C18/40—Coating with copper using reducing agents
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/30—Acidic compositions for etching other metallic material
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
- H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P10/00—Technologies related to metal processing
- Y02P10/20—Recycling
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- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electrochemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
A method for controlling copper thickness of electroplating hole filling surface of printed circuit belongs to the technical field of printed circuit boards. The method comprises the following steps: depositing a conductive buffer layer on the base plate by adopting an electroplating or chemical plating method; forming a through hole; soaking in a passivation solution to form a passivation layer on the conductive buffer layer; flash plating a copper layer on the passivation layer; depositing a copper layer on the wall of the through hole by adopting a chemical copper deposition process; performing copper filling electroplating on the through holes; etching the copper layer on the passivation layer until the conductive buffer layer is etched; soaking in the etching solution of the conductive buffer layer to remove the conductive buffer layer; and removing the copper column at the hole opening of the etched through hole to obtain a smooth and flat copper layer. The invention adopts the copper reduction process to obtain the flat surface copper with no dent in the orifice, has simple process and high reliability, can realize large-scale industrialization, and provides an effective method for manufacturing the circuit board with higher frequency requirement in the 5G era.
Description
Technical Field
The invention belongs to the technical field of printed circuit boards, and particularly relates to a method for controlling the copper thickness of a printed circuit electroplating hole filling surface.
Background
With the development of 5G communication technologies, the requirements for data transmission speed of various applications such as servers, intelligent driving, internet of things and the like are faster and faster, the volumes of various electronic products are gradually reduced, and the integration level of electronic components is higher, so that the functions of the electronic products must be realized by means of the electronic components and the electrical interconnection among the electronic components, and the development speed of the printed circuit board serving as a main carrier for the electrical interconnection among the electronic components must limit the advancing steps of the 5G technology.
The high-density interconnection printed circuit board is manufactured through the technology of blind hole burying and through hole burying, so that each electronic element has higher integration level, and electronic products gradually develop towards the directions of smaller volume and higher reliability. The process of manufacturing the board usually uses a core board to complete hole stacking through the processes of drilling, electroless copper plating, full board electroplating, resin hole plugging, secondary electroplating, etching and windowing, laser drilling, blind hole filling and the like. However, the through hole resin plug hole is easy to have defects, so that the hole stacking failure is caused, and the signal transmission is affected. In addition, the resin is easy to break holes due to the difference of temperature expansion coefficients of the resin and the substrate material after plugging holes, thereby affecting the reliability. To solve the above problems, a micro via hole filling plating technique may be employed to enhance the electrical and thermal conductivity of the interconnect lines and the mechanical strength of the board to achieve good electrical interconnection.
The micro via hole filling electroplating technology needs special hole filling electroplating liquid, wherein the most important is the use of electroplating additives, and the deposition speed of copper ions at different positions of a hole wall is regulated and controlled through the adsorption action of different additives on the hole wall, so that the deposition speed of the copper ions at the center of the hole wall is the fastest, and the hole filling is completed. However, as copper ions are deposited in the holes, the thickness of the surface copper plating layer is always increasing and large depressions exist at the holes, and the reliability of manufacturing the circuit board is greatly affected by the deep depressions. For subsequent fine line fabrication, the surface copper thickness needs to be reduced below the line required thickness. At present, a method of etching or polishing a board to reduce copper is generally adopted in a circuit board production line, however, the etching solution cannot ensure the same etching speed at all positions of a copper surface, so that the copper surface is very rough after being soaked in the etching solution for a long time, a circuit cannot be manufactured, and the long-time sand paper polishing board can cause the phenomenon of uneven thickness of the board surface.
Therefore, the thickness control of the surface copper layer needs to be considered in electroplating to fill the through holes so as to ensure the subsequent fine circuit manufacture. Currently, the prior art has disclosed controlling the surface copper thickness by improving the quality of the surface copper plating by increasing the plating rate and modifying the plating apparatus. Chen Huanzong et al (patent publication No. CN 103320844A) propose a plating process surface copper control device, by arranging accompanying plating bars on both side edges of a circuit board and arranging a floating plate structure between the bottom of a plating tank and the circuit board, the copper plating thickness is effectively controlled, but the structure can only limit the surface copper thickness at a specified position and cannot be applied to plating filling holes. Tang XiaoPing et al (patent publication No. CN 107090589A) propose a PCB electroplating device and an electroplating thickness control method, wherein the electroplating floating groove and the baffle plate move to shield the whole part of the plate surface, so that the uniform control of the thickness value of the electroplating layer of the plate surface is realized. Although the method can control the thickness of the plating layer through the baffle plate, the method can block the filling hole of the through hole and is not suitable for controlling the thickness of the surface copper during electroplating filling the through hole.
Disclosure of Invention
The invention aims to provide a method for controlling the thickness of copper on a hole filling surface of electroplating of a printed circuit, aiming at the defects existing in the background technology.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a method for controlling the thickness of copper on the electroplating hole filling surface of a printed circuit comprises the following steps:
step 1, depositing a conductive buffer layer on a base plate by adopting an electroplating or chemical plating method;
step 6, carrying out copper filling electroplating on the through holes; wherein the electroplating current is direct current or pulse, and the current density is 0.4A/dm 2 ～3.0A/dm 2 ；
Step 7, etching the copper layer on the passivation layer by adopting an etching method until the conductive buffer layer is etched;
step 8, soaking the circuit board obtained after the treatment in the step 7 in a conductive buffer layer etching solution to remove the conductive buffer layer;
and 9, removing the copper column at the hole opening of the residual through hole after etching in the step 8, so as to obtain a smooth and flat copper layer for manufacturing the fine circuit.
Further, the base board in step 1 is a core board, a multilayer board of pressed prepregs and copper foils, or a circuit board requiring through hole interconnection such as a high-density interconnection printed circuit board.
Further, the conductive buffer layer in step 1 is a metal layer with metal activity stronger than that of copper, and is used for protecting the bottom copper from etching and conducting subsequent electroplating hole filling, and the thickness of the conductive buffer layer is 2-40 μm.
Further, the through hole in the step 2 is obtained by adopting a mechanical drilling method, and the aperture of the through hole is 100-300 mu m.
Further, the passivation solution in step 3 includes: 0.5-5 g/L of triethanolamine phosphate, 4-20 g/L of phosphate imidazolinone and 2-6 g/L of benzalkonium chloride.
Further, the flash plating in the step 4 adopts a vertical continuous plating line flash plating process, and the thickness of the copper layer obtained by flash plating is 2-5 μm.
Furthermore, the electroless copper plating process in the step 5 comprises the processes of removing glue, neutralizing, removing oil, microetching, activating and reducing.
Further, the copper filling electroplating of the through hole in the step 6 is realized by adopting gantry line electroplating or vertical continuous electroplating.
Further, the etching solution adopted in the etching method in step 7 is cupric chloride, and cupric chloride oxidizes copper ions into cuprous ions, so that the copper layer on the surface is etched.
Further, the etching solution for the conductive buffer layer in step 8 includes: 70-300 g/L of dilute nitric acid, 1-6 g/L of amido gemini quaternary ammonium salt and 50-200 g/L of ferric nitrate.
Further, in step 9, copper pillars at the openings of the residual through holes after etching in step 8 are removed by adopting a plate grinding line deburring and sharp cutting process, and the abrasive paper for polishing the openings is 2400 meshes or more.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a method for controlling the thickness of copper on a hole-filling surface of electroplating of a printed circuit, which adopts a copper reduction process to obtain flat copper on a surface with no dent on an orifice, has simple process and high reliability, can realize large-scale industrialization, and provides an effective method for manufacturing a circuit board with higher frequency requirement in the 5G era.
Drawings
FIG. 1 is a flow chart of a method for controlling the copper thickness of a printed circuit electroplating hole filling surface;
FIG. 2 is a cut-away view of a circuit board after copper-filled electroplating of the via holes in step 6 of the present invention;
FIG. 3 is a slice view of the polished plate obtained in step 9 of the present embodiment;
FIG. 4 is a slice view of the comparative example obtained in step 3 after electroplating hole filling;
fig. 5 is a slice view after etching obtained in step 4 of comparative example.
In the accompanying drawings: 1. copper on the substrate surface; 2. an insulating substrate; 3. a tin buffer layer; 4. a through hole; 5. flash copper plating; 6. electroless copper plating in the holes; 7. plating a surface copper layer; 8. copper is filled in the holes.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples.
Examples
A method for controlling the thickness of copper on the electroplating hole filling surface of a printed circuit specifically comprises the following steps:
step 1, depositing a metal tin layer with the thickness of 20 mu m on a base plate by adopting an electroplating method, wherein the metal tin layer is used as a conductive buffer layer, and a circuit board after tin electroplating is shown in (2) in fig. 1; wherein the base plate is a copper-clad plate (shown as (1) in figure 1) composed of a base material with the thickness of 180 mu m and a substrate surface copper with the thickness of 17.5 mu m;
step 6, carrying out through hole copper filling electroplating on the circuit board subjected to electroless copper deposition by adopting gantry wire electroplating, wherein the electroplating current is direct current, and the current density is 0.8A/dm 2 Filling the through holes after electroplating for 2 hours, wherein the growing thickness of the electroplated copper layer is 50 mu m, the circuit board after copper filling electroplating of the through holes is shown in (5) in fig. 1, and the slicing diagram of the circuit board after copper filling electroplating of the through holes is shown in fig. 2;
step 7, using copper chloride as etching solution, and etching the copper layer on the passivation layer by adopting an etching method until the tin conductive buffer layer is etched; the etched circuit board is shown in fig. 1 (6);
step 8, soaking the circuit board obtained after the treatment in the step 7 in a conductive buffer layer etching solution to remove the tin conductive buffer layer, wherein the circuit board after tin etching is shown in (7) in fig. 1; wherein, the conductive buffer layer etching solution comprises: 200g/L of dilute nitric acid, 3g/L of amido gemini quaternary ammonium salt and 60g/L of ferric nitrate;
and 9, removing copper columns at the positions of the residual through hole openings after etching in the step 8 by using 4000-mesh sand paper through a grinding plate line, wherein a slicing diagram after grinding the plate is shown in fig. 3.
Comparative example
Step 1, forming a through hole with the aperture of 200 mu m on a basic plate by adopting a mechanical drilling method; wherein the base plate is a copper-clad plate consisting of a base material with the thickness of 180 mu m and substrate surface copper with the thickness of 17.5 mu m;
and 4, soaking the circuit board subjected to electroplating hole filling in a copper chloride etching solution for about 20min, and slicing the etched circuit board according to the graph shown in fig. 5.
As can be seen from fig. 2-5, the existence of a large recess at the copper-reducing orifice after direct electroplating in the comparative example can seriously affect the reliability of subsequent circuit fabrication; while the embodiment can obtain a flat surface copper layer with no concave orifice through reducing copper by the buffer layer.
The above description is only an example of the present invention and is not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. The method for controlling the copper thickness of the electroplating hole filling surface of the printed circuit is characterized by comprising the following steps:
step 1, depositing a conductive buffer layer on a base plate by adopting an electroplating or chemical plating method; the conductive buffer layer is a metal layer with metal activity stronger than copper, and the thickness of the conductive buffer layer is 2-40 mu m;
step 2, forming a through hole on the plate obtained after the treatment in the step 1;
step 3, soaking the plate obtained after the treatment in the step 2 in a passivation solution for 15-20 min, and forming a passivation layer on the conductive buffer layer;
step 4, flash plating a copper layer on the passivation layer obtained in the step 3;
step 5, depositing a copper layer with the thickness of 0.2-0.6 mu m on the hole wall of the through hole by adopting a chemical copper deposition process;
step 6, carrying out copper filling electroplating on the through holes; wherein the electroplating current is direct current or pulse, and the current density is 0.4A/dm 2 ～3.0A/dm 2 ；
Step 7, etching the copper layer on the passivation layer by adopting an etching method until the conductive buffer layer is etched;
step 8, soaking the circuit board obtained after the treatment in the step 7 in a conductive buffer layer etching solution to remove the conductive buffer layer;
and 9, removing the copper column at the hole opening of the residual through hole after etching in the step 8 to obtain a smooth and flat copper layer.
2. The method for controlling the copper thickness of the electroplating hole filling surface of the printed circuit according to claim 1, wherein the through hole in the step 2 is obtained by adopting a mechanical drilling method, and the aperture of the through hole is 100-300 μm.
3. The method for controlling copper thickness on a plated hole-filling surface of a printed circuit according to claim 1, wherein the passivation solution in step 3 comprises: 0.5-5 g/L of triethanolamine phosphate, 4-20 g/L of phosphate imidazolinone and 2-6 g/L of benzalkonium chloride.
4. The method for controlling the copper thickness of the electroplating hole filling surface of the printed circuit according to claim 1, wherein in the step 4, a vertical continuous electroplating line flash plating process is adopted, and the thickness of a copper layer obtained by flash plating is 2-5 μm.
5. The method for controlling copper thickness on a hole filling surface in a printed circuit board according to claim 1, wherein the through hole copper filling plating in step 6 is implemented by using a gantry line plating or a vertical continuous plating.
6. The method for controlling copper thickness on a hole-filling surface for electroplating of a printed circuit according to claim 1, wherein the etching solution used in the etching method in the step 7 is copper chloride.
7. The method for controlling copper thickness on a plated via hole filling surface of a printed circuit according to claim 1, wherein the etching solution for the conductive buffer layer in step 8 comprises: 70-300 g/L of dilute nitric acid, 1-6 g/L of amido gemini quaternary ammonium salt and 50-200 g/L of ferric nitrate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210323016.0A CN114561675B (en) | 2022-03-29 | 2022-03-29 | Method for controlling copper thickness of electroplating hole filling surface of printed circuit |
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| CN202210323016.0A CN114561675B (en) | 2022-03-29 | 2022-03-29 | Method for controlling copper thickness of electroplating hole filling surface of printed circuit |
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| CN114561675B true CN114561675B (en) | 2023-04-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9281274B1 (en) * | 2013-09-27 | 2016-03-08 | Stats Chippac Ltd. | Integrated circuit through-substrate via system with a buffer layer and method of manufacture thereof |
| CN106132116A (en) * | 2016-07-05 | 2016-11-16 | 广州美维电子有限公司 | A kind of wiring board blind hole fills out process for copper |
| CN110248474A (en) * | 2019-06-10 | 2019-09-17 | 江门崇达电路技术有限公司 | A kind of production method of high-frequency high-speed random layer HDI plate laser blind hole |
| CN111107715A (en) * | 2020-01-15 | 2020-05-05 | 江门崇达电路技术有限公司 | Manufacturing method of HDI plate back drilling hole |
| CN111405759B (en) * | 2020-02-17 | 2021-10-19 | 广东科翔电子科技股份有限公司 | Method for preparing high-precision communication optical module printed circuit board |
| CN111654979A (en) * | 2020-06-30 | 2020-09-11 | 博敏电子股份有限公司 | Method for embedding copper pillar in seamless connection mode in through hole |
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