JP2009021581A - Buried copper plating method for manufacturing printed circuit board and printed circuit board obtained employing the buried copper plating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plating method for burying the inside of a through hole and a via hole employing electrolytic method or buried plating method excellent in production cost and reduced in positional deviation between the surface of the buried metal plating layer and the surface of external layer of the printed circuit. <P>SOLUTION: The buried copper plating method for manufacturing the printed circuit board, which comprises two-stage plating process consisting of a first buried copper plating process and a second buried copper plating process while copper plating solution, having the same composition, is employed in the first buried copper plating process and the second buried copper plating process, in the buried copper plating method wherein the inside of the via hole or the through hole equipped with a conductive film is buried through electric plating method. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a buried copper plating method for producing a printed wiring board and a printed wiring board obtained by using the buried copper plating method.

  In recent years, electronic devices and electric products are required to be small in size, high in performance, and multifunctional. Therefore, miniaturization is also required for printed wiring boards used for controlling electrical signals and power of these products. Then, when the printed wiring board is downsized, a multilayer printed wiring board has been adopted from the viewpoint of simultaneously satisfying the demand for higher signal transmission speed.

  This multilayer printed wiring board is in a state where three or more circuit layers are laminated via an insulating resin layer. In order to ensure electrical connection between circuit layers of the multilayer printed wiring board in such a laminated state, a through hole as disclosed in Patent Document 1, a via hole as disclosed in Patent Document 2, and the like Has been used as an interlayer conduction means.

  The interlayer conduction means such as through holes and via holes are holes penetrating through the insulating resin layer of the printed wiring board, or recess-shaped holes such as so-called blind via holes, and at least the inner wall surface of the interlayer conduction plating Form a layer. This interlayer conductive plating layer is formed by plating in the order of electroless plating and electrolytic plating because the insulating resin layer having no conductivity is exposed on the inner wall surfaces of the through holes and via holes before plating.

  The through hole and the via hole are sufficient as required functions as long as conduction between the overlapping circuit surfaces can be secured. Therefore, the interlayer conductive plating is generally not performed to such an extent that a conductor layer is formed on the inner wall surfaces of the through holes and via holes, and the insides of the through holes and via holes can be embedded. However, if the insides of the through holes and via holes are hollow after the interlayer conductive plating, the bonding of the etching resist when performing the etching process of the outer conductive layer after the interlayer conductive plating becomes uneven around the through holes and via holes. In addition, it is impossible to mount components on the through holes and via holes, and there is a limit to downsizing of the printed wiring board.

  Therefore, a method of burying internal voids of through holes and via holes has been adopted. For example, in Patent Document 3, as a method of forming a flattened multilayer wiring layer, a catalyst is deposited on the first wiring layer and the resist mask at the bottom of the through hole, and the resist mask is removed together with the catalyst on the resist mask. For this reason, since the surface of the bottom of the through hole can be activated regardless of the material of the bottom of the through hole, it is disclosed that plating is embedded in the through hole by an electroless plating method to form a plating layer. As a result, it is possible to form a flat multilayer wiring layer having no step, prevent disconnection at the step of each layer, and obtain a good interlayer connection.

  Further, in Patent Document 4, a through-hole that conducts both sides of a wiring board and a mounting land are provided at the same location, and is provided on a double-sided copper-clad laminate for the purpose of providing a cheap printed wiring board having a large mounting area. After the conductive ink was embedded in the through-hole holes and cured under predetermined conditions, electrolytic copper plating was performed on both sides of the double-sided copper-clad laminate to form a copper plating layer, and then the cured A method is employed in which a circuit in which a component mounting land is installed immediately above the conductive ink is drawn on the copper plating layer using a dry film or other circuit forming ink, and the circuit is formed by etching or the like.

  Further, in Patent Document 5, a wall surface including an insulating layer surface of a substrate and a bottom surface of the via hole is provided for the purpose of providing a via filling plating method capable of satisfactorily filling a small-diameter via hole having a large aspect ratio with copper plating. A copper film forming step for forming a copper film on the substrate, a dipping process for immersing the substrate on which the copper film is formed in an aqueous solution to which a plating accelerator is added, and attaching the plating accelerator to the surface of the copper film; A peeling process to remove the plating accelerator adhering to the surface of the copper film excluding the inner wall surface including the bottom surface of the copper, and a copper film formed on the insulating film surface and the wall surface including the bottom surface of the via hole after the peeling process A method characterized by including an electrolytic copper plating step of applying electrolytic copper plating on the film and filling the via hole with a plating metal.

JP-A-5-166939 JP-A-5-218618 Japanese Patent Laid-Open No. 2001-291554

  However, the inventions disclosed in Patent Documents 3 to 5 have the following problems.

  In the invention disclosed in Patent Document 3, an electroless plating method is used to form a plating layer embedded in a through hole. This electroless plating method is superior in cost because it does not energize, but is not a method with excellent productivity because it requires more time to embed plating in a through hole than in the electrolysis method. . In addition, it is difficult to form an embedded plating layer in which the surface of the embedded plating layer formed by the electroless plating method is controlled as a deviation in the depth direction within 5 μm from the position of the outer surface of the printed wiring. Therefore, if an etching resist layer is provided on the outer layer after this embedded plating, the etched resist layer floats in the embedded plating layer portion when it is depressed, and exposure blurring is likely to occur during exposure to form an etching resist pattern. For this reason, it becomes difficult to form a fine pitch circuit. Moreover, if the deviation in the depth direction of the through hole portion exceeds 5 μm, it becomes impossible to use the embedded plating surface of the through hole as a component mounting land.

  In the case of the invention disclosed in Patent Document 4, the through-hole hole is embedded by filling the through-hole hole provided in the double-sided copper-clad laminate with conductive ink and curing it. However, since the conductive ink is composed of a resin component and a metal particle component, and a remarkable shrinkage phenomenon occurs when the conductive ink is cured, the surface of the conductive ink embedded and cured is printed. It is difficult to match the position of the surface of the outer layer of the wiring, and a displacement exceeding 5 μm tends to occur in the depth direction in the through-hole portion. Therefore, the same problem as in Patent Document 3 occurs.

  On the other hand, Patent Document 5 adopts a method of filling the via hole with a copper component, and uses electrolytic copper plating when filling the final via hole with copper. That is, according to the content disclosed in Patent Document 5, "a copper film forming step of forming a copper film on the wall surface including the insulating layer surface of the substrate and the bottom surface of the via hole", "in the aqueous solution to which the plating accelerator is added, "Immersion process to immerse the substrate on which the copper film is formed and attach the plating accelerator to the copper film surface", "Peeling process to remove the plating accelerator adhering to the copper film surface excluding the inner wall surface including the bottom surface of the via hole" "After the stripping process, electrolytic copper plating process to fill the via hole with electrolytic copper plating on the copper film formed on the insulating layer surface and the copper film formed on the wall surface including the bottom of the via hole “The above steps are necessary. Here, “a dipping process in which a substrate on which a copper film is formed is immersed in an aqueous solution to which a plating accelerator is added and the plating accelerator is attached to the surface of the copper film” and “the inner wall surface including the bottom surface of the via hole are excluded. The fact that the “peeling step for removing the plating accelerator adhering to the surface of the copper film” is required means that the number of steps is increased accordingly and the production cost is increased.

  As can be understood from the above, it is a plating method that can finally embed the inside of the through hole and the via hole by using an electrolytic method, which is excellent in production cost, and the surface of the metal plating layer in which the through hole and the via hole are buried is Therefore, there has been a demand for a buried plating method for through holes and via holes, which can easily match the position of the surface of the outer layer of the printed wiring and can form a buried state with fewer depressions.

  Thus, as a result of diligent research, the present inventors have come up with a via hole or through hole buried copper plating method described below.

Embedded copper plating method according to the present invention: The embedded copper plating method according to the present invention includes a first embedded copper plating step in an embedded copper plating method in which an inside of a via hole or a through hole provided with a conductive film is embedded by electroplating. A printed wiring board manufacture comprising a two-stage plating process comprising a second embedded copper plating process, and using a copper plating solution having the same composition in the first embedded copper plating process and the second embedded copper plating process Adopt buried copper plating method.

  In the embedded copper plating method according to the present invention, the copper plating solution is preferably a copper plating solution having a solution temperature of 20 ° C. to 30 ° C. and a copper concentration of 30 g / L or more.

  In the embedded copper plating method according to the present invention, it is preferable to provide a non-energization time of 1 second to 600 seconds between the first embedded copper plating step and the second embedded copper plating step.

  In the embedded copper plating method according to the present invention, it is preferable that the first embedded copper plating step performs embedded copper plating using a current density larger than a current density used in the second embedded copper plating step.

In the buried copper plating method according to the present invention, it is preferable that the first buried copper plating step is copper plated using a current density in a range of 1 A / dm ^{2 to} 5 A / dm ² .

In the embedded copper plating method according to the present invention, the first embedded copper plating step preferably includes a plurality of sub-plating steps using a current density in a range of 1 A / dm ^{2 to} 5 A / dm ² .

  It is also preferable to provide at least one no-energization time of 1 second to 600 seconds between the plurality of sub-plating steps.

  Moreover, it is preferable that the said 1st embedded copper plating process performs the embedded copper plating for the thickness of 0.3 micrometer-5 micrometers.

In the embedded copper plating method according to the present invention, it is preferable that the second embedded copper plating step performs copper plating using a current density in a range of 0.5 A / dm ^{2 to} 4 A / dm ² .

Printed wiring board according to the present invention: The printed wiring board according to the present invention is characterized in that embedded copper plating is performed using the embedded copper plating method for manufacturing the printed wiring board described above.

  The embedded copper plating method for producing a printed wiring board according to the present invention includes the first embedded copper plating step and the second embedded copper plating step, and there is a difference in current density during electrolysis in each step. However, the same copper plating solution can be used, and the process can be shortened. Moreover, by making it possible to use the same copper plating solution, it is also possible to design the embedded copper plating production line as one line, thereby reducing the manufacturing equipment cost and the management cost, and as a result, the printed wiring board. It also leads to reduction of product manufacturing costs.

  In addition, in this buried copper plating method for manufacturing printed wiring boards, the same copper plating solution is used in all of the buried plating processes, and finally the electrolytic plating method is adopted, so that the copper having buried through holes and via holes is obtained. Control of the surface state of plating is easy. As a result, the printed wiring board manufactured using this buried copper plating method is easy to match the position of the buried copper plating surface of the through hole and via hole and the outer layer surface of the printed wiring in the depth direction within 5 μm. Since it is possible to form a buried state with little misalignment, the adhesion between the etching resist to be formed later and the copper plating surface of the through hole and via hole is good, and the exposure blur of the etching resist does not occur. Is excellent. Furthermore, since there are few depressions in the through holes and via holes, it becomes easy to use the buried copper plating surfaces of the through holes and via holes as component mounting lands.

  Hereinafter, each embodiment of the embedded copper plating method according to the present invention and the printed wiring board according to the present invention will be described.

Form of buried copper plating method according to the present invention: The buried copper plating method according to the present invention is a buried copper plating method in which a via hole or a through hole having a conductive film is buried by an electroplating method. In the buried copper plating method according to the present invention, since the purpose is to bury the inside of the “via hole or through hole” by electroplating, the printed wiring board is more than a double-sided printed wiring board having two circuit layers. It is clear that the target is a multilayer printed wiring board. This is because it is not necessary to provide via holes or through holes in the case of a single-sided printed wiring board.

  Next, the “conductive film” referred to here will be described. The conductive coating is generally a copper coating, a nickel coating, a gold coating or the like formed by electroless plating. That is, the via hole or the through hole of the printed wiring board is formed by drilling the printed wiring board using a mechanical drill, laser processing, or the like. Since the resin layer of the insulating resin substrate is exposed on the inner wall surface of the via hole or through hole after this drilling process, it cannot be energized, so the metal layer is formed as a conductive film on the inner wall surface by electroless plating. It forms. Therefore, any material may be used for the conductive film as long as it can be energized and has excellent adhesion to the insulating resin substrate.

  The buried copper plating method according to the present invention includes a two-step plating process including a first buried copper plating process and a second buried copper plating process. And it is a big feature that the copper plating solution of the same composition is used in the first embedded copper plating step and the second embedded copper plating step.

  Here, the copper plating solution used in common in the first embedded copper plating step and the second embedded copper plating step will be described. The copper plating solution used here is preferably a copper plating solution having a copper concentration of 30 g / L or more. As long as this condition is satisfied, there is no limitation on plating solution systems such as a sulfuric acid-based copper plating solution and a pyrophosphate-based copper plating solution. Here, when the copper concentration is less than 30 g / L, the copper deposition rate becomes slow, and as the copper concentration decreases, uniform embedded copper plating becomes impossible. Moreover, it is more preferable to use it as a copper plating solution having a copper concentration of 50 g / L or more. This is because the burying performance of the deposited copper is stabilized and the smoothness of the deposited surface is improved. Here, the upper limit copper concentration is not particularly specified. The reason for this is that the following liquid temperature exists, and it is possible to increase the concentration to the saturation concentration within the following liquid temperature range.

  Next, it is preferable to use the copper plating solution in a temperature range of 20 ° C to 30 ° C. In electrolytic copper plating, the liquid temperature is an important factor that affects the properties of the deposited copper plating layer. For example, it affects the hardness, crystal structure, density, etc. of the deposited copper. As a result of earnest research on the premise that buried copper plating is performed, the above range was most appropriate. Here, when the liquid temperature is less than 20 ° C., precipitated copper having a high density is obtained, but the deposition rate becomes slow. At the same time, from an industrial point of view, in order to obtain a liquid temperature of less than 20 ° C., it is necessary to cool the copper plating solution, which affects the equipment cost. On the other hand, when the liquid temperature exceeds 30 ° C., the copper deposition rate increases, but the flatness of the plating surface during the buried copper plating is lost, and the buried copper plating surface of the through hole and via hole and the printed wiring It is difficult to control the deviation in the depth direction within 5 μm so as to match the position of the outer layer surface. In order to ensure the significance of the liquid temperature control described above, it is preferable to set the temperature within the range of 22 ° C to 28 ° C, more preferably 23 ° C to 26 ° C.

  In the buried copper plating method according to the present invention, it is preferable that a certain non-energization time is provided between the first buried copper plating step and the second buried copper plating step. That is, the first embedded copper plating step and the second embedded copper plating step can be designed as a single embedded copper plating production line, which is a great advantage of adopting the embedded copper plating method according to the present invention. .

  At this time, the first embedded copper plating step and the second embedded copper plating step are continuously arranged, and the current density used in the first embedded copper plating step is used in the second embedded copper plating step. It is also possible to continuously change the current density to be changed. However, in the case of the buried copper plating method according to the present invention, when changing from the current density used in the first buried copper plating step to the current density used in the second buried copper plating step, the current flow once. There must be no un-energized state for a certain period of time, so that the influence of the plating operation of the first embedded copper plating process is not given to the second embedded copper plating process, and the plating conditions of each process must be clearly separated In addition, it becomes difficult to control the buried copper plating surface of the through hole and via hole and the position of the outer layer surface of the printed wiring with accuracy within 5 μm in the depth direction.

  Here, when the non-energization time is less than 1 second, the second embedded copper plating process is affected by the plating operation of the first embedded copper plating process, and each process is clearly separated. It is not possible to flatten the buried copper plating surface. On the other hand, if this non-energization time exceeds 600 seconds, the copper plating layer in the activated state formed in the first embedded copper plating step is in a state where it is exposed to the atmosphere or solution without being energized. As the oxidation progresses, useless copper oxide formation occurs, and the adhesion between the copper plating layer formed in the first embedded copper plating step and the copper plating layer formed in the second embedded copper plating step deteriorates, Uniform buried copper plating cannot be performed, and the buried copper plating surface cannot be flattened. And in order to achieve more reliably the meaning which provides the said non-energization time, the non-energization time is 5 second-500 second, More preferably, it is 10 second-350 second.

  Subsequently, the current density used in the first embedded copper plating step and the second embedded copper plating step of the embedded copper plating method according to the present invention will be described. First, “current density used in the first embedded copper plating step (hereinafter referred to as“ first current density ”)” and “current density used in the second embedded copper plating step (hereinafter referred to as“ second current density ”). The relationship with “density” may be [first current density] = [second current density]. This is because by providing the non-energization time between the first embedded copper plating step and the second embedded copper plating step, good embedded copper plating becomes possible.

  As for the current density, it is more preferable to satisfy the relationship of [first current density]> [second current density]. That is, in the first buried copper plating step, a high current density is used to form a surface having excellent adhesion of plated copper to be subsequently formed thereon. Then, on the copper plating layer formed in the first embedded copper plating step, a copper plating layer that grows uniformly in the second embedded copper plating step using a lower current density is used in order to approach the uniform plating conditions. Form.

At this time, it is preferable that the first buried copper plating step is copper plating using a current density in a range of 1 A / dm ^{2 to} 5 A / dm ² . Here, when the current density of the first buried copper plating step is less than 1 A / dm ² , the surface is not a surface with excellent adhesion of the plated copper to be subsequently formed thereon, and the first buried copper plating step is performed. The significance of setting disappears. On the other hand, when the current density of the first embedded copper plating step exceeds 5 A / dm ² , the surface of the copper plating layer becomes too rough, and the surface state of the copper plating layer formed in the second embedded copper plating step is Since it becomes coarse, it is not preferable.

  Further, the first buried copper plating process may be a multi-stage plating process including a plurality of sub plating processes. That is, when the first buried copper plating step is considered to be a step of setting a high current, energization with a high current is performed in a plurality of times. For example, when energization for 10 seconds at a high current is continuously performed, current concentration occurs in the uneven portions of the formed plating layer, and abnormal precipitation portions are easily formed. However, when energization with the same high current for 10 seconds is repeated 5 times every 2 seconds, the surface of the formed plating layer is obtained as a surface having uniform and fine irregularities without an abnormal precipitation portion. Therefore, the first embedded copper plating process is preferably a multi-stage plating process including a plurality of sub plating processes.

Here, in the sub-plating step, a current density in the range of 1 A / dm ^{2 to} 5 A / dm ² used in the first buried copper plating step is used. This is because of the same reason as described above. And it is preferable to provide at least one no-energization time of 1 second to 600 seconds even between the plurality of sub-plating steps. The meaning of providing this non-energization time is the same as described above.

  In the first embedded copper plating step described above, it is preferable to perform embedded copper plating for a thickness of 0.3 μm to 5 μm. Even if copper plating with a thickness of less than 0.3 μm is performed in the first embedded copper plating step, a copper plating surface having excellent adhesion of the plated copper formed later in the second embedded copper plating step is formed on the copper plating surface. Cannot be formed. On the other hand, if copper plating with a thickness exceeding 5 μm is performed in the first embedded copper plating step, the surface of the copper plating layer becomes rough, and the plated copper formed later in the second embedded copper plating step The buried copper plating surface becomes rough, which is not preferable.

In the second embedded copper plating step performed after the first embedded copper plating step described above, the embedded copper plating is preferably performed using a current density in the range of 0.5 A / dm ^{2 to} 4 A / dm ² . Here, when the current density of the second embedded copper plating step is less than 0.5 A / dm ² , the deposition rate of copper becomes slow, and the significance of using the electrolytic copper plating method is lost and industrially required. Not satisfied with productivity. On the other hand, if the current density in the second embedded copper plating step exceeds 4 A / dm ² , the deposition rate of copper is too high, and the embedded copper plating surface becomes rough, which is not preferable.

Printed wiring board according to the present invention: The printed wiring board according to the present invention is obtained by performing embedded copper plating on through holes and / or via holes using the embedded copper plating method for manufacturing printed wiring boards described above. It is a feature. Therefore, there is no special limitation regarding the number of constituent layers of the printed wiring board, the material, the size, the type of copper foil used, the thickness of the copper foil, and the like. However, as described above, a printed wiring board including three or more circuit layers is a target.

  In this example, the results shown in Table 1 below show the results of eight types of buried copper plating in a 100 μm diameter blind via hole provided by laser drilling on a double-sided printed wiring board. Here, a blind via hole shape having a diameter of 100 μm was formed by a carbon dioxide laser from one side of the double-sided printed wiring board. Then, in order to impart conductivity to the inner peripheral wall of the blind via hole, electroless copper plating is performed by performing alkali degreasing, conditioning, catalyzing (Sn—Pd colloid), and accelerator pretreatment, and a thickness of 0.3 μm. The electroless copper plating layer was formed as a conductive film.

  Then, buried copper plating was performed in the blind via hole by the process shown in Table 1 below. For acid degreasing in Table 1, Melplate PC-316 manufactured by Meltex Co., Ltd. was used. For the activation treatment, a diluted sulfuric acid solution (room temperature) having a sulfuric acid concentration of 10 wt% was used. A benzotriazole solution having a concentration of 10 wt% was used for rust prevention. And in the 1st embedding copper plating process and the 2nd embedding copper plating process, copper sulfate 50g / l, free sulfuric acid 70g / l, chloride ion 50ppm, and containing sulfuric acid copper plating solution were used.

Then, using a current density of 2.0 A / dm ² as the current density of the first embedded copper plating process and 1.5 A / dm ² as the current density of the second embedded copper plating process, a total copper layer of 25 μm thickness is obtained. It was deposited in the blind via hole. The non-energization time between the first embedded copper plating step and the second embedded copper plating step was 10 seconds. Furthermore, when the first embedded copper plating process is constituted by a plurality of sub-plating processes, a non-energization time of 5 seconds is provided even between the sub-plating processes.

  In Table 2 below, in correspondence with eight types of buried copper plating conditions, the buried copper plating surface of the blind via hole and the position of the outer layer surface of the printed wiring are shifted in the depth direction (in Table 2, simply “gap” At the same time. In addition, eight types of samples obtained here are shown as Sample A to Sample H. And the photograph which observed the cross section of the blind via hole obtained in this Example with the metallographic microscope in FIGS. 1-8 is shown. It is clearly shown that the gap is indicated by an arrow in the drawing, but the width of the arrow does not indicate the exact gap length.

Comparative example

  In this comparative example, the first copper plating step of the example was omitted, and the blind via hole was embedded in the copper plating only in the second embedded copper plating step. The results are summarized in Table 2 so that they can be compared with the examples. FIG. 9 shows a photograph of the cross section of the blind via hole obtained in this comparative example observed with a metal microscope. It should be noted that the magnification of FIG. 9 is slightly different from that of FIGS.

Comparison between Examples and Comparative Examples: As can be seen from Table 2 above, the gaps of Sample A to Sample H in the Examples are all 5 μm or less. On the other hand, the comparative sample has a value exceeding 5 μm. That is, it is better to perform electrolytic buried copper plating of the blind via hole separately in the first copper plating step and the second buried copper plating step than to perform as one electrolytic buried copper plating, It can be said that the buried state can be obtained.

  The embedded copper plating method for manufacturing a printed wiring board according to the present invention includes the first embedded copper plating process and the second embedded copper plating process, but the same copper plating solution can be used, and the process is as follows. Can be shortened. Therefore, it is possible to design the buried copper plating production line as one line, and the production equipment cost and the management cost can be reduced. In addition, the printed wiring board obtained by the buried copper plating method for manufacturing the printed wiring board can easily align the buried copper plating surface of the through hole and via hole with the position of the outer layer surface of the printed wiring. Can form a buried state of 5 μm or less, so that the adhesion of an etching resist to be formed later is good and suitable for forming a fine pitch circuit. Furthermore, since there are few depressions in the through holes and via holes, it becomes easy to use the buried copper plating surfaces of the through holes and via holes as component mounting lands.

It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the buried copper plating method for manufacturing a printed wiring board according to the present invention (Sample A). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the embedded copper plating method for printed wiring board manufacture concerning this invention (sample B). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the embedded copper plating method for manufacturing a printed wiring board according to the present invention (Sample C). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the burying copper plating method for printed wiring board manufacture concerning this invention (sample D). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the burying copper plating method for printed wiring board manufacture concerning this invention (sample E). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the burying copper plating method for printed wiring board manufacture concerning this invention (sample F). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the burying copper plating method for printed wiring board manufacture concerning this invention (sample G). It is a metal-microscope observation photograph of the cross section of the blind via hole obtained by applying the embedded copper plating method for printed wiring board manufacture concerning this invention (sample H). It is a metal-microscope observation photograph of the cross section of the blind via hole of the comparative sample obtained in the comparative example.

Claims (10)

In the buried copper plating method of burying the inside of a via hole or a through hole provided with a conductive film by an electroplating method,
A two-stage plating process comprising a first embedded copper plating process and a second embedded copper plating process is provided, and a copper plating solution having the same composition is used in the first embedded copper plating process and the second embedded copper plating process. A buried copper plating method for producing a printed wiring board. 2. The embedded copper plating method for producing a printed wiring board according to claim 1, wherein the copper plating solution uses a copper plating solution having a liquid temperature of 20 ° C. to 30 ° C. and a copper concentration of 30 g / L or more. 3. The embedded wiring for manufacturing a printed wiring board according to claim 1, wherein a non-energization time of 1 second to 600 seconds is provided between the first embedded copper plating step and the second embedded copper plating step. 4. Copper plating method. The printed wiring according to any one of claims 1 to 3, wherein the first embedded copper plating step performs embedded copper plating using a current density larger than a current density used in the second embedded copper plating step. Embedded copper plating method for plate manufacturing. 5. The printed wiring board manufacturing method according to claim 1, wherein the first embedded copper plating step is copper plating using a current density in a range of 1 A / dm ^{2 to} 5 A / dm ² . Embedded copper plating method. 6. The print according to claim 1, wherein the first embedded copper plating step includes a plurality of sub-plating steps using a current density in a range of 1 A / dm ^{2 to} 5 A / dm ^2. Embedded copper plating method for wiring board manufacture. The embedded copper plating method for manufacturing a printed wiring board according to claim 6, wherein at least one non-energization time of 1 second to 600 seconds is provided between the plurality of sub-plating steps. The embedded copper plating method for producing a printed wiring board according to any one of claims 1 to 7, wherein the first embedded copper plating step performs copper plating for a thickness of 0.3 to 5 µm. The embedded wiring for printed wiring board production according to any one of claims 1 to 7, wherein the second embedded copper plating step uses a current density in a range of 0.5 A / dm ^{2 to} 4 A / dm ^2. Copper plating method. A printed wiring board, wherein embedded copper plating is applied to a through hole and / or a via hole using the embedded copper plating method for producing a printed wiring board according to any one of claims 1 to 9.