CN114551563A - Nucleation layer structure, semiconductor device and manufacturing method of nucleation layer structure - Google Patents

Nucleation layer structure, semiconductor device and manufacturing method of nucleation layer structure Download PDF

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Publication number
CN114551563A
CN114551563A CN202011335959.2A CN202011335959A CN114551563A CN 114551563 A CN114551563 A CN 114551563A CN 202011335959 A CN202011335959 A CN 202011335959A CN 114551563 A CN114551563 A CN 114551563A
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nucleation
nucleation layer
layer
layer structure
layers
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张晖
张燕飞
钱洪途
孔苏苏
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Dynax Semiconductor Inc
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Dynax Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

The present application provides a nucleation layer structure, a semiconductor device, and a method of manufacturing the nucleation layer structure, the nucleation layer structure including: forming at least two first nucleation layers and at least two second nucleation layers on the substrate layer; the first nucleation layer and the second nucleation layer are alternately arranged at intervals, and the substrate layer is contacted with the first nucleation layer; the second nucleation layer is doped with metal impurities including a metal that can form positive ions. The multilayer structure is formed by intermittently supplying ammonia gas, and metal compound metal impurities are doped when ammonia gas is not supplied. Therefore, the pre-reaction of trimethylaluminum and ammonia gas can be reduced, and metal positive ions are arranged in the nucleation layer structure, so that the influence of deep-level holes in the nucleation layer structure on two-dimensional electron gas can be reduced while the crystal quality of the nucleation layer structure can be improved.

Description

Nucleation layer structure, semiconductor device and manufacturing method of nucleation layer structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a nucleation layer structure, a semiconductor device, and a method for manufacturing the nucleation layer structure.
Background
The semiconductor material gallium nitride has been a research hotspot at present due to the characteristics of large forbidden bandwidth, high electron saturation drift velocity, high breakdown field strength, good heat conductivity and the like. Gallium nitride materials are more suitable than silicon and gallium arsenide for the fabrication of High temperature, High frequency, High voltage and High power devices, such as High Electron Mobility Transistors (HEMTs), and thus gallium nitride-based electronic devices have a promising application prospect.
HEMT devices perform very well in high frequency and high power applications, but there are problems of large thermal mismatch and lattice mismatch between the substrate and the epitaxial layer, which results in large stress generated during the growth of the epitaxial layer. In some prior art techniques, lattice mismatch is mitigated by growing a high temperature AlN nucleation layer between the substrate layer and the GaN epitaxial layer. However, the AlN nucleation layer continuously grown also has a large stress, which causes the residual stress to deform the epitaxial layer during the GaN epitaxial growth process, resulting in a decrease in uniformity and a negative effect on the reliability of the device. Moreover, during the growth of the high-temperature AlN nucleation layer, the pre-reaction between trimethylaluminum (TMAl) and ammonia (NH3) is also accelerated, thereby deteriorating the quality of AlN itself. In addition, impurities such as O atoms, unintentionally doped impurities, N vacancies, and the like are introduced more or less in the heteroepitaxy process as main sources of background carriers, and these impurities or defects introduced from the AlN layer form various energy levels, and when the HEMT device is in an operating state, these energy levels trap two-dimensional electron gas in the device channel, which causes degradation of the current, output power, and other properties of the device, and seriously deteriorates the electrical properties of the device.
Disclosure of Invention
In order to overcome the above-mentioned deficiencies in the prior art, it is an object of the present application to provide a nucleation layer structure comprising:
forming at least two first nucleation layers and at least two second nucleation layers on the substrate layer; the first nucleation layer and the second nucleation layer are alternately arranged at intervals, and the substrate layer is in contact with the first nucleation layer;
the second nucleation layer is doped with metal impurities including a metal that can form positive ions.
In one possible implementation, the metal doped in the second nucleation layer is iron or magnesium.
In a possible implementation manner, the concentration of the doped metal impurities in the second nucleation layer is in the order of 1e14 per cubic centimeter, and the concentration of the doped metal impurities in the last second nucleation layer farthest from the substrate layer side is lower than that of the doped metal impurities in the first second nucleation layer closest to the substrate layer.
In one possible implementation, the number of the first nucleation layers and the number of the second nucleation layers are equal, and the thickness of the second nucleation layers is greater than the thickness of the first nucleation layers.
In one possible implementation, the nucleation layer structure has a total thickness of 70 to 110 nanometers.
In one possible implementation, the difference in thickness between the at least two second nucleation layers is less than or equal to 10 nm.
In one possible implementation, the difference in thickness between the at least two first nucleation layers is less than or equal to 10 nm.
Another object of the present application is to provide a semiconductor device, including:
a substrate layer;
the present application formed on the substrate layer provides the nucleation layer structure;
a buffer layer formed on the nucleation layer structure;
a channel layer formed on the buffer layer;
a barrier layer formed on the channel layer;
and an electrode formed on the barrier layer.
It is another object of the present application to provide a method of fabricating a nucleation layer structure, the method comprising:
sequentially laminating a plurality of nucleation layers on a substrate layer in a mode of intermittently supplying ammonia gas to trimethylaluminum, forming a first nucleation layer by the trimethylaluminum and the ammonia gas when the ammonia gas is supplied, and doping metal impurities into the trimethylaluminum to form a second nucleation layer when the ammonia gas is not supplied;
and the first nucleation layer is formed on the substrate layer, and the metal doped in the second nucleation layer is metal capable of forming positive ions.
In one possible implementation manner, the step of doping the trimethylaluminum with metal impurities in the absence of ammonia gas comprises:
the trimethylaluminum is doped with a metal impurity containing an iron element or a magnesium element in the absence of ammonia gas.
Compared with the prior art, the method has the following beneficial effects:
embodiments of the present application provide a nucleation layer structure, a semiconductor device, and a method of manufacturing the nucleation layer structure, in which a multi-layer structure is formed by intermittently supplying ammonia gas when a nucleation layer is grown, and metal impurities are doped when ammonia gas is not supplied. Therefore, metal positive ions can be contained in the nucleation layer structure, so that the crystal quality of the nucleation layer can be improved, and the influence of deep-level holes in the nucleation layer structure on two-dimensional electron gas can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram of a nucleation layer structure provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating the growth of a nucleation layer structure according to an embodiment of the present disclosure;
FIG. 4 is a second schematic view illustrating the growth of a nucleation layer structure according to an embodiment of the present disclosure;
fig. 5 is a schematic view of a first second nucleation layer and a last second nucleation layer provided in an embodiment of the present application;
FIG. 6 is a schematic thickness diagram of a first nucleation layer and a second nucleation layer provided in accordance with an embodiment of the present application;
fig. 7 is a schematic flow chart illustrating a method for fabricating a nucleation layer structure according to an embodiment of the present disclosure.
Icon: 10-a substrate layer; 20-a nucleation layer structure; 21-a first nucleation layer; 22-a second nucleation layer; 30-a buffer layer; 40-a channel layer; 50-barrier layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are used only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In order to form high quality semiconductor epitaxial structures, it is desirable to improve the quality of the crystal in the nucleation layer. In some existing schemes, a nucleation method for forming AlN at high temperature is mainly adopted, the growth temperature of the nucleation layer is controlled to be about 1000 ℃, the surface migration force of Al atoms can be improved, the density of AlN nucleation islands is improved, a good foundation is laid for a 3D merging process in the subsequent buffer layer growth process, and therefore the crystal quality is improved.
However, the high temperature environment may aggravate the pre-reaction between TMAl and NH3, thereby deteriorating the quality of AlN and further affecting the growth of the subsequent buffer layer. On the other hand, many defects such as O atoms and unintentionally doped impurities, and N vacancies are present in the AlN nucleation layer to form various energy levels. When the semiconductor device works, the holes of the deep energy level can trap two-dimensional electron gas in the channel layer, so that the output power of the device is influenced, and the performance of the device is reduced.
In view of the above, the present embodiments provide a nucleation layer structure, a semiconductor device, and a method for manufacturing the nucleation layer structure, in which ammonia gas is intermittently added during the growth of the nucleation layer, and metal impurities are doped without supplying ammonia gas, so that the influence of deep level holes in the nucleation layer on two-dimensional electron gas can be reduced while the crystal quality of the nucleation layer is improved. The scheme provided by the present embodiment is explained in detail below.
Referring to fig. 1, fig. 1 is a schematic view of a nucleation layer structure provided in this embodiment, the nucleation layer structure may be formed on a substrate layer 10, and the substrate layer 10 may include one or a combination of more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitride.
The nucleation layer structure 20, which may comprise a III-V compound based semiconductor material, includes at least two first nucleation layers 21 and at least two second nucleation layers 22. The first nucleation layers 21 and the second nucleation layers 22 are alternately arranged at intervals, and the first nucleation layer 21 is formed on the substrate layer 10 and contacts the substrate layer 10. The second nucleation layer 22 is doped with metal impurities including a metal that can form positive ions. For example, the first nucleation layer 21 may be aluminum nitride AlN, and the second nucleation layer 22 may be metal-doped AlN.
In the present embodiment, referring to fig. 2, on the basis of the nucleation layer structure 20 provided in the present embodiment, a buffer layer 30, a channel layer 40, a barrier layer 50 and other structures may be sequentially formed. The nucleation layer structure 20 provided in this embodiment can reduce the stress between the substrate layer 10 and the buffer layer 30 due to lattice mismatch and thermal expansion coefficient mismatch.
In this embodiment, when the nucleation layer structure 20 is grown, NH3 may be intermittently supplied to TMAl multiple times, and the TMAl may be doped with metal impurities when NH3 is not supplied.
For example, referring to fig. 3, NH3 may be supplied to TMAl in addition to the substrate layer 10, and AlN formed by rapid reaction of TMAl and NH3 at a high temperature may be used as the first nucleation layer 21. And then the second nucleation layer 22 formed when metal impurities are doped in TMAl without supplying NH 3. Referring to fig. 4, the formation of the first nucleation layer 21 and the second nucleation layer 22 may be continued by intermittently supplying NH3 and doping metal impurities.
For the first nucleation layer 21 directly grown on the substrate layer 10, which provides nucleation centers having the same crystal orientation as the substrate layer 10, direct contact between the buffer layer 30 and the substrate layer 10 is avoided, thereby avoiding mismatch stress due to lattice mismatch between the buffer layer 30 and the substrate layer 10 and stress due to thermal expansion coefficient mismatch. Therefore, the overall quality of the crystal can be improved, and the structural stability of the whole semiconductor device is improved.
For the first nucleation layer 21 not directly grown on the substrate layer 10 (i.e. the first nucleation layer 21 grown on the second nucleation layer 22), this is mainly because of the cyclic (loop) type growth used to further relieve some residual stress. Because NH3 is supplied intermittently, the pre-reaction of TMAl and NH3 under a high-temperature environment is reduced, so that the merging mode and the 2D growth mode of the AlN nucleation island are enhanced, an AlN layer with better surface appearance and crystal quality is obtained, and a vital role is played for the subsequent growth of GaN on the AlN layer.
Each of the second nucleation layers 22 is formed by doping TMAl with a metal impurity without supplying NH 3.
The strong adhesion and weak mobility of Al atoms results in slower lateral growth of AlN, forming high density 3D islands due to the absence of NH 3. And thus impurity atoms (such as oxygen atoms) under the substrate diffuse upward to form shallow donors, a buried charge layer is formed between the AlN nucleation layer structure 20 and the buffer layer 30 to form a leakage path, and two-dimensional electron gas in the channel layer 40 is trapped when the semiconductor device is in operation, thereby affecting the output power of the device and causing the performance of the device to be degraded.
Therefore, in this embodiment, when the second nucleation layer 22 is grown, TMAl is doped with a metal impurity, and a metal element in the metal impurity can form a positive valence metal ion. Since the energy level of the positive valence metal ions is relatively shallow compared to the deep level holes (e.g., nitrogen holes), the speed of releasing electrons is also relatively fast, so that electrons trapped by the deep level holes (e.g., nitrogen holes) can be reduced, a recombination center is played, the lifetime of carriers is reduced, and the mobility of background carriers is reduced.
Based on the above design, the nucleation layer structure 20 provided in this embodiment forms the first nucleation layer 21 and the second nucleation layer 22 alternately spaced by intermittently supplying NH3 and doping metal impurities when ammonia gas is not supplied, and the influence of deep-level holes in the nucleation layer structure 20 on the two-dimensional electron gas can be reduced due to the presence of positive metal ions in the second nucleation layer 22.
Optionally, in some possible implementations, the metal doped in the second nucleation layer 22 is iron or magnesium. For example, ferrocene or dimocene may be doped into TMAl without supplying NH3 during the growth of the second nucleation layer 22, so that the second nucleation layer 22 has iron or magnesium as a metal impurity.
Optionally, in some possible implementations, the concentration of the metal impurity doped in the second nucleation layer 22 is on the order of 1e14 per cubic centimeter. By doping the metal element with higher concentration at intervals in layers, the influence of the memory effect of the doped metal element on the electrical performance of the device can be reduced.
Optionally, in some possible implementations, the concentration of the doped metal impurity in the last second nucleation layer farthest from the substrate layer 10 is lower than the concentration of the doped metal impurity in the first second nucleation layer closest to the substrate layer 10. For example, referring to fig. 5, in at least two of the second nucleation layers, the second nucleation layer 22A is a first second nucleation layer closest to the substrate layer 10, the second nucleation layer 22X is a last second nucleation layer farthest from the substrate layer 10, and a concentration of the metal impurity doped in the second nucleation layer 22A is greater than a concentration of the metal impurity doped in the second nucleation layer 22X.
Optionally, in some possible implementations, the number of the first nucleation layers 21 and the number of the second nucleation layers 22 are equal, and the thickness of the second nucleation layers 22 is greater than the thickness of the first nucleation layers 21. For example, referring to fig. 6, the thickness of the first nucleation layer 21 is d1, the thickness of the second nucleation layer 22 is d2, and d2> d 1.
In this way, for the second nucleation layer 22, the increase in thickness may result in an increase in hall mobility in the heterojunction formed with the second nucleation layer 22, and a decrease in background carrier concentration, providing some positive assistance for the subsequent realization of the higher resistivity buffer layer 30(GaN layer).
Optionally, in the present embodiment, the total thickness of the nucleation layer structure 20 is 70 to 110nm, and may be 70nm, 80nm, 90nm, 100nm, 110nm, for example. For example, the nucleation layer structure 20 may include two first nucleation layers 21 and two second nucleation layers 22, the total thickness of the entire nucleation layer structure 20 may be about 80nm, the thickness of the first nucleation layer 21 may be about 15nm, and the thickness of the second nucleation layer 22 may be about 25 nm; for example, the total thickness of the nucleation layer structure 20 may be about 100nm, and the thickness of the second nucleation layer 22 may be about 30 nm.
The thicknesses of the respective first nucleation layers 21 may be substantially equal to each other, and the difference may not be too large, for example, the difference in thickness between the respective first nucleation layers 21 is 10nm or less. The thicknesses of the respective second nucleation layers 22 may be substantially equal to each other, and the difference may not be too large, for example, the difference in thickness between the respective second nucleation layers 22 is 10nm or less.
The present embodiment further provides a semiconductor device, which includes a substrate layer 10, a nucleation layer structure 20, a buffer layer 30, a channel layer 40, and a barrier layer 50, wherein the nucleation layer structure 20 is the nucleation layer structure 20 provided in the present embodiment, and details thereof are not repeated herein.
The buffer layer 30 is formed on the nucleation layer structure 20, and the buffer layer 30 mainly functions to adhere to a semiconductor material layer to be grown next and protect a substrate material from being invaded by some metal ions. Meanwhile, the leakage current can be reduced and the pinch-off effect can be achieved. In this embodiment, the material of the buffer layer 30 may be a group III nitride material such as AlGaN, GaN, or AlGaInN. In this embodiment, the buffer layer 30 is taken as a GaN material as an example.
The channel layer 40 is formed on a side of the buffer layer 30 away from the nucleation layer structure 20, and the material of the channel layer 40 may be nitride, including at least one of GaN, AlN, InAlN, AlGaN, InAlGaN, or other semiconductor materials. The channel layer 40 mainly functions to provide a channel for two-dimensional electron gas, and oxygen atoms with reasonable concentration are arranged in the channel layer 40, so that the scattering effect of impurities generated by ionization of the oxygen atoms on the two-dimensional electron gas is reduced, the mobility of the two-dimensional electron gas is ensured, and the stable performance of a semiconductor device is ensured. In the present embodiment, the channel layer 40 is made of GaN material as an example.
The barrier layer 50 is formed on the channel layer 40, the barrier layer 50 may be made of a material including nitride, for example, at least one of AlN, InAlN, AlGaN, InAlGaN, or other semiconductor material, and the main function of the barrier layer 50 is to form a two-dimensional electron gas between the barrier layer 50 and the channel layer 40. In the present embodiment, the barrier layer 50 is made of AlGaN.
Referring to fig. 7, the present embodiment further provides a method for manufacturing a nucleation layer structure, which includes the following steps.
And step S110, sequentially laminating a plurality of nucleation layers on a substrate layer in a mode of intermittently supplying ammonia gas to trimethylaluminum, forming a first nucleation layer by the trimethylaluminum and the ammonia gas when the ammonia gas is supplied, and doping metal impurities into the trimethylaluminum to form a second nucleation layer when the ammonia gas is not supplied.
In this embodiment, the nucleation layer structure formed by the above method can be referred to the structure shown in fig. 1, and will not be described herein.
Alternatively, in some possible implementations, the metal impurity doped in the second nucleation layer 22 may be a compound including iron (Fe) or magnesium (Mg). For example, the metal impurity may be a magnesium metallocene (CP2Fe) or a magnesium metallocene (CP2 Mg).
In summary, embodiments of the present application provide a nucleation layer structure, a semiconductor device, and a method for manufacturing the nucleation layer structure, in which a multi-layer structure is formed by intermittently supplying ammonia gas when growing a nucleation layer, and metal impurities are doped when ammonia gas is not supplied. In this way, metal positive ions can be provided in the nucleation layer structure, so that the influence of deep-level holes in the nucleation layer structure on the two-dimensional electron gas is reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and all such changes or substitutions are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A nucleation layer structure, comprising:
forming at least two first nucleation layers and at least two second nucleation layers on the substrate layer; the first nucleation layer and the second nucleation layer are alternately arranged at intervals, and the substrate layer is in contact with the first nucleation layer;
the second nucleation layer is doped with metal impurities including a metal that can form positive ions.
2. The nucleation layer structure of claim 1 wherein the metal doped in the second nucleation layer is iron or magnesium.
3. A nucleation layer structure according to claim 1 wherein the concentration of metal impurities doped in the second nucleation layer is in the order of 1e14 per cubic centimeter and the concentration of metal impurities doped in the last second nucleation layer furthest from the substrate layer side is lower than the concentration of metal impurities doped in the first second nucleation layer closest to the substrate layer.
4. The nucleation layer structure of claim 1 wherein the number of first nucleation layers and the number of second nucleation layers are equal and the thickness of the second nucleation layers is greater than the thickness of the first nucleation layers.
5. The nucleation layer structure of claim 1 wherein the overall thickness of the nucleation layer structure is from 70 to 110 nanometers.
6. The nucleation layer structure of claim 1 wherein the difference in thickness between the at least two second nucleation layers is 10nm or less.
7. The nucleation layer structure of claim 1 wherein the difference in thickness between the at least two first nucleation layers is 10nm or less.
8. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate layer;
the nucleation layer structure of any of claims 1-7 formed on the substrate layer;
a buffer layer formed on the nucleation layer structure;
a channel layer formed on the buffer layer;
a barrier layer formed on the channel layer;
and an electrode formed on the barrier layer.
9. A method of fabricating a nucleation layer structure, the method comprising:
sequentially laminating a plurality of nucleation layers on a substrate layer in a mode of intermittently supplying ammonia gas to trimethylaluminum, forming a first nucleation layer by the trimethylaluminum and the ammonia gas when the ammonia gas is supplied, and doping metal impurities into the trimethylaluminum to form a second nucleation layer when the ammonia gas is not supplied;
and the first nucleation layer is formed on the substrate layer, and the metal doped in the second nucleation layer is metal capable of forming positive ions.
10. The method of claim 9, wherein the step of doping trimethylaluminum with metal impurities in the absence of ammonia gas comprises:
doping the trimethyl aluminum with metal impurities containing iron element or magnesium element when ammonia gas is not supplied.
CN202011335959.2A 2020-11-25 2020-11-25 Nucleation layer structure, semiconductor device and manufacturing method of nucleation layer structure Pending CN114551563A (en)

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WO2023231566A1 (en) * 2022-05-30 2023-12-07 湖南三安半导体有限责任公司 Semiconductor epitaxial structure and preparation method therefor, and semiconductor device
WO2023241593A1 (en) * 2022-06-16 2023-12-21 华为技术有限公司 Radio frequency semiconductor device, electronic device, and preparation method for radio frequency semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023231566A1 (en) * 2022-05-30 2023-12-07 湖南三安半导体有限责任公司 Semiconductor epitaxial structure and preparation method therefor, and semiconductor device
WO2023241593A1 (en) * 2022-06-16 2023-12-21 华为技术有限公司 Radio frequency semiconductor device, electronic device, and preparation method for radio frequency semiconductor device

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