CN114531134B - Method and structure for chip-scale packaging of thin film filter - Google Patents

Method and structure for chip-scale packaging of thin film filter Download PDF

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CN114531134B
CN114531134B CN202210427874.XA CN202210427874A CN114531134B CN 114531134 B CN114531134 B CN 114531134B CN 202210427874 A CN202210427874 A CN 202210427874A CN 114531134 B CN114531134 B CN 114531134B
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supporting
wafer
bulges
bulge
chip
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CN114531134A (en
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不公告发明人
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Shenzhen Newsonic Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/64—Filters using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

The invention provides a method and a structure for chip scale packaging of a thin film filter. The method comprises the steps of providing a wafer bottom lining to be packaged, and arranging a wafer mounting groove with a plurality of bulges on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion; utilizing a first supporting bulge and a second supporting bulge to flip-chip a chip wafer of the thin film filter in the wafer mounting groove, and establishing a metal conductor connection relation between the chip wafer and a wafer bottom lining to be packaged; arranging a plastic packaging layer on the chip wafer for plastic packaging, wherein the upper surface of the metal salient point of the chip wafer is exposed out of the upper surface of the plastic packaging layer; and a sealing and conductive connecting structure is arranged on the plastic packaging layer.

Description

Method and structure for chip-scale packaging of thin film filter
Technical Field
The invention provides a method and a structure for chip-scale packaging of a thin film filter, belonging to the technical field of thin film filters.
Background
At present, a System in Package System-in-Package method for a plurality of chips includes a WLP (Wafer Level Package) packaging method in which a plurality of chips are mounted on the same Package substrate and are electrically interconnected Through Wire Bonding metal Wire Bonding or Package substrate wiring, or the chips are mounted on a Wafer and are electrically interconnected to the outside Through Silicon Vias (TSVs) on the back of the Wafer, and the like. In addition, in the process of miniaturization, the problem of poor filter performance is caused by the poor consumption of the transverse vibration mode due to the change of the packaging structure or the over-thinning treatment of a part of the layer body.
Disclosure of Invention
The invention provides a method and a structure for chip-scale packaging of a thin film filter, which are used for solving the problems of poor performance of the filter caused by overlarge thickness and incomplete consumption of transverse vibration waves of the conventional packaging structure, and adopt the following technical scheme:
a method for thin film filter chip scale packaging, the method comprising:
providing a wafer bottom lining to be packaged, and arranging a wafer mounting groove with a plurality of bulges on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion;
utilizing a first supporting bulge and a second supporting bulge to flip-chip a chip wafer of the thin film filter in the wafer mounting groove, and establishing a metal conductor connection relation between the chip wafer and a wafer bottom lining to be packaged;
arranging a plastic packaging layer on the chip wafer for plastic packaging, wherein the upper surface of the metal salient point of the chip wafer is exposed out of the upper surface of the plastic packaging layer;
and arranging a sealing and conductive connecting structure on the plastic packaging layer.
Further, a wafer mounting groove with a plurality of protrusions is arranged on the wafer substrate to be packaged, and the wafer mounting groove comprises:
obtaining a wafer bottom lining to be packaged;
planning a corresponding mounting position and a corresponding mounting area of the chip wafer on the to-be-packaged wafer bottom lining according to the size of the chip wafer to be packaged;
laser engraving is carried out in the mounting area in a laser engraving mode according to the positions and the sizes of the first supporting bulges, the second supporting bulges and the spacing bulges to form an engraving pattern;
and etching according to the imprinting pattern, wherein the bottom surface of the groove on the wafer substrate to be packaged is provided with a first supporting bulge, a second supporting bulge and a wafer mounting groove with interval bulges.
Further, the first supporting protrusion comprises two combined first supporting protrusions and a free-standing first supporting protrusion; each combined first supporting bulge and each combined second supporting bulge are combined for use; the independent first supporting bulge is used independently;
the two combined first supporting bulges are respectively arranged in a circular mounting groove at one side close to the groove wall of the wafer mounting groove; the second supporting bulges are respectively arranged in the circular mounting grooves on one side of the center position, close to the wafer mounting groove, of the combined first supporting bulge corresponding to the combination of the second supporting bulges; a spacing bulge is arranged between the combined first supporting bulge and the second supporting bulge;
the independent first supporting bulge is arranged at the center of the wafer mounting groove.
Furthermore, the first supporting bulges and the spacing bulges adopt an isosceles trapezoid-shaped bulge structure; the second supporting protrusion is of an isosceles trapezoid protrusion structure with a side waist wall provided with an inward concave guide angle; and the concave lead angle is opposite to a free-standing first supporting bulge in the first supporting bulges; wherein the angle range of the concave lead angle is 48-100 degrees.
Further, the dimensional proportion relation among the first supporting protrusion, the second supporting protrusion and the spacing protrusion is as follows:
the height dimension proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
H3<H1<H2and, in addition,
0.88H≤H2<0.93H；
0.85×[H2-0.26×（H-H2）]≤H1<H2；
0.72×[H1-0.22×（H2-H1）]≤H3<H1；
wherein H represents a side surface of the piezoelectric layer of the chip wafer facing the wafer mounting grooveThe vertical distance between the wafer mounting groove and the bottom surface of the wafer mounting groove; h1、H2And H3The height sizes of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively;
the proportion condition of the sizes of the upper bottom edges among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
D3<D1<D2and, in addition,
0.40D2≤D1≤0.59D2；
0.47D1≤D3≤0.63D1；
wherein D is1、D2And D3And D4The sizes of the upper bottom surfaces of the first supporting bulges, the second supporting bulges and the spacing bulges are correspondingly represented respectively;
the base angle proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
0.92W1≤W3≤W1；
0.84W3≤W2<W1；
wherein, W1、W2And W3The bottom angle angles of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively.
Further, flip-chip mounting of the chip wafer of the thin film filter in the wafer mounting groove using the first support bump and the second support bump includes:
arranging a first metal substrate on the upper surfaces of the first supporting bulges and the second supporting bulges;
a chip passivation layer is arranged on the surface of one side of the chip wafer, and a third metal substrate is arranged on the upper surface of the chip passivation layer;
a fourth metal substrate is arranged on the other side surface of the chip wafer, and a welding point is arranged on the fourth metal substrate; the welding points correspond to the positions of the first metal substrate on the first supporting bulge and the second supporting bulge;
and welding and fixing the third metal substrate, the first metal substrate and the welding points, so that the chip wafer is arranged in the wafer mounting groove in an inverted mode.
Further, establishing a metal conductor connection relationship between the chip wafer and the wafer substrate to be packaged includes:
a second metal substrate is arranged on the upper surface of the amorphous round mounting groove of the wafer bottom lining to be packaged;
a first conductor communicated with the second metal substrate and a third metal substrate is arranged between the second metal substrate and the third metal substrate arranged on the upper surface of the chip passivation layer;
and a plurality of metal bumps are arranged on the third metal substrate.
Further, set up sealed and electrically conductive connection structure on the plastic envelope layer, include:
laying a first packaging passivation layer at the exposed position of the nonmetal salient points on the upper surface of the plastic packaging layer;
arranging a metal layer on the upper surface of the metal bump, wherein the outer edge of the metal layer reaches the upper surface of the first packaging passivation layer;
arranging a second packaging passivation layer on the upper surface of the metal layer and the upper surface of the exposed first packaging passivation layer, and arranging a hole corresponding to the metal layer on the second packaging passivation layer at a position opposite to the metal layer;
and arranging a second conductor on the corresponding opening of the metal layer, and welding and arranging a welding ball on the second conductor.
A structure for chip scale packaging of a thin film filter comprises a wafer substrate to be packaged and a chip wafer; a wafer mounting groove with a plurality of bulges is arranged on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion; the chip wafer is arranged in the wafer mounting groove in an inverted mode; a plastic packaging layer is arranged on the chip wafer; a sealing and conductive connecting structure is arranged on the plastic packaging layer;
the first supporting bulges and the spacing bulges adopt isosceles trapezoid bulge structures; the second supporting protrusion is of an isosceles trapezoid protrusion structure with a side waist wall provided with an inward concave guide angle; and the concave lead angle is opposite to a free-standing first supporting bulge in the first supporting bulges; wherein the angle range of the concave lead angle is 48-100 degrees.
Further, the dimensional proportion relationship among the first supporting protrusion, the second supporting protrusion and the spacing protrusion is as follows:
the height dimension proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
H3<H1<H2and, in addition,
0.88H≤H2<0.93H；
0.85×[H2-0.26×（H-H2）]≤H1<H2；
0.72×[H1-0.22×（H2-H1）]≤H3<H1；
h represents the vertical distance between the surface of one side, facing the wafer mounting groove, of the piezoelectric layer of the chip wafer and the bottom surface of the wafer mounting groove; h1、H2And H3The height sizes of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively;
the proportion condition of the sizes of the upper bottom edges among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
D3<D1<D2and, in addition,
0.40D2≤D1≤0.59D2；
0.47D1≤D3≤0.63D1；
wherein D is1、D2And D3And D4The sizes of the upper bottom surfaces of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly expressed respectively;
the base angle proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
0.92W1≤W3≤W1；
0.84W3≤W2<W1；
wherein, W1、W2And W3The bottom angle angles of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively.
The invention has the beneficial effects that:
according to the method and the structure for chip-scale packaging of the thin film filter, the chip wafer is embedded into the wafer bottom lining to be packaged in a mode that the wafer mounting groove is formed in the wafer bottom lining to be packaged, and the overall thickness of the packaged chip can be reduced to the maximum extent; meanwhile, the mounting firmness between the chip wafer and the wafer bottom lining to be packaged can be effectively improved. On the other hand, the bottom thickness of the wafer substrate to be packaged is reduced due to the fact that the thickness of the wafer substrate to be packaged is greatly reduced, and therefore the transverse vibration mode of the thin-film filter cannot be completely eliminated due to the fact that the thickness of the substrate is not enough in the vibration process, and the problem of poor performance of the filter is caused. Therefore, a first supporting bulge, a second supporting bulge and a spacing bulge which are different in height and size are arranged at the bottom of the wafer mounting groove of the wafer bottom lining to be packaged; the amplitude of the vibration transverse wave is reduced and eliminated through the protrusions of the first supporting protrusion, the second supporting protrusion and the interval protrusion, the thickness of the bottom lining of the wafer to be packaged is greatly reduced, meanwhile, the influence of the vibration transverse wave on the performance of the filter is reduced to the maximum extent, and the performance of the thin film filter is improved.
Drawings
FIG. 1 is a first flow chart of the method of the present invention;
FIG. 2 is a second flow chart of the method of the present invention;
FIG. 3 is a schematic view of the structure of the present invention;
(1, a wafer substrate to be packaged; 2, a chip wafer; 3, a plastic encapsulation layer; 4, a first package passivation layer; 5, a metal layer; 6, a second package passivation layer; 7, a second conductor; 8, a solder ball; 9, a cavity; 11, a spacing bump; 12, a first support bump; 13, a second support bump; 14, a first metal substrate; 15, a second metal substrate; 16, a first conductor; 21, a fourth metal substrate; 22, a solder joint; 23, a chip passivation layer; 24, a third metal substrate; 25, a metal bump).
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
An embodiment of the present invention provides a method for chip scale packaging of a thin film filter, as shown in fig. 1, the method includes:
s1, providing a wafer substrate to be packaged, and arranging a wafer mounting groove with a plurality of bulges on the wafer substrate to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion;
s2, flip-chip mounting the chip wafer of the thin film filter in the wafer mounting groove by using the first supporting bulge and the second supporting bulge, and establishing a metal conductor connection relation between the chip wafer and the wafer substrate to be packaged;
s3, arranging a plastic packaging layer on the chip wafer for plastic packaging, wherein the upper surface of the metal salient point of the chip wafer is exposed out of the upper surface of the plastic packaging layer;
and S4, arranging a sealing and conductive connecting structure on the plastic packaging layer.
As shown in fig. 2, the step of providing a wafer mounting groove with a plurality of protrusions on the wafer substrate to be packaged includes:
s101, obtaining a wafer bottom lining to be packaged;
s102, planning a corresponding mounting position and a corresponding mounting area of a chip wafer on the wafer substrate to be packaged according to the size of the chip wafer to be packaged on the wafer substrate to be packaged;
s103, laser engraving is carried out in the mounting area in a laser engraving mode according to the positions and the sizes of the first supporting bulges, the second supporting bulges and the spacing bulges to form engraving patterns;
and S104, etching according to the imprinting pattern, and forming a wafer mounting groove with a first supporting bulge, a second supporting bulge and an interval bulge on the bottom surface of the groove on the wafer substrate to be packaged.
Specifically, the flip chip of the thin film filter is disposed in the wafer mounting groove by using a first supporting protrusion and a second supporting protrusion, including:
s201a, arranging a first metal substrate on the upper surfaces of the first supporting bulge and the second supporting bulge;
s202a, arranging a chip passivation layer on one side surface of the chip wafer, and arranging a third metal substrate on the upper surface of the chip passivation layer;
s203a, arranging a fourth metal substrate on the other side surface of the chip wafer, and arranging welding points on the fourth metal substrate; the welding points correspond to the positions of the first metal substrate on the first supporting bulge and the second supporting bulge;
and S204a, welding and fixing the third metal substrate, the first metal substrate and the welding points, and enabling the chip wafer to be arranged in the wafer mounting groove in an inverted mode.
Wherein, establishing a metal conductor connection relation between the chip wafer and the wafer substrate to be packaged comprises:
s201b, arranging a second metal substrate on the upper surface of the amorphous round mounting groove of the wafer substrate to be packaged;
s202b, arranging a first conductor communicated with the second metal substrate and a third metal substrate between the second metal substrate and the third metal substrate arranged on the upper surface of the chip passivation layer;
and S203b, arranging a plurality of metal bumps on the third metal substrate.
Set up sealed and electrically conductive connection structure on the plastic envelope layer, include:
s301, laying a first packaging passivation layer at the exposed position of the nonmetal salient points on the upper surface of the plastic packaging layer;
s302, arranging a metal layer on the upper surface of the metal bump, wherein the outer edge of the metal layer reaches the upper surface of the first packaging passivation layer;
s303, laying a second packaging passivation layer on the upper surface of the metal layer and the upper surface of the exposed first packaging passivation layer, and arranging a hole corresponding to the metal layer on the second packaging passivation layer at a position opposite to the metal layer;
and S304, arranging a second conductor on the corresponding hole of the metal layer, and welding and arranging a welding ball on the second conductor.
The working principle of the technical scheme is as follows: firstly, providing a wafer bottom lining to be packaged, and arranging a wafer mounting groove with a plurality of bulges on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion; then, a chip wafer of the thin film filter is arranged in the wafer mounting groove in an inverted mode through the first supporting bulges and the second supporting bulges, and a metal conductor connection relation is established between the chip wafer and a wafer bottom lining to be packaged; then, arranging a plastic packaging layer on the chip wafer for plastic packaging, wherein the upper surface of the metal salient point of the chip wafer is exposed out of the upper surface of the plastic packaging layer; and finally, arranging a sealing and conductive connecting structure on the plastic packaging layer.
The effect of the above technical scheme is as follows: in the method for chip-scale packaging of a thin film filter provided by the embodiment, the chip wafer is embedded into the wafer substrate to be packaged in a manner that the wafer mounting groove is formed in the wafer substrate to be packaged, so that the overall thickness of the packaged chip can be reduced to the maximum extent; meanwhile, the mounting firmness between the chip wafer and the wafer bottom lining to be packaged can be effectively improved. On the other hand, the bottom thickness of the wafer substrate to be packaged is reduced due to the fact that the thickness of the wafer substrate to be packaged is greatly reduced, and therefore the transverse vibration mode of the thin-film filter cannot be completely eliminated due to the fact that the thickness of the substrate is not enough in the vibration process, and the problem of poor performance of the filter is caused. Therefore, a first supporting bulge, a second supporting bulge and a spacing bulge which are different in height and size are arranged at the bottom of the wafer mounting groove of the wafer bottom lining to be packaged; the amplitude of the vibration transverse wave is reduced and eliminated through the protrusions of the first supporting protrusion, the second supporting protrusion and the interval protrusion, the thickness of the bottom lining of the wafer to be packaged is greatly reduced, meanwhile, the influence of the vibration transverse wave on the performance of the filter is reduced to the maximum extent, and the performance of the thin film filter is improved.
In one embodiment of the invention, the first supporting protrusion comprises two combined first supporting protrusions and a free-standing first supporting protrusion; each combined first supporting bulge and each combined second supporting bulge are combined for use; the independent first supporting bulge is used independently;
the two combined first supporting bulges are respectively arranged in a circular mounting groove at one side close to the groove wall of the wafer mounting groove; the second supporting bulges are respectively arranged in a circular mounting groove at one side of the central position of the wafer mounting groove, which is close to the combined first supporting bulge corresponding to the combination of the second supporting bulges; a spacing bulge is arranged between the combined first supporting bulge and the second supporting bulge;
the independent first supporting bulge is arranged at the center of the wafer mounting groove.
Wherein the first supporting bulges and the spacing bulges adopt an isosceles trapezoid bulge structure; the second supporting protrusion is of an isosceles trapezoid protrusion structure with a side waist wall provided with an inward concave guide angle; and the concave lead angle is opposite to a free-standing first supporting bulge in the first supporting bulges; wherein the angle range of the concave lead angle is 48-100 degrees.
The dimensional proportion relation among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
the height dimension proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
H3<H1<H2and, in addition,
0.88H≤H2<0.93H；
0.85×[H2-0.26×（H-H2）]≤H1<H2；
0.72×[H1-0.22×（H2-H1）]≤H3<H1；
h represents the vertical distance between the surface of one side, facing the wafer mounting groove, of the piezoelectric layer of the chip wafer and the bottom surface of the wafer mounting groove; h1、H2And H3The height sizes of the first supporting bulges, the second supporting bulges and the spacing bulges are correspondingly represented respectively;
the proportion condition of the sizes of the upper bottom edges among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
D3<D1<D2and, in addition,
0.40D2≤D1≤0.59D2；
0.47D1≤D3≤0.63D1；
wherein D is1、D2And D3And D4The sizes of the upper bottom surfaces of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly expressed respectively;
the base angle proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
0.92W1≤W3≤W1；
0.84W3≤W2<W1；
wherein, W1、W2And W3The bottom angle angles of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively.
The working principle and the effect of the technical scheme are as follows: the thickness of the bottom lining of the wafer to be packaged is greatly reduced, so that the thickness of the bottom lining of the wafer to be packaged is reduced, and the transverse vibration mode of the thin film filter cannot be completely eliminated due to the insufficient thickness of the bottom lining in the vibration process, so that the problem of poor performance of the filter is easily caused. Therefore, a first supporting bulge, a second supporting bulge and a spacing bulge which are different in height and size are arranged at the bottom of the wafer mounting groove of the wafer bottom lining to be packaged; the amplitude of the vibration transverse wave is reduced and eliminated through the protrusions of the first supporting protrusion, the second supporting protrusion and the interval protrusion, the thickness of the bottom lining of the wafer to be packaged is greatly reduced, meanwhile, the influence of the vibration transverse wave on the performance of the filter is reduced to the maximum extent, and the performance of the thin film filter is improved.
On the other hand, different size parameters of the first supporting protrusion, the second supporting protrusion and the spacing protrusion are set through the specific proportional relation, protrusions and cavities with different sizes and gradients can be formed on the substrate, the continuity of the solid substrate for the transverse vibration wave conduction can be reduced in the transverse vibration process, meanwhile, the continuity of the transverse vibration wave conduction is further reduced through different heights and different side surface gradients and structures of the protrusions in the transverse vibration wave conduction process, the heights and other parameters are different, so that the amplitude of the transverse vibration wave is counteracted and consumed to the maximum extent, and the influence of the transverse vibration wave on the performance of the filter is reduced.
The embodiment of the invention provides a structure for chip-scale packaging of a thin film filter, which comprises a wafer substrate to be packaged and a chip wafer, as shown in fig. 3; a wafer mounting groove with a plurality of bulges is arranged on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion; the chip wafer is arranged in the wafer mounting groove in an inverted mode; a plastic packaging layer is arranged on the chip wafer; a sealing and conductive connecting structure is arranged on the plastic packaging layer;
the first supporting bulges and the spacing bulges adopt isosceles trapezoid bulge structures; the second supporting protrusion is of an isosceles trapezoid protrusion structure with a side waist wall provided with an inward concave guide angle; and the concave lead angle is opposite to a free-standing first supporting bulge in the first supporting bulges; wherein the angle range of the concave lead angle is 48-100 degrees.
The first supporting bulge, the second supporting bulge and the spacing bulge have the following dimensional proportion relation:
the height dimension proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
H3<H1<H2and, in addition,
0.88H≤H2<0.93H；
0.85×[H2-0.26×（H-H2）]≤H1<H2；
0.72×[H1-0.22×（H2-H1）]≤H3<H1；
h represents the vertical distance between the surface of one side, facing the wafer mounting groove, of the piezoelectric layer of the chip wafer and the bottom surface of the wafer mounting groove; h1、H2And H3The height sizes of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively;
the proportion condition of the sizes of the upper bottom edges among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
D3<D1<D2and, in addition,
0.40D2≤D1≤0.59D2；
0.47D1≤D3≤0.63D1；
wherein D is1、D2And D3And D4The sizes of the upper bottom surfaces of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly expressed respectively;
the base angle proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
0.92W1≤W3≤W1；
0.84W3≤W2<W1；
wherein, W1、W2And W3The bottom angle angles of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively.
The working principle and the effect of the technical scheme are as follows: according to the structure for chip-scale packaging of the thin film filter, the chip wafer is embedded into the wafer substrate to be packaged in a mode of arranging the wafer mounting groove on the wafer substrate to be packaged, and the overall thickness of the packaged chip can be reduced to the maximum extent through the mode; meanwhile, the mounting firmness between the chip wafer and the wafer bottom lining to be packaged can be effectively improved. On the other hand, the bottom thickness of the wafer substrate to be packaged is reduced due to the fact that the thickness of the wafer substrate to be packaged is greatly reduced, and therefore the transverse vibration mode of the thin-film filter cannot be completely eliminated due to the fact that the thickness of the substrate is not enough in the vibration process, and the problem of poor performance of the filter is caused. Therefore, a first supporting bulge, a second supporting bulge and a spacing bulge which are different in height and size are arranged at the bottom of the wafer mounting groove of the wafer bottom lining to be packaged; the amplitude of the transverse vibration wave is reduced and eliminated through the protrusions of the first supporting protrusions, the second supporting protrusions and the interval protrusions, the thickness of the bottom lining of the wafer to be packaged is greatly reduced, the influence of the transverse vibration wave on the performance of the filter is reduced to the greatest extent, and the performance of the thin-film filter is improved.
Meanwhile, different size parameters of the first supporting protrusion, the second supporting protrusion and the spacing protrusion are set according to the specific proportional relation, protrusions and cavities with different sizes and slopes can be formed on the substrate, the continuity of the solid substrate for the conduction of the transverse vibration waves can be reduced in the transverse vibration process, meanwhile, the continuity of the conduction of the transverse vibration waves is further reduced through different heights and different side surface slopes and structures of the protrusions in the transverse vibration wave conduction process, the amplitude of the transverse vibration waves is offset and consumed to the maximum extent, and the influence of the transverse vibration waves on the performance of the filter is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (8)

1. A method for chip scale packaging of a thin film filter, the method comprising:
providing a wafer bottom lining to be packaged, and arranging a wafer mounting groove with a plurality of bulges on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion;
utilizing a first supporting bulge and a second supporting bulge to flip-chip a chip wafer of the thin film filter in the wafer mounting groove, and establishing a metal conductor connection relation between the chip wafer and a wafer bottom lining to be packaged;
arranging a plastic packaging layer on the chip wafer for plastic packaging, wherein the upper surface of the metal salient point of the chip wafer is exposed out of the upper surface of the plastic packaging layer;
arranging a sealing and conductive connecting structure on the plastic packaging layer;
utilize first support arch and second support arch with thin-film filter's chip wafer flip-chip sets up in the wafer mounting groove includes:
arranging a first metal substrate on the upper surfaces of the first supporting bulges and the second supporting bulges;
a chip passivation layer is arranged on the surface of one side of the chip wafer, and a third metal substrate is arranged on the upper surface of the chip passivation layer;
a fourth metal substrate is arranged on the other side surface of the chip wafer, and a welding point is arranged on the fourth metal substrate; the welding points correspond to the positions of the first metal substrates on the first supporting bulges and the second supporting bulges;
and welding and fixing the third metal substrate, the first metal substrate and the welding points, so that the chip wafer is arranged in the wafer mounting groove in an inverted mode.
2. The method as claimed in claim 1, wherein providing a wafer mounting recess with a plurality of protrusions on the wafer substrate to be packaged comprises:
obtaining a wafer bottom lining to be packaged;
planning a mounting position and a mounting area corresponding to the chip wafer on the wafer bottom lining to be packaged according to the size of the chip wafer to be packaged on the wafer bottom lining to be packaged;
laser engraving is carried out in the mounting area in a laser engraving mode according to the positions and the sizes of the first supporting bulges, the second supporting bulges and the spacing bulges to form an engraving pattern;
and etching according to the imprinting pattern, wherein the bottom surface of the groove on the wafer substrate to be packaged is provided with a first supporting bulge, a second supporting bulge and a wafer mounting groove with interval bulges.
3. The method of claim 1 or 2, wherein the first support protrusion comprises two combined first support protrusions and one free-standing first support protrusion; each combined first supporting bulge and each combined second supporting bulge are combined for use; the independent first supporting bulge is used independently;
the two combined first supporting bulges are respectively arranged in a circular mounting groove at one side close to the groove wall of the wafer mounting groove; the second supporting bulges are respectively arranged in a circular mounting groove at one side of the central position of the wafer mounting groove, which is close to the combined first supporting bulge corresponding to the combination of the second supporting bulges; a spacing bulge is arranged between the combined first supporting bulge and the second supporting bulge;
the independent first supporting bulge is arranged at the center of the wafer mounting groove.
4. The method of claim 1, wherein the first supporting protrusions and the spacing protrusions are in an isosceles trapezoid protrusion structure; the second supporting protrusion is of an isosceles trapezoid protrusion structure with a side waist wall provided with an inward concave guide angle; and the concave lead angle is opposite to a free-standing first supporting bulge in the first supporting bulges; wherein the angle range of the concave lead angle is 48-100 degrees.
5. The method according to claim 1 or 4, wherein the dimensional ratio relationship among the first supporting protrusion, the second supporting protrusion and the spacing protrusion is as follows:
the height dimension proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
H3<H1<H2and, in addition,
0.88H≤H2<0.93H；
0.85×[H2-0.26×（H-H2）]≤H1<H2；
0.72×[H1-0.22×（H2-H1）]≤H3<H1；
h represents the vertical distance between the surface of one side, facing the wafer mounting groove, of the piezoelectric layer of the chip wafer and the bottom surface of the wafer mounting groove; h1、H2And H3The height sizes of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively;
the proportion condition of the sizes of the upper bottom edges among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
D3<D1<D2and, in addition,
0.40D2≤D1≤0.59D2；
0.47D1≤D3≤0.63D1；
wherein D is1、D2And D3And D4The sizes of the upper bottom surfaces of the first supporting bulges, the second supporting bulges and the spacing bulges are correspondingly represented respectively;
the base angle proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
0.92W1≤W3≤W1；
0.84W3≤W2<W1；
wherein, W1、W2And W3The bottom angle angles of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively.
6. The method of claim 1, wherein establishing a metal conductor connection between the chip wafer and the wafer substrate to be packaged comprises:
a second metal substrate is arranged on the upper surface of the amorphous round mounting groove of the wafer bottom lining to be packaged;
a first conductor communicated with the second metal substrate and a third metal substrate is arranged between the second metal substrate and the third metal substrate arranged on the upper surface of the chip passivation layer;
and a plurality of metal bumps are arranged on the third metal substrate.
7. The method of claim 1, wherein providing a sealing and conductive connection structure on the molding layer comprises:
arranging a first packaging passivation layer at the exposed position of the nonmetal salient points on the upper surface of the plastic packaging layer;
arranging a metal layer on the upper surface of the metal bump, wherein the outer edge of the metal layer reaches the upper surface of the first packaging passivation layer;
arranging a second packaging passivation layer on the upper surface of the metal layer and the upper surface of the exposed first packaging passivation layer, and arranging a hole corresponding to the metal layer on the second packaging passivation layer at a position opposite to the metal layer;
and arranging a second conductor on the corresponding opening of the metal layer, and welding and arranging a welding ball on the second conductor.
8. A structure for chip-scale packaging of a thin film filter is characterized by comprising a wafer substrate to be packaged and a chip wafer; a wafer mounting groove with a plurality of bulges is arranged on the wafer bottom lining to be packaged; wherein the protrusions include a first support protrusion, a second support protrusion, and a spacing protrusion; the chip wafer is arranged in the wafer mounting groove in an inverted mode; a plastic packaging layer is arranged on the chip wafer; a sealing and conductive connecting structure is arranged on the plastic packaging layer;
the first supporting bulges and the spacing bulges adopt isosceles trapezoid bulge structures; the second supporting protrusion is of an isosceles trapezoid protrusion structure with an inward concave guide angle on one waist wall; and the internal concave lead-in angle is opposite to a free-standing first supporting bulge of the first supporting bulges; wherein the angle range of the concave lead angle is 48-100 degrees;
the first supporting bulge, the second supporting bulge and the spacing bulge have the following dimensional proportion relation:
the height dimension proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
H3<H1<H2and, in addition,
0.88H≤H2<0.93H；
0.85×[H2-0.26×（H-H2）]≤H1<H2；
0.72×[H1-0.22×（H2-H1）]≤H3<H1；
h represents the vertical distance between the surface of one side, facing the wafer mounting groove, of the piezoelectric layer of the chip wafer and the bottom surface of the wafer mounting groove; h1、H2And H3The height sizes of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively;
the proportion condition of the sizes of the upper bottom edges among the first supporting bulges, the second supporting bulges and the spacing bulges is as follows:
D3<D1<D2and, in addition,
0.40D2≤D1≤0.59D2；
0.47D1≤D3≤0.63D1；
wherein D is1、D2And D3And D4The sizes of the upper bottom surfaces of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly expressed respectively;
the base angle proportion conditions among the first supporting bulges, the second supporting bulges and the spacing bulges are as follows:
0.92W1≤W3≤W1；
0.84W3≤W2<W1；
wherein, W1、W2And W3The bottom angle angles of the first supporting bulge, the second supporting bulge and the spacing bulge are correspondingly represented respectively.
CN202210427874.XA 2022-04-22 2022-04-22 Method and structure for chip-scale packaging of thin film filter Active CN114531134B (en)

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CN108512523A (en) * 2017-11-06 2018-09-07 贵州中科汉天下微电子有限公司 The encapsulating method and structure of piezoelectric sound wave device
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