CN218217323U

CN218217323U - Novel CSP substrate structure

Info

Publication number: CN218217323U
Application number: CN202222536230.2U
Authority: CN
Inventors: 项明亮; 周善远; 熊安祥; 刘凯明; 高忠强
Original assignee: Zhejiang Huayuan Micro Electronics Technology Co ltd
Current assignee: Zhejiang Huayuan Micro Electronics Technology Co ltd
Priority date: 2022-08-17
Filing date: 2022-08-17
Publication date: 2023-01-03
Anticipated expiration: 2032-08-17

Abstract

The utility model provides a novel CSP substrate structure, is in including base plate, flip chip on the base plate, still including establishing weld zone on the base plate and edge the district that blocks that the weld zone edge set up, the chip bottom with the perpendicular distance that blocks the district top is less than 5um, just the chip is in projection on the base plate with the weld zone coincidence. The utility model discloses according to the supporting design welding area of chip size, make every device flip back gold ball highly reach suitable value to make the chip reduce the interval between chip and the base plate after the flip, inside the clearance that will unable infiltration chip and base plate between the resin at the tectorial membrane in-process, thereby avoid the problem that the device became invalid completely.

Description

Novel CSP substrate structure

Technical Field

The utility model relates to the field of semiconductor technology, especially a novel CSP substrate structure.

Background

With the rapid development of the semiconductor industry technology, the packaging mode of the surface acoustic wave device is from DIP packaging to SMD packaging, and then to the present CSP and WLP packaging, and the application field thereof is gradually expanded, and the miniaturization of the surface acoustic wave device is also an inevitable trend. However, with the miniaturization of surface acoustic wave devices, the film-covered packaging process of CSP packaged surface acoustic wave devices has also created new demands for the structure of the substrate. After the chip and the substrate are reversely mounted, a gap can exist between the chip and the substrate, the IDT on the surface of the chip is effectively protected from being damaged, and meanwhile, a large amount of resin can permeate into the gap between the chip and the substrate after the product is packaged by a film, so that the IDT is damaged to cause device failure.

Disclosure of Invention

The utility model aims at providing a novel CSP base plate structure to solve the problem that proposes in the background art.

The technical solution of the utility model is that: the utility model provides a novel CSP base plate structure, includes the base plate, the flip chip is in chip on the base plate, still including establishing welding area on the base plate and edge the district that blocks that the welding area edge set up, the chip bottom with the perpendicular distance that blocks the district top is less than 5umm, just the chip is in projection on the base plate with the welding area coincidence.

Preferably, the land is provided with a first placing groove in which the chip is flip-chip mounted.

Preferably, the depth of the first placing groove is 5-10um.

Preferably, the blocking area is provided with a first protrusion, and the first protrusion is arranged along the top edge of the blocking area.

Preferably, the height of the first protrusion is 5-10um.

Preferably, the welding area is provided with a second placing groove, the blocking area is provided with a second protrusion, and the height difference between the bottom of the second placing groove and the top of the second protrusion is 5-10um.

The utility model discloses beneficial effect is:

compared with the prior art, the utility model discloses according to the supporting design welding area of chip size, make every device flip back gold ball highly reach suitable value to make the chip reduce the interval between chip and the base plate after the flip, inside the clearance that will unable infiltration chip and base plate between the resin at the tectorial membrane in-process, thereby avoid the problem that the device became invalid completely.

Drawings

FIG. 1 is a schematic view of the present invention;

FIG. 2 is a cross-sectional view of a conventional flip chip and substrate;

FIG. 3 is a cross-sectional view of a conventional coated product;

FIG. 4 is a schematic structural view of embodiment 2;

FIG. 5 is a schematic structural view of embodiment 3;

Detailed Description

The present invention will be further described with reference to the following embodiments in conjunction with the accompanying drawings.

The present embodiment is only for explaining the present invention, and it is not limited to the present invention, and those skilled in the art can make modifications to the present embodiment without inventive contribution as required after reading the present specification, but all of them are protected by patent laws within the scope of the claims of the present invention.

Embodiment 1, as shown in fig. 1 to 3, a novel CSP substrate structure includes a substrate 1, a chip 2 flip-mounted on the substrate 1, a bonding pad 101 disposed on the substrate 1, and a blocking area 102 disposed along an edge of the bonding pad 101, wherein a vertical distance between a bottom of the chip 2 and a top of the blocking area 102 is less than 5um, and a projection of the chip 2 on the substrate 1 coincides with the bonding pad 101, in the bonding pad 101 of this embodiment, a pad 103, a gold ball 104, an upper copper plating 105, a via hole 106, and a lower copper plating 107 are disposed; as shown in fig. 2: after chip 2 and base plate 1 carried out the flip-chip, can have the clearance between chip 2 and the base plate 1, effectively protect 2 surperficial interdigital transducer IDT of chip not destroyed, but also have the product simultaneously and in the tectorial membrane encapsulation back, have inside a large amount of resin 7 infiltration chip 2 and the clearance between the base plate 1, cause destruction like figure 3 to interdigital transducer IDT: the IDT is destroyed by the resin 7, resulting in device failure; as shown in FIG. 1: the utility model discloses according to 2 supporting design weld zones 101 of chip size, make every device flip back gold ball highly reach suitable value to make chip 2 after the flip, reduce the interval between chip 2 and the base plate 1, inside the clearance that will unable infiltration chip 2 and base plate 1 between tectorial membrane in-process resin 7, thereby avoid the problem that the device became invalid completely.

The bonding pad 101 is provided with a first placing groove 3, and the chip 2 is flip-chip mounted in the first placing groove 3.

The depth of the first placing groove 3 is 5-10um, and preferably, the first placing groove 3 in the present embodiment can be realized by using laser etching in the welding area 101; through setting up first standing groove 3 for chip 2 falls in the height behind the first standing groove 3 of flip-chip package, thereby makes chip 2 bottom and the perpendicular distance that blocks district 102 top be less than 5um, and inside the clearance that can't permeate between chip 2 and the base plate 1 at tectorial membrane in-process resin, thereby avoid the problem of device inefficacy completely.

Embodiment 2, as shown in fig. 2-4, a novel CSP substrate structure includes a substrate 1, a chip 2 flip-mounted on the substrate 1, a bonding pad 101 disposed on the substrate 1, and a blocking area 102 disposed along an edge of the bonding pad 101, wherein a vertical distance between a bottom of the chip 2 and a top of the blocking area 102 is less than 5um, and a projection of the chip 2 on the substrate 1 coincides with the bonding pad 101, in the bonding pad 101 of this embodiment, a pad 103, a gold ball 104, an upper copper plating 105, a via hole 106, and a lower copper plating 107 are disposed; as shown in fig. 2: after chip 2 and base plate 1 flip-chip, can have the clearance between chip 2 and the base plate 1, effectively protect chip 2 surface interdigital transducer IDT not destroyed, but also have the product simultaneously and after the tectorial membrane encapsulation, have inside a large amount of resin 7 infiltration clearance between chip 2 and the base plate 1, cause destruction to interdigital transducer IDT as figure 3: the IDT is destroyed by the resin 7, resulting in device failure; as shown in FIG. 1: the utility model discloses according to 2 supporting design weld zones 101 of chip size, make every device flip back gold ball highly reach suitable value to make chip 2 after the flip, reduce the interval between chip 2 and the base plate 1, inside the clearance that will unable infiltration chip 2 and base plate 1 between tectorial membrane in-process resin 7, thereby avoid the problem that the device became invalid completely.

The barrier region 102 is provided with a first protrusion 4, and the first protrusion 4 is provided along a top edge of the barrier region 102.

The height of the first protrusion 4 is 5-10um, preferably, the first protrusion 4 in this embodiment can be realized by brushing green oil; through setting up first arch 4 for the vertical distance at chip 2 bottom and blocking area 102 top is less than 5um, and inside the clearance that the resin will unable infiltration chip 2 and base plate 1 between the tectorial membrane in-process, thereby avoided the problem of device inefficacy completely.

Embodiment 3, as shown in fig. 2, fig. 3, and fig. 5, a novel CSP substrate structure includes a substrate 1, a chip 2 flip-chip mounted on the substrate 1, a bonding pad 101 disposed on the substrate 1, and a barrier region 102 disposed along an edge of the bonding pad 101, where a vertical distance between a bottom of the chip 2 and a top of the barrier region 102 is less than 5um, and a projection of the chip 2 on the substrate 1 coincides with the bonding pad 101, and a bonding pad 103, a gold ball 104, an upper copper plating 105, a via hole 106, and a lower copper plating 107 are disposed in the bonding pad 101 in this embodiment; as shown in fig. 2: after chip 2 and base plate 1 flip-chip, can have the clearance between chip 2 and the base plate 1, effectively protect chip 2 surface interdigital transducer IDT not destroyed, but also have the product simultaneously and after the tectorial membrane encapsulation, have inside a large amount of resin 7 infiltration clearance between chip 2 and the base plate 1, cause destruction to interdigital transducer IDT as figure 3: the IDT is destroyed by the resin 7, resulting in device failure; as shown in FIG. 1: the utility model discloses according to 2 supporting design weld zones 101 of chip size, make every device flip back gold ball highly reach suitable value to make chip 2 after the flip, reduce the interval between chip 2 and the base plate 1, inside the clearance that will unable infiltration chip 2 and base plate 1 between tectorial membrane in-process resin 7, thereby avoid the problem that the device became invalid completely.

The welding area 101 is provided with a second placing groove 5, the blocking area 102 is provided with a second protrusion 6, the height difference between the bottom of the second placing groove 5 and the top of the second protrusion 6 is 5-10um, preferably, the second placing groove 5 in the embodiment can be realized by using laser etching on the welding area 101, and the second protrusion 6 can be realized by brushing green oil; make the high decline of chip 2 flip-chip behind first standing groove 3 through setting up second standing groove 5, set up the second simultaneously and protruding 6 for the perpendicular distance at chip 2 bottom and block district 102 top is less than 5um, and inside the clearance that can't permeate between chip 2 and the base plate 1 at tectorial membrane in-process resin, thereby avoid the problem of device inefficacy completely.

Claims

1. A novel CSP substrate structure comprises a substrate (1) and a chip (2) which is inversely arranged on the substrate (1), and is characterized in that: the chip packaging structure further comprises a welding area (101) arranged on the substrate (1) and a blocking area (102) arranged along the edge of the welding area (101), the vertical distance between the bottom of the chip (2) and the top of the blocking area (102) is smaller than 5um, and the projection of the chip (2) on the substrate (1) is superposed with the welding area (101).

2. The novel CSP substrate structure as recited in claim 1, wherein: the welding area (101) is provided with a first placing groove (3), and the chip (2) is arranged in the first placing groove (3) in an inverted mode.

3. The novel CSP substrate structure as recited in claim 2, wherein: the depth of the first placing groove (3) is 5-10um.

4. The novel CSP substrate structure as recited in claim 1, wherein: the blocking area (102) is provided with a first protrusion (4), and the first protrusion (4) is arranged along the top edge of the blocking area (102).

5. The novel CSP substrate structure as claimed in claim 4, wherein: the height of the first bulge (4) is 5-10um.

6. The novel CSP substrate structure as defined in claim 1 wherein: the welding area (101) is provided with a second placing groove (5), the blocking area (102) is provided with a second protrusion (6), and the height difference between the bottom of the second placing groove (5) and the top of the second protrusion (6) is 5-10um.