CN114520202A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN114520202A
CN114520202A CN202111320041.5A CN202111320041A CN114520202A CN 114520202 A CN114520202 A CN 114520202A CN 202111320041 A CN202111320041 A CN 202111320041A CN 114520202 A CN114520202 A CN 114520202A
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CN
China
Prior art keywords
heat sink
semiconductor chip
cover member
wiring substrate
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111320041.5A
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Chinese (zh)
Inventor
秋叶俊彦
田沼祐辅
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN114520202A publication Critical patent/CN114520202A/en
Pending legal-status Critical Current

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Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat sink disposed on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member covering the semiconductor chip and the heat sink and fixing the heat sink. The cover member has a first portion facing the semiconductor chip, a flange portion arranged at a periphery of the first portion and bonded and fixed to the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member as viewed from the heat sink, the heat sink is joined/fixed to the cover member by a joining member partially disposed between the heat sink and the cover member.

Description

Semiconductor device and method for manufacturing the same
Cross Reference to Related Applications
The disclosure of Japanese patent application No. 2020-.
Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
Background
The disclosed techniques are listed below.
[ patent document 1] Japanese unexamined patent application publication No. 2012-54597
A semiconductor device having a structure in which a cap is bonded to a semiconductor chip mounted on a wiring substrate is exemplified (see patent document 1).
Disclosure of Invention
One of the problems in realizing the complex functions of the semiconductor device is to improve the heat dissipation performance of the semiconductor device. In order to realize a complex function of a semiconductor device, power consumption increases, which leads to an increase in the amount of heat generation in a semiconductor chip. If the temperature rise of the semiconductor chip can be suppressed by improving the heat dissipation performance of the semiconductor device, erroneous operation due to heat of the circuit inside the semiconductor chip can be suppressed. Other objects and novel features will become apparent from the description of the specification and drawings.
A semiconductor device according to an embodiment includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat sink disposed on the semiconductor chip to cover the entire semiconductor chip and having an area larger than that of the semiconductor chip; and a cover member that covers the heat sink and the semiconductor chip and fixes the heat sink. The cover member has a first portion facing the semiconductor chip, a flange portion arranged at a periphery of the first portion and bonded and fixed to the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member as viewed from the heat sink, the heat sink is joined and fixed to the cover member by a second joining member which is partially disposed between the heat sink and the cover member.
According to the embodiment, the performance of the semiconductor device can be improved.
Drawings
Fig. 1 is a top view of a semiconductor device according to an embodiment.
Fig. 2 is a bottom view of the semiconductor device shown in fig. 1.
Fig. 3 is a plan view showing an internal structure of the semiconductor device on the wiring substrate in a state where the cover member shown in fig. 1 is removed.
Fig. 4 is a sectional view taken along line a-a of fig. 1.
Fig. 5 is a plan view of the cover member shown in fig. 4 as viewed from the heat sink.
Fig. 6 is an enlarged sectional view taken along line B-B of fig. 5.
Fig. 7 is a plan view showing a layout example of the engaging members according to the modified example of fig. 5.
Fig. 8 is a plan view showing a layout example of engaging members according to another modified example of fig. 5.
Fig. 9 is a cross-sectional view of a semiconductor device according to the modified example of fig. 4.
Fig. 10 is a plan view of the cover member shown in fig. 9 as viewed from the heat sink according to another modified example of fig. 5.
Fig. 11 is a plan view showing a layout example of the engaging members according to the modified example of fig. 10.
Fig. 12 is a sectional view showing a modified example of fig. 9.
Fig. 13 is a plan view showing a modified example of fig. 11.
Fig. 14 is an enlarged sectional view taken along line C-C of fig. 13.
Fig. 15 is an explanatory diagram showing a flow of an assembly process of the semiconductor device explained with reference to fig. 1 to 4.
Fig. 16 is an enlarged plan view showing a modified example of the periphery of the joint portion between the cover member and the wiring substrate shown in any of fig. 4, 9, and 12.
Detailed Description
(description of the forms, basic terms and usage in the present application)
In this application, the present invention will be described in a plurality of portions and the like for convenience, when necessary. However, these portions and the like are not independent of each other unless otherwise specified, and include modified examples and the like in which any one portion of a single example is a specific portion, one portion, or all of another example, regardless of the order in which they are described, unless otherwise specified. In addition, in principle, a repetitive description of the same parts is omitted. In addition, unless specifically stated otherwise, each element of an embodiment is not essential unless logically limited to that number or otherwise apparent from the context.
Similarly, when "X made of a" and the like "are described with respect to a material, a composition and the like in the description of examples and the like, a material, a composition and the like containing other components than a are not excluded unless otherwise specified or unless it is apparent from the context that such a material, a composition and the like are excluded. For example, the component means "X containing A as a main component" or the like. For example, it goes without saying that "silicon material" and the like include not only pure silicon but also SiGe (silicon germanium) alloy or other multicomponent alloy containing silicon as a main component, or a member containing other additives and the like. Further, unless otherwise specified, gold plating, copper plating, nickel plating, and the like include not only pure materials but also members respectively containing gold, copper, nickel, and the like as main components.
Furthermore, even if specific values and numbers are mentioned, they can be more or less than the specific values unless otherwise stated, logically limited to the numbers, and clearly described in context.
Furthermore, in the drawings of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and are not described in detail.
Further, in the drawings, even in a cross-sectional view in a case of being rather complicated or in a case of clearly distinguishing a space therefrom, hatching and the like are omitted in some cases. In this regard, in the case of being clear from the description or the like, in some cases, the outline of the background is omitted even in the closed hole in the plan view. Further, even when the drawing is not a sectional view, a hatched or dotted pattern is added to the drawing so as to be clearly illustrated so as not to become a space or to clearly illustrate a boundary between regions.
In this specification, a "semiconductor component" is a component using electrons inside a semiconductor. As an example of the "semiconductor component", a semiconductor chip, a semiconductor package in which the semiconductor chip is packaged, or the like can be exemplified. A component embedded in a circuit and having an electrical function, whether or not including a semiconductor, is referred to as an "electronic component". The electronic components include not only semiconductor components but also resistive elements, capacitive elements, inductive elements, and the like.
< semiconductor device >
Fig. 1 is a top view of a semiconductor device according to the present embodiment. Fig. 2 is a bottom view of the semiconductor device shown in fig. 1. Fig. 3 is a plan view showing an internal structure of the semiconductor device on the wiring substrate in a state where the cover member shown in the figure is removed. Fig. 4 is a sectional view taken along line a-a of fig. 1.
The semiconductor device PKG1 of the present embodiment includes a wiring substrate SUB1 and a semiconductor chip CHP1 mounted on a wiring substrate SUB1 (see fig. 3). The semiconductor device PKG1 includes: a heat spreader TIM disposed on the semiconductor chip CHP 1; and a wiring substrate SUB1 that covers the entire semiconductor chip CHP1, the entire heat sink TIM, and a portion of the wiring substrate SUB1 and to which the heat sink TIM is fixed.
As shown in fig. 4, the wiring substrate SUB1 has a top surface (surface, main surface, chip mounting surface, first main surface) 2t on which the semiconductor chip CHP1 is mounted, and a bottom surface (surface, main surface, package surface, second main surface) 2b opposite to the top surface 2 t. The wiring board SUB1 has a plurality of side surfaces 2s intersecting the outer edges of the top surface 2t and the bottom surface 2b (see fig. 1 to 3). In the present embodiment, the top surface 2t (see fig. 1) and the bottom surface 2b (see fig. 2) of the wiring substrate SUB1 are each rectangular.
The wiring substrate SUB1 includes a plurality of (eight in the example shown in fig. 4) wiring layers WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 which electrically connect a terminal (terminal 2PD) near the top surface 2t as the chip mounting surface and a terminal (pad 2LD) near the bottom surface 2b as the package surface. Each wiring layer is located between the top surface 2t and the bottom surface 2 b. Each wiring layer includes a conductor pattern such as a wiring as a passage for supplying an electric signal or power. And, the insulating film 2e is arranged between the wiring layers. The wiring layers are electrically connected to each other by: a via hole 2v or a through hole wiring 2THW as an interlayer conduction path penetrating the insulating film 2 e. In the present embodiment, it is noted that a wiring substrate including eight wiring layers is exemplified as an example of the wiring substrate SUB 1. However, the number of wiring layers included in the wiring substrate SUB1 is not limited to eight. For example, a wiring substrate including seven or less wiring layers or nine or more wiring layers may be used as a modified example.
The wiring layer WL1 closest to the top surface 2t among the plurality of wiring layers is covered with the insulating film SR 1. The insulating film SR1 has an opening, and the plurality of terminals 2PD arranged in the wiring layer WL1 are exposed from the insulating film SR1 at the opening. The wiring layer WL8 closest to the bottom surface 2b of the wiring substrate SUB1 among the plurality of wiring layers has a plurality of pads. The wiring layer WL8 is covered with an insulating film SR 2. Each of the insulating film SR1 and the insulating film SR2 is a solder resist film. The plurality of terminals 2PD arranged in the wiring layer WL1, and the plurality of pads 2LD arranged in the wiring layer WL8 are electrically connected to each other by: a conductor pattern (wiring 2d or a large-area conductor pattern), a via hole 2v and a through hole 2THW formed in each wiring layer included in the wiring substrate SUB 1.
The wiring substrate SUB1 is formed by, for example, a build-up method: a plurality of wiring layers are stacked on the top surface 2Ct and the bottom surface 2Cb of the insulating layer (core material, core insulating layer) 2CR made of a prepreg which is glass fiber impregnated with a resin. The wiring layer WL4 near the top surface 2Ct of the insulating layer 2CR and the wiring layer WL5 near the bottom surface 2Cb thereof are electrically connected to each other by a plurality of via wirings 2THW embedded in a plurality of vias penetrating from either one of the top surface 2Ct and the bottom surface 2Cb to the other.
In the example shown in fig. 4, the wiring substrate SUB1 denotes a wiring substrate including a plurality of wiring layers stacked close to the top surface 2Ct and the bottom surface 2Cb of the insulating layer 2CR as a core material. However, a so-called coreless substrate that does not include the insulating layer 2CR made of a hard material such as a prepreg and formed by sequentially stacking the insulating film 2e and a conductor pattern such as the wiring 2d may be used as a modified example of fig. 4. When a coreless substrate is used, the through-hole wirings 2THW are not formed, and the wiring layers are electrically connected to each other through the via holes 2 v.
In the example shown in fig. 4, a solder ball (solder member, external terminal, electrode, external electrode) SB is connected to each of the plurality of pads 2 LD. When the semiconductor device PKG1 is mounted on a motherboard (not shown), the solder balls SB are conductive members that electrically connect a plurality of terminals (not shown) of the motherboard and a plurality of pads 2 LD. The solder ball SB is, for example, a Sn — Pb solder member containing lead (Pb) or a solder member made of so-called lead-free solder substantially free of Pb. As examples of the lead-free solder, for example, single tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), and the like are exemplified. In this case, the lead-free solder means a material containing 0.1 wt% or less of lead (Pb), and the content thereof is defined by the standard of RoHS (hazardous substance restriction) regulation.
As shown in fig. 2, a plurality of solder balls SB are arranged in a matrix form (array form, matrix shape). Although not illustrated in fig. 2, a plurality of pads 2LD (see fig. 4) bonded to a plurality of solder balls SB are also arranged in an array form (matrix form). In this way, a semiconductor device including a plurality of external terminals (solder balls SB and pads 2LD) arranged in an array on a region close to the package surface of the wiring substrate SUB1 is referred to as an area array type semiconductor device. In the area array type semiconductor device, a region close to the package surface (bottom surface 2b) of the wiring substrate SUB1 can be effectively used as an arrangement space of the external terminals. Therefore, the area array type semiconductor device is preferable because even if the number of external terminals is increased, an increase in the package area of the semiconductor device can be suppressed. In other words, in order to achieve a complicated function and high integration, a semiconductor device having an increased number of external terminals can be packaged in a space-saving manner.
The semiconductor device PKG1 includes a semiconductor chip CHP1 mounted on a wiring substrate SUB 1. As shown in fig. 4, each semiconductor chip CHP1 has a front surface (main surface, top surface) 3t and a rear surface (main surface, bottom surface) 3b opposite to the front surface 3 t. The semiconductor chip CHP1 has a plurality of side faces 3s intersecting the front face 3t and the back face 3 b. As shown in fig. 3, the semiconductor chip CHP1 is formed in a rectangular outer shape having a smaller planar area than that of the wiring substrate SUB1 in plan view. In the example shown in fig. 3, the semiconductor chip CHP1 is mounted at the center of the top surface 2t of the wiring substrate SUB1, and each of the four side surfaces 3s of the semiconductor chip CHP1 extends along each of the four side surfaces 2s of the wiring substrate SUB 1.
A plurality of electrodes (pads, electrode pads, bonding pads) 3PD are formed in a region near the front surface 3t of the semiconductor chip CHP 1. In the example shown in fig. 4, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 such that the front surface 3t faces the top surface 2t of the wiring substrate SUB 1. Such a mounting method is called a face-down packaging method or a flip-chip connection method.
Although not shown, a plurality of semiconductor elements (circuit elements) are formed in the main surface of the semiconductor chip CHP1 (more specifically, a semiconductor element formation region disposed on the element formation surface of the semiconductor substrate as the base member of the semiconductor chip CHP 1). The plurality of electrodes 3PD are electrically connected to the plurality of semiconductor elements through wirings (not shown) formed in a wiring layer arranged inside the semiconductor chip CHP1 (more specifically, between the front surface 3t and a semiconductor element formation region not shown).
The semiconductor chip CHP1 (more specifically, the base member of the semiconductor chip CHP 1) is made of, for example, silicon (Si). An insulating film covering the base member and the wiring of the semiconductor chip CHP1 is formed in the front surface 3t, and a part of the plurality of electrodes 3PD is exposed from the insulating film at the opening in the insulating film 3 PF. In the present embodiment, each of the plurality of electrodes 3PD is made of metal such as aluminum (Al).
As shown in fig. 4, the protruding electrode 3BP is connected to each of the plurality of electrodes 3PD, and the plurality of electrodes 3PD of the semiconductor chip CHP1 and the plurality of terminals 2PD of the wiring substrate SUB1 are electrically connected to each other through the plurality of protruding electrodes 3 BP. The protruding electrodes (bump electrodes) 3BP are metal members (conductive members) formed to protrude from the front surface 3t of the semiconductor chip CHP 1. The protruding electrode 3BP is a so-called solder bump formed by stacking solder members via a base metal film (under bump metal). As the solder member constituting the solder bump, a lead-containing solder member or a lead-free solder can be used, similar to the solder ball SB. In mounting the semiconductor chip CHP1 on the wiring substrate SUB1, solder bumps are formed in both the plurality of electrodes 3PD and the plurality of terminals 2PD in advance, and a heating process (reflow process) is performed in a state of contact between the solder bumps so that the solder bumps join to form the protruding electrodes 3 BP. As a modified example of the present embodiment, a pillar bump (pillar electrode) having a solder film formed in a tip surface of a conductor pillar made of copper (Cu) or nickel (Ni) may be used as the protruding electrode 3 BP.
As shown in fig. 4, underfill resin (insulating resin) UF is arranged between the semiconductor chip CHP1 and the wiring substrate SUB 1. The underfill resin UF is arranged to close a space between the front surface 3t of the semiconductor chip CHP1 and the top surface 2t of the wiring substrate SUB 1. Each of the plurality of protruding electrodes 3BP is sealed with underfill resin UF. The underfill resin UF is made of an insulating (non-conductive) material such as a resin material, and is arranged to seal an electrical connection portion (a joint portion of the plurality of protruding electrodes 3 BP) between the semiconductor chip CHP1 and the wiring substrate SUB 1. Since the joint portions between the plurality of protruding electrodes 3BP and the plurality of terminals 2PD are covered with the underfill resin UF, stress on the electrical connection portion between the semiconductor chip CHP1 and the wiring substrate SUB1 can be relaxed. Further, the stress at the joint portion between the plurality of projecting electrodes 3BP and the plurality of projecting electrodes 3BP of the semiconductor chip CHP1 can be relaxed. Further, the main surface of the semiconductor element (circuit element) forming the semiconductor chip CHP1 can be protected.
On the rear surface 3b of the semiconductor chip CHP1, a cover member (cover, heat sink, heat dissipation member) LID is arranged. The cover member LID is, for example, a metal sheet having a higher thermal conductivity than that of the wiring substrate SUB1, and has a function of discharging heat generated in the semiconductor chip CHP1 to the outside. The LID member LID is thermally connected to the semiconductor chip CHP1 through the heat sink TIM. The heat sink TIM makes contact with each of the semiconductor chip CHP1 and the LID member LID.
As a method of thermally connecting the semiconductor chip CHP1 and the LID member LID, a method using a conductive paste formed by mixing a metal filler such as silver particles into a resin paste is exemplified. For example, a conductive paste such as a silver paste formed by mixing a large amount of silver filler into an epoxy resin is exemplified. However, in the case of the conductive paste, heat is transmitted through the metal particles dispersed in the resin material, and therefore, improvement in thermal conductivity efficiency is limited. Therefore, a method of disposing the heat sink TIM made of a material selected to provide high thermal conductivity between the semiconductor chip CHP1 and the LID member LID is effective from the viewpoint of improving thermal conductivity efficiency.
The heat sink TIM is a heat dissipation member for thermally connecting the semiconductor chip CHP1 and the LID member LID. The heat sink TIM is shaped, for example, in a sheet shape so as to be easily disposed between the semiconductor chip CHP1 and the LID member LID. From the viewpoint of improving the heat dissipation property from the semiconductor chip CHP1 to the cover member LID, the heat sink TIM is required to have a high heat dissipation property. The thermal conductivity of the material constituting the heat sink TIM is at least higher than that of the material constituting the underfill resin UF. The thermal conductivity of the material constituting the heat sink TIM is preferably higher than the thermal conductivity of the material constituting the cover member LID. As an example of a material capable of improving the thermal conductivity of the heat sink, for example, a metal film such as a copper film or a silver film can be exemplified. As another example, carbon graphite or boron nitride may be exemplified. Particularly in the case of using carbon graphite, a heat spreader TIM having a thermal conductivity about several times higher than that of a metal material such as copper or silver can be provided. Details of the cover member LID and the heat sink TIM will be described later.
< Heat dissipation channel >
Next, details of the cover member LID and the heat sink TIM shown in fig. 4 will be explained. Fig. 5 is a plan view of the cover member shown in fig. 4 as viewed from the heat sink. Fig. 6 is an enlarged sectional view taken along line B-B of fig. 5. Fig. 7 is a plan view showing a layout example of the engaging members according to the modified example of fig. 5. In fig. 5 and 7, the outline of the portion LID1 facing the semiconductor chip CHP1 is shown by a two-dot chain line. In fig. 5 and 7, the outline of the plurality of engagement members BND2 arranged between the cover member LID and the heat sink TIM is shown by a broken line. In the following description, in each of the drawings shown as a modified example of fig. 5, the outline of the portion LID1 is shown by a two-dot chain line, and the portion of the engagement member BND2 disposed between the LID member LID and the heat sink TIM is shown by a broken line.
As shown in fig. 5, the cover member LID has a portion LID1 facing the rear surface 3b (see fig. 4) of the semiconductor chip CHP1 (see fig. 4), a flange portion LID f disposed at the periphery of the portion LID1 and engaged and fixed to the top surface 2t of the wiring substrate SUB1 by an engaging member BND1 (see fig. 4), and a portion LID2 disposed between the portion LID1 and the flange portion LID f. In a plan view of the LID member LID viewed from the heat sink TIM, as shown in fig. 5, the heat sink TIM is engaged and fixed to the LID member LID by an engagement member BND2 partially arranged between the heat sink TIM and the LID member LID.
When the cover member LID is used as a main channel for releasing heat generated in the semiconductor chip CHP1, it is important to improve the heat dissipation property of the heat dissipation channel thermally connecting the semiconductor chip CHP1 and the cover member LID, as shown in fig. 6. For example, if there is a space between the semiconductor chip CHP1 and the heat sink TIM or a space between the cover member LID and the heat sink TIM, the heat dissipation property is degraded due to the presence of the space.
In the case of fixing the heat spreader TIM to the semiconductor chip CHP1, it is necessary to dispose an engaging member such as a resin between the semiconductor chip CHP1 and the heat spreader TIM. When a resin joint member such as epoxy resin is used as the joint member, the thermal conductivity of a part of the resin joint member is low, and therefore, an increase in the amount of application of the resin joint member decreases the thermal conductivity of the heat dissipation channel. A method of using a conductive paste formed by mixing metal particles such as silver filler into a resin paste for joining members is considerable. However, in the case of the conductive paste, heat is transmitted through the metal particles dispersed in the resin material, and therefore, the conductive paste has lower thermal conductivity than the heat dissipation member of the present embodiment, such as the release sheet TIM made of a material selected so as to provide high thermal conductivity.
In the present embodiment, since the heat sink TIM is fixed to the LID member LID by the joining member BND2, there is no need to insert the joining member between the heat sink TIM and the semiconductor chip CHP 1. Therefore, when the LID member LID bonded and fixed to the heat sink TIM in advance is pressed onto the wiring substrate SUB1 (see fig. 4) by the bonding member BND1 (see fig. 4), the rear surface 3b of the semiconductor chip CHP1 and the heat sink TIM can be made to easily contact each other. When the joining member BND1 is hardened in a state of contact between the semiconductor chip CHP1 and the heat sink TIM, a gap is hardly left between the semiconductor chip CHP1 and the heat sink TIM. This results in high thermal dissipation properties at the connection interface between semiconductor chip CHP1 and heat sink TIM.
As shown in fig. 6, the heat spreader TIM covers the entire back surface 3b of the semiconductor chip CHP 1. The heat spreader TIM has a portion TIM1 overlapping the back surface 3b of the semiconductor chip CHP1 and a portion TIM2 not overlapping the back surface 3 b. In other words, the heat spreader TIM has a surface 4a facing the semiconductor chip CHP1 and a surface 4b opposite to the surface 4a, and each area of the surfaces 4a and 4b is larger than the area of the back surface 3b of the semiconductor chip CHP 1. When the area of the heat sink TIM is larger than the area of the back surface 3b of the semiconductor chip CHP1, even if a positional difference is generated when the heat sink TIM is fixed or when the LID member LID is attached, the same area as the area of the semiconductor chip CHP1 can be ensured as the heat dissipation area. Since the engagement member BND2 is partially disposed between the heat sink TIM and the LID member LID, the heat sink TIM and the LID member LID can be brought into contact with each other at the portion where the engagement member BND2 is not disposed. This results in high heat dissipation properties at the connection interface between the cover member LID and the heat sink TIM.
In this way, according to the present embodiment, a high heat dissipation property can be ensured at each of the connection interface between the semiconductor chip CHP1 and the heat sink TIM, and the connection interface between the cover member LID and the heat sink TIM, and therefore, heat generated in the semiconductor chip CHP1 can be effectively discharged. This results in suppression of temperature rise of the semiconductor chip CHP1, and therefore, erroneous operation due to heat of the circuit inside the semiconductor chip CHP1 can be suppressed. In other words, according to the present embodiment, the complex function of the semiconductor chip CHP1 can be realized, and the performance thereof can be improved.
As shown in fig. 6, the heat sink TIM is engaged and fixed to the LID member LID by an engagement member BND2 arranged at a position overlapping with a portion LID2 of the LID member LID. In other words, the heat sink TIM has, in the thickness direction of the heat sink TIM, a portion TIM1 overlapping the semiconductor chip CHP1, and a portion TIM2 not overlapping the semiconductor chip CHP1 but overlapping the portion LID2 of the LID member LID. An engagement member BND2 that engages the heat sink TIM and the LID member LID is engaged to the partial TIM2 of the heat sink TIM. Although not illustrated, as a modified example of the present embodiment, a case where the engagement member BND2 is engaged not to the TIM2 portion but to the TIM1 portion is also exemplified. Even in this case, when the engagement member BND2 is partially engaged, the heat dissipation channel can be ensured by the portion not engaged to the engagement member BND 2.
On the other hand, as shown in fig. 6, when the engagement member BND2 is arranged at a position overlapping with the portion LID2 (a position overlapping with the portion TIM 2), even if the amount of the engagement member BND2 arranged at a position overlapping with the portion LID1 is small, a necessary engagement strength can be ensured. Ideally, it is particularly preferable that the engagement member BND2 is not arranged at a position overlapping with the portion LID1 of the LID member LID (in other words, not arranged in the portion TIM1 of the heat sink TIM). In order to improve the heat dissipation efficiency, the distance of the heat dissipation channel is preferably smaller. In the case of the heat dissipation channel from the semiconductor chip CHP1 to the cover member LID shown in fig. 6, the channel from the rear surface 3b of the semiconductor chip CHP1 to the portion LID1 of the cover member LID has the smallest distance. Therefore, by disposing the engagement member BND2 having a thermal conductivity lower than that of the heat sink not in the connectable heat dissipation channel having the minimum distance, the heat dissipation efficiency of the entire semiconductor device PKG1 (see fig. 4) can be improved.
Even if a part of the engagement member BND2 is arranged in the region overlapping with the part LID1, as shown in the modified example of fig. 7, the heat dissipation efficiency does not immediately drop significantly. However, the area of the coupling member BND2 disposed at a position overlapping the portion LID1 of the cover member LID is preferably small from the viewpoint of improving heat dissipation efficiency. For example, in the example shown in fig. 7, in the area comparison of the regions where the engagers BND2 are arranged, the engaging area of the engagers BND2 arranged in the region overlapping the portion LID2 is larger than the engaging area of the engagers BND2 arranged in the region overlapping the portion LID 1. This case can reduce the degree of reduction in heat dissipation efficiency due to the arrangement of the engagement member BND2 in the region overlapping the portion LID 1. Although not illustrated, in another example of fig. 7, in the area comparison of the region in which the junction BND2 is arranged, the junction area of the junction BND2 arranged in the region overlapping with the partial LID2 may be smaller than the junction area of the junction BND2 arranged in the region overlapping with the partial LID 1.
Fig. 8 is a plan view showing a layout example of engaging members according to another modified example of fig. 5. As shown in fig. 8, in the modified example of fig. 5, the frame-like engagement member BND2 may be arranged to surround the periphery of the portion LID1 of the LID member LID. In the example shown in fig. 8, the engagement member BND2 is arranged at a position overlapping with the partial LID2 of the cover member LID, but is not arranged at a position overlapping with the partial LID 1.
On the other hand, in the example shown in fig. 5, the heat sink TIM is joined and fixed to the LID member LID by a plurality of joining members BND2 separated from each other. Although described in detail later, in the step of joining and fixing the heat sink TIM to the LID member LID, the heat sink TIM is joined and fixed thereto by attaching the heat sink TIM to the LID member LID in a state where the joining member BND2 is applied to at least either one of the heat sink TIM and the LID member LID, and then the joining member BND2 is hardened. In this case, when gas remains in the space surrounded by the engagement member BND2, the heat sink TIM, and the LID member LID, if there is no passage for discharging the gas, the gas may remain between the heat sink TIM and the LID member LID. Therefore, in the example shown in fig. 8, the work for attaching the heat sink TIM to the LID member LID is preferably performed in a vacuum state (i.e., a reduced pressure state in which the pressure is lower than the atmospheric pressure). Meanwhile, in the example shown in fig. 5, since there is a space between the plurality of engagement members BND2, the gas is discharged to the outside by pressing the heat sink TIM onto the LID member LID. Alternatively, even if gas remains between the heat sink TIM and the cover member LID, the remaining gas LID may be discharged through the gap between the heat sink TIM and the cover member LID by pressing the cover member LID in the direction toward the rear surface 3b of the semiconductor chip CHP1 in the step of bonding and fixing the cover member LID to the wiring substrate SUB1 (see fig. 4).
< first modified example >
Next, as a modified example with reference to the semiconductor device shown in fig. 1 to 4, an embodiment in the following case will be explained: electronic components other than the semiconductor chip are arranged between the cover member LID and the wiring substrate SUB 1. Fig. 9 is a cross-sectional view of a semiconductor device according to the modified example of fig. 4. Fig. 10 is a plan view of the cover member shown in fig. 9 as viewed from the heat sink according to another modified example of fig. 5.
The semiconductor device PKG2 shown in fig. 9 is different from the semiconductor device PKG1 shown in fig. 4 in that an electronic component EC1 is arranged in a space surrounded by the cover member LID and the wiring substrate SUB 1. The electronic component EC1 is, for example, a capacitor electrically connected to a power supply circuit included in the semiconductor chip CHP 1. Since the electronic component EC1 as a capacitor is arranged near the semiconductor chip CHP1, a voltage drop at the time of a momentary increase in power demand in some circuits of the semiconductor chip CHP1 can be suppressed. The electronic component EC1 as a capacitor may be applied as a bypass capacitor or a decoupling capacitor. Note that one example has been described as the type of the electronic component EC1, but not only a capacitor but also various modified examples such as a resistive element, an inductor, or a semiconductor component are illustrated.
As shown in fig. 9, the semiconductor device PKG2 includes an electronic component EC1 mounted on the wiring substrate SUB1 and covered by a cover member LID. The electronic component EC1 includes an electrode ECe1 exposed to a space surrounded by the cover member LID and the wiring substrate SUB 1. As shown in the drawing, when the electrode ECe1 exposed on the wiring substrate SUB1 is arranged adjacent to the semiconductor chip CHP1, attention needs to be paid to an electrical failure of the chip drop due to breakage of the heat sink TIM. In other words, when the heat sink TIM is a conductive member, the sheet resulting from the breakage of a part of the heat sink TIM becomes a conductive material. When in contact with the electrode ECe1, the conductive substance may be a cause of an electrical fault such as a short circuit. However, as described above, the heat sink TIM is a component for improving the thermal conductivity property, and for this reason, many materials have electrical conductivity in many cases. For example, carbon graphite has a higher thermal conductivity than copper and silver, but at the same time has an electrical conductivity. Therefore, when the electronic component EC1 including the exposed electrode ECe1 is disposed adjacent to the semiconductor chip CHP1, it is important to suppress breakage of the heat sink TIM.
According to the study of the present inventors, when the planar shape of the heat sink TIM is rectangular, the fragile portions are particularly the four corners. If the joining member BND2 is joined to the four corners, the heat sink TIM can be prevented from being broken. Explained with reference to fig. 10, the heat sink TIM has four sides and four corners as intersections between the four sides in plan view. Specifically, the heat sink TIM has a side Ts1 extending in the X direction, a side Ts2 opposing the side Ts1, a side Ts3 extending in the Y direction intersecting the X direction, and a side Ts4 opposing the side Ts 3. Further, the heat sink TIM has a corner Tc1 at the intersection between the side Ts1 and the side Ts3, a corner Tc2 at the intersection between the side Ts1 and the side Ts4, a corner Tc3 at the intersection between the side Ts2 and the side Ts3, and a corner Tc4 at the intersection between the side Ts2 and the side Ts 4. In this case, as shown in fig. 10, the joining member BND2 is joined to each of the four corners of the heat sink (specifically, the corners Tc1, Tc2, Tc3, and Tc 4).
Stress is easily concentrated on the corners Tc1, Tc2, Tc3, and Tc 4. Therefore, if the heat sink TIM is broken, any one of the corners Tc1, Tc2, Tc3, and Tc4 is easily broken. When the engagement member BND2 is engaged to each of the four corners Tc1, Tc2, Tc3, and Tc4, as shown in fig. 10, the engagement member BND2 can prevent falling off due to breakage of the heat sink TIM.
In the method of suppressing breakage of the heat sink TIM, an "R (round) chamfering" process may be performed on each of the corners Tc1, Tc2, Tc3, and Tc4 to cut each intersection of the sides Ts1, Ts2, Ts3, and Tc4 in advance. In this case, the R chamfered portions may be regarded as the corners Tc1, Tc2, Tc3, and Tc 4.
Fig. 10 shows an example in which the engagement members BND2 separated from each other are engaged to each corner Tc1, Tc2, Tc3 and Tc 4. However, the layout of the engagement member BND2 includes various modified examples. For example, as shown in fig. 11 as one modified example of fig. 10, an engaging member BND2 extending in a belt-like shape is used in some cases. In the example shown in fig. 11, the engagement member BND2 extending in a belt-like shape along the side Ts1 is engaged to the corner Tc1 and the corner Tc 2. The engaging member BND2 extending in a belt-like shape along the side Ts2 is engaged to the corner Tc3 and the corner Tc 4.
Fig. 12 is a sectional view showing a modified example of fig. 9. The semiconductor device PKG2 shown in fig. 12 is different from the semiconductor device PKG1 shown in fig. 9 in that a semiconductor element CHP2 is mounted in a space surrounded by a cover member LID and a wiring substrate SUB 1. The semiconductor component CHP2 is mounted on the wiring substrate SUB1 such that the surface on which the plurality of electrodes 5PD are formed faces the top surface 2t of the wiring substrate SUB 1. The plurality of electrodes 5PD of the wiring substrate SUB1 and the plurality of terminals 2PD of the wiring substrate are electrically connected to each other by the protruding electrodes 5 BP. Each of the plurality of electrodes 5PD and the protruding electrodes 5BP is sealed by underfill resin UF.
The semiconductor component CHP2 is, for example, a memory package including a memory circuit. Meanwhile, the semiconductor chip CHP1 in the example shown in fig. 12 includes, for example, a control circuit for transmitting a data signal to/from the memory circuit of the semiconductor package CHP 2.
In the case where a semiconductor device (as seen in the semiconductor device PKG 3) includes a plurality of semiconductor components (the semiconductor chip CHP1 and the semiconductor component CHP2), the contact of the heat sink TIM with each of the plurality of semiconductor components enables the plurality of semiconductor components to be arranged close to each other, and can contribute to reducing the number of processes for attaching the heat sink TIM. As shown in fig. 12, the heat sink TIM is arranged to cover each of the semiconductor chip CHP1 and the semiconductor assembly CHP 2. The heat sink TIM is bonded and fixed to the LID member LID similarly to the semiconductor device PKG1 shown in fig. 4 and the semiconductor device PKG2 shown in fig. 9. The layout of the junction element BND2 (see fig. 5) is the same as the layout of the junction element BND2 explained with reference to fig. 5 to 8, 10 and 11. Either way, since the semiconductor assembly CHP2 and the heat sink TIM can contact each other, the thermal conductivity efficiency of the heat dissipation channel from the semiconductor assembly CHP2 can be improved.
< second modified example >
Next, as a modified example of fig. 11, a modified example of a joining and fixing method of the joining member will be exemplified. Fig. 13 is a plan view showing a modified example of fig. 11. Fig. 14 is an enlarged sectional view taken along line C-C of fig. 13. In fig. 13, since a part of the heat sink TIM is covered with the joining member BND3, the outline of the heat sink TIM is shown in a dashed line.
The method of arranging the joining member BND3 shown in fig. 13 and 14 differs from the joining and fixing method of the heat sink TIM shown in fig. 11 in that the joining member BND3 is attached to a region close to the surface 4a of the heat sink TIM (see fig. 14) which faces the semiconductor chip CHP 1. As shown in fig. 14, the heat spreader TIM has a surface 4a facing the semiconductor chip CHP1 and a surface 4b opposite to the surface 4 a. The junction element BND3 is a tape-shaped member, and the junction element BND3 includes a film layer BNF and an adhesion layer BNA formed on either surface of the film layer BNF. The adhesive layer BNA of the joining member BND3 is pasted on the cover member LID and the surface 4a of the heat sink TIM.
In the present modified example, the joining member BND3 is not between the semiconductor chip CHP1 and the heat sink TIM, nor between the heat sink TIM and the LID member LID. Accordingly, the contact area between the heat sink TIM and the cover member LID can be made larger than that of the embodiment shown in fig. 6.
In the present modified example, since the end of the heat sink TIM is covered with the joining member BND3 as a belt-shaped member, it is easy to prevent the falling off due to partial breakage of the heat sink TIM.
In the present modified example, the layout illustrated in fig. 13 is shown as an example of an embodiment in which the joining member BND3 is attached to the surface 4a of the heat sink TIM. However, the shape and layout of the engagement member BND3 include various modified examples. For example, similar to the engagement member BND2 shown in fig. 5, four engagement members BND3 separated from each other may be attached to corners Tc1, Tc2, Tc3, and Tc4 of the heat sink TIM, respectively (see fig. 13). Alternatively, similar to the engagement member BND2 shown in fig. 8, the frame-shaped engagement member BND3 may be attached to surround the periphery of the portion LID1 of the LID member LID.
However, in the present modified example, as shown in fig. 14, from the viewpoint of avoiding interference from the semiconductor chip CHP1, it is preferable to arrange the engagement member BND3 so as not to be located at a position overlapping with the portion LID1 of the LID member LID. Also, in order to fix the heat sink TIM to the LID member LID, it is necessary to bond the adhesive layer BNA of the bonding member BND3 to the heat sink TIM and the LID member LID.
< method for manufacturing semiconductor device >
Next, a method of manufacturing a semiconductor device will be explained in sequence. This section illustrates a method of manufacturing the semiconductor device shown in fig. 4, which is explained as a typical example of the semiconductor device. For each modified example, only the differences from the typical example will be explained. Fig. 15 is an explanatory diagram showing a flow of an assembly process of the semiconductor device explained with reference to fig. 1 to 4.
< substrate preparation step >
In the substrate preparation step shown in fig. 15, a wiring substrate SUB1 shown in fig. 4 is prepared. On the wiring substrate SUB1 prepared in this step, the respective members of the wiring substrate SUB1 explained with reference to fig. 4 are formed. However, as the wiring substrate SUB1, in the present step, the wiring substrate SUB1 provided before mounting the semiconductor chip CHP1, the heat sink TIM, and the LID member LID is prepared.
< chip preparation step >
In the chip fabrication step shown in fig. 15, the semiconductor chip CHP1 shown in fig. 3 and 4 is fabricated. The structure of the semiconductor chip CHP1 is as described above, and therefore, a duplicate description will be omitted.
< Cap preparation step >
In the cover preparation step shown in fig. 15, the cover member LID previously engaged with the heat sink shown in fig. 4 is prepared. Details of the presetting step will be described later.
< die bonding step >
Next, in a die bonding step shown in fig. 15, the semiconductor chip CHP1 is mounted on the top surface 2t of the wiring substrate SUB1 as shown in fig. 4. In the die bonding step, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 such that the front surface 3t faces the top surface 2t of the wiring substrate SUB 1. The plurality of electrodes 3PD of the semiconductor chip CHP1 are arranged at positions facing the plurality of terminals 2PD of the wiring substrate SUB1, respectively. After the semiconductor chip CHP1 is mounted on the wiring substrate SUB1, a reflow process is performed to electrically connect the plurality of electrodes 3PD and the plurality of terminals 2PD through the protruding electrodes 3 BP. This connection method is referred to as a flip chip connection method, and the die bonding method of the present embodiment is referred to as a face-down mounting method in which the front surface 3t of the semiconductor chip CHP1 and the top surface 2t of the wiring substrate SUB1 are arranged to face each other.
< sealing step >
Next, in the sealing step shown in fig. 15, as shown in fig. 4, underfill resin UF is supplied into the gap between the semiconductor chip CHP1 and the wiring substrate SUB1 to seal the plurality of protruding electrodes 3BP so that the protruding electrodes are electrically insulated from each other.
< Cap mounting step >
Next, in the cover mounting step shown in fig. 15, as shown in fig. 4, the cover member LID is mounted on the top surface 2t of the wiring substrate SUB 1. The LID mounting step includes a LID bonding step of bonding the LID member LID to the wiring substrate SUB1 through the bonding member BND1 and a bonding member hardening step of hardening the bonding member BND 1. In this step, the cover member LID is bonded and fixed onto the top surface 2t of the wiring substrate SUB1 to cover the entire semiconductor chip CHP1, the entire heat sink TIM and a part of the wiring substrate SUB1 and to arrange the heat sink TIM to face the back surface 3b of the semiconductor chip CHP 1.
In the case of the method of manufacturing the semiconductor device PKG2 shown in fig. 9, the electronic component EC1 is mounted in advance at any timing between the substrate preparation step and the lid mounting step. In this step, the cover member LID is arranged to completely cover the semiconductor chip CHP1 and the electronic component EC 1.
In the case of the method of manufacturing the semiconductor device PKG3 shown in fig. 12, the semiconductor module CHP2 is mounted in advance at any timing between the substrate preparation step and the lid mounting step. In this step, the cover member LID is arranged to completely cover the semiconductor chip CHP1 and the semiconductor package CHP 2.
In this step, the cover member LID is pressed so that the heat sink TIM is pressed onto the semiconductor chip CHP 1. By adjusting the pressing force, residual gas between the semiconductor chip CHP1 and the heat sink TIM and between the heat sink TIM and the LID member LID can be evacuated, and the heat sink TIM can be brought into contact with each of the semiconductor chip CHP1 and the LID member LID.
< ball mounting step >
Next, in the ball mounting step shown in fig. 15, a plurality of solder balls SB (see fig. 2 and 4) are bonded to a plurality of pads 2LD (see fig. 4) formed on the bottom surface of the wiring substrate SUB 1. In this step, the solder ball SB is arranged on each of the plurality of pads 2LD exposed at the bottom surface of the wiring substrate SUB1 and then heated, and thus, the plurality of solder balls SB and the pads 2LD are bonded to each other. Through this step, the plurality of solder balls SB are electrically connected to the semiconductor chip CHP1 through the wiring substrate SUB 1.
Through each of the above steps, the semiconductor device PKG1 explained with reference to fig. 1 to 4 is provided. Then, necessary tests and experiments such as appearance inspection tests, electrical tests, and the like are performed, and the semiconductor device PKG1 is shipped or mounted on a mounting board, not illustrated.
< detailed information of the lid preparation step >
Next, the cap preparation step shown in fig. 15 is explained in detail. As shown in fig. 15, the cap preparation step includes a cap molding step, a bonding material application step, a heat sink bonding step, and a bonding member hardening step.
In the cover molding step, the cover member LID is molded as shown in fig. 4 and 5, for example. The cover member LID is made of metal and can be easily molded by, for example, die casting using a die. As shown in fig. 5, the molding cover member has a portion LID1 facing the rear surface 3b of the semiconductor chip CHP1 in the cover mounting step, a flange portion LID f (see fig. 4) disposed in the periphery of the portion LID1 and engaged and fixed to the top surface 2t (see fig. 4) of the wiring substrate SUB1 by the engaging member BND1, and a portion LID2 existing between the portion LID1 and the flange portion LID f.
As explained with reference to fig. 5 to 8, 10, and 11, in the joining method in which the joining member BND2 is disposed between the LID member LID and the heat sink TIM, a joining member application step shown in parentheses in fig. 15 is performed before the heat sink joining step. In the joining member applying step, the pasted joining member BND2 is prepared, and the joining member BND2 is partially applied to at least one of the LID member LID and the heat sink TIM. In the present embodiment, the junction element BND2 does not need to have high thermal conductivity properties, and therefore, has a high degree of freedom in the selection of the material constituting the junction element BND 2. For example, from the viewpoint of ease of application and joining strength, an appropriate joining member BND2 can be selected. For example, epoxy without filler may be used for the junction element BND1 shown in fig. 4 and the junction element BND2 shown in fig. 6. Alternatively, a resin joint member containing a filler may be selected. Alternatively, the engagement member BND1 and the engagement member BND2 may be made of different materials from each other.
As explained with reference to fig. 13 and 14, in the case of the joining method of attaching the joining member BND3 as a tape-like member to the surface 4a of the heat sink TIM, the joining member applying step may be omitted.
The heat spreader TIM prepared in the heat spreader bonding step has, for example, a surface 4a facing the semiconductor chip CHP1 in the cap mounting step and a surface 4b opposite to the surface 4a, as shown in fig. 6. Each area of the surface 4a and the surface 4b is larger than the area of the back surface 3b of the semiconductor chip CHP 1. As explained with reference to fig. 5 to 8, 10, and 11, in the joining method of disposing the joining member BND2 between the LID member LID and the heat sink TIM, the pasted joining member BND2 is applied to at least one of the LID member LID and the heat sink TIM in advance, and therefore, after the position alignment between the LID member LID and the heat sink TIM, the heat sink TIM can be joined to the LID member LID by pressing the heat sink TIM onto the LID member LID. In the positional alignment between the LID member LID and the heat sink TIM, the positional alignment is performed such that the heat sink TIM covers the entire portion LID1 of the LID member. It is preferred that the heat sink TIM covers the entire circumference of a portion of LID2, which is adjacent to portion LID 1. In this step, attachment of the LID member LID to the heat sink TIM is preferably performed to prevent air bubbles from remaining. However, even if the air bubbles remain, the air bubbles can be discharged through the cap joining step of the cap mounting step.
As explained with reference to fig. 13 and 14, in the case of the bonding method of attaching the bonding member BND3 as a band-shaped member to the surface 4a of the heat sink TIM, the positional alignment between the LID member LID and the heat sink TIM is performed in the heat sink bonding step. The details of the positional alignment are the same as those of the above-described method. After the positional alignment between the LID member LID and the heat sink TIM is completed, the engagement member BND3 as a belt-like member is attached to the surface 4a of the heat sink TIM (see fig. 14). After the adhesive layer BNA (see fig. 14) is pasted on both the LID member LID and the heat sink TIM, the temporary fixation of the heat sink TIM is completed.
As seen in the semiconductor device PKG2 explained with reference to fig. 9, when the electrode ECe1 is exposed between the cover member LID and the wiring substrate SUB1, for example, it is preferable to join the joining member BND2 to each of the corners Tc1, Tc2, Tc3, and Tc4 as shown in fig. 10 in the heat sink joining step.
In the joining member curing step, the thermosetting resin composition contained in the joining member BND2 shown in fig. 6 or the adhesion layer BNA of the joining member BND3 shown in fig. 14 is cured, for example, by heating. In this way, the heat sink TIM is bonded and fixed to the LID member LID. Since the heat sink TIM is temporarily fixed to the LID member LID by the heat sink bonding step of the LID preparation step, the bonding member curing step of the LID preparation step may be omitted depending on the strength of the temporary fixation in some cases. In this case, the coupling member BND1 shown in fig. 4 and the coupling member BND2 shown in fig. 6 (or the adhesion layer BNA of the coupling member BND3 shown in fig. 14) are co-hardened by the coupling member curing step of the lid preparation step shown in fig. 15. Since the joining member hardening step is omitted as described above, the work efficiency of the cap preparing step can be improved.
< modified example of engaging portion of cover member >
Fig. 16 is an enlarged plan view showing a modified example of the joining region between the cover member and the wiring substrate shown in any one of fig. 4, 9, and 12.
In the structure of the portion connecting the cover member LID and the wiring substrate SUB1, the semiconductor device PKG4 shown in fig. 16 is different from each of the semiconductor device PKG1 shown in fig. 4, the semiconductor device PKG2 shown in fig. 9, and the semiconductor device PKG3 shown in fig. 12. In the semiconductor device PKG4, an opening is formed in a part of the insulating film SR1, and a part of the conductor pattern (base plane) 2CP formed in the uppermost wiring layer WL1 of the wiring substrate SUB1 is exposed at the opening. The conductor pattern 2CP is a large-area conductor pattern supplied with the ground potential GND. Further, the semiconductor device PKG4 differs from each of the semiconductor device PKG1 shown in fig. 4, the semiconductor device PKG2 shown in fig. 9, and the semiconductor device PKG3 shown in fig. 12 in that the joining member BND4 is a conductive joining member having conductivity. For example, the junction element BND4 shown in fig. 16 is made of a resin component such as epoxy resin and a large number of conductive particles (such as silver particles) contained in the resin component.
In the semiconductor device PKG4, the ground potential GND is supplied to the LID member LID through the bonding member BND4 as a conductive bonding member. In this way, the semiconductor chip CHP1 is covered by the cover member LID, to which the ground potential GND is supplied. In this structure, since the cover member LID functions as a shielding member for shielding electromagnetic noise between the semiconductor chip CHP1 and the peripheral space thereof, the reliability of the electrical operation of the semiconductor chip CHP1 can be improved.
The present invention made by the present inventors has been described above specifically on the basis of the embodiments. However, it goes without saying that the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

Claims (12)

1. A semiconductor device, comprising:
a wiring substrate having a first surface;
a semiconductor chip having a second surface on which a plurality of terminals are arranged and a third surface opposite to the second surface, and mounted on the wiring substrate such that the second surface faces the first surface of the wiring substrate;
a heat sink that is arranged on the third surface of the semiconductor chip to cover the entire semiconductor chip, and that has an area larger than that of the third surface of the semiconductor chip; and
a cover member covering the entire semiconductor chip, the entire heat sink, and a part of the wiring substrate, and the heat sink is fixed to the cover member,
wherein the cover member has a first portion facing the third surface of the semiconductor chip, a flange portion arranged at a periphery of the first portion and bonded and fixed to the first surface of the wiring substrate by a first bonding member, and a second portion arranged between the first portion and the flange portion,
the heat sink is joined and fixed to the cover member by a second joining member partially arranged between the heat sink and the cover member in a plan view of the cover member viewed from the heat sink.
2. The semiconductor device as set forth in claim 1,
wherein the heat sink is joined and fixed to the cover member by the second joining member arranged at a position overlapping the second portion of the cover member.
3. The semiconductor device as set forth in claim 2,
wherein the second engaging member is not arranged at a position overlapping with the first portion of the cover member.
4. The semiconductor device as set forth in claim 1,
wherein the heat sink is joined and fixed to the cover member by a plurality of the second joining members separated from each other.
5. The semiconductor device of claim 1, further comprising:
an electronic component mounted on the wiring substrate and covered by the cover member,
wherein the electronic component includes an electrode exposed to a space surrounded by the cover member and the wiring substrate,
the heat sink has four sides and four corners, two sides of the four sides at the corners intersect with each other in a plan view, and
the second joining member is joined to each of the four corners of the heat sink.
6. The semiconductor device of claim 1, further comprising:
a semiconductor module mounted on the wiring substrate and covered with the cover member,
wherein the heat sink is arranged to cover each of the semiconductor chip and the semiconductor component.
7. A semiconductor device, comprising:
a wiring substrate having a first surface;
a semiconductor chip having a second surface on which a plurality of terminals are arranged and a third surface opposite to the second surface, and mounted on the wiring substrate such that the second surface faces the first surface of the wiring substrate;
a heat sink that is arranged on the third surface of the semiconductor chip to cover the entire semiconductor chip, and that has an area larger than that of the third surface of the semiconductor chip; and
a cover member covering the entire semiconductor chip, the entire heat sink, and a part of the wiring substrate, and the heat sink is fixed to the cover member,
wherein the heat sink has a first portion facing the third surface of the semiconductor chip, a flange portion arranged at a periphery of the first portion and engaged and fixed to the first surface of the wiring substrate by the first engaging member, and a second portion arranged between the first portion and the flange portion,
the heat sink is joined and fixed to the cover member by a second joining member arranged at a position overlapping with the second portion of the cover member in a plan view of the cover member viewed from the heat sink.
8. The semiconductor device as set forth in claim 7,
wherein the heat sink has a fourth surface facing the semiconductor chip and a fifth surface opposite to the fourth surface,
the second joining member is a belt-like member including a film layer and an adhesive layer formed on either surface of the film layer, and
the adhesive layer of the second joint is attached to the fourth surface of the heat sink and the cover member.
9. The semiconductor device as set forth in claim 8,
wherein the heat sink is joined and fixed to the cover member by a plurality of the second joining members separated from each other.
10. The semiconductor device of claim 8, further comprising:
an electronic component mounted on the wiring substrate and covered by the cover member,
wherein the electronic component includes an electrode exposed to a space surrounded by the cover member and the wiring substrate,
the heat sink has four sides and four corners, two sides of the four sides at the corners intersect with each other in a plan view, and
the second engaging member is engaged to each of the four corners of the heat sink.
11. A method of manufacturing a semiconductor device, comprising the steps of:
(a) preparing a wiring substrate having a first surface, a semiconductor chip having a second surface on which a plurality of terminals are arranged and a third surface opposite to the second surface, and a cover member joined to a heat sink;
(b) mounting the semiconductor chip on the first surface of the wiring substrate such that the second surface and the first surface face each other; and
(c) after the step (b), bonding and fixing the cover member onto the first surface of the wiring substrate so as to cover the entire semiconductor chip, the entire heat sink, and a part of the wiring substrate, and to make the heat sink and the third surface of the semiconductor chip face each other,
wherein the cover member has a first portion facing the third surface of the semiconductor chip in the step (c), a flange portion arranged at a periphery of the first portion and bonded and fixed to the first surface of the wiring substrate by a first bonding member, and a second portion arranged between the first portion and the flange portion,
the area of the heat sink is larger than the area of the third surface of the semiconductor chip,
in the step (a), the heat sink is joined and fixed to the cover member by a second joining member partially arranged between the heat sink and the cover member in a plan view of the cover member viewed from the heat sink.
12. A method of manufacturing a semiconductor device, comprising the steps of:
(a) preparing a wiring substrate having a first surface, a semiconductor chip having a second surface on which a plurality of terminals are arranged and a third surface opposite to the second surface, and a cover member joined to a heat sink;
(b) mounting the semiconductor chip on the first surface of the wiring substrate such that the second surface and the first surface face each other; and
(c) after the step (b), bonding and fixing the cover member onto the first surface of the wiring substrate so as to cover the entire semiconductor chip, the entire heat sink, and a part of the wiring substrate, and to make the heat sink and the third surface of the semiconductor chip face each other,
wherein the cover member has a first portion facing the third surface of the semiconductor chip in the step (c), a flange portion arranged at a periphery of the first portion and bonded and fixed to the first surface of the wiring substrate by a first bonding member, and a second portion arranged between the first portion and the flange portion,
the heat sink has a fourth surface facing the semiconductor chip and a fifth surface opposite to the fourth surface,
the area of the fourth surface of the heat sink is larger than the area of the third surface of the semiconductor chip,
in the step (a), the heat sink is joined and fixed to the lid member by a second joining member arranged at a position overlapping the second portion in a plan view of the lid member viewed from the heat sink.
CN202111320041.5A 2020-11-20 2021-11-09 Semiconductor device and method for manufacturing the same Pending CN114520202A (en)

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