CN116487342A - High-density SiP packaging structure and packaging method - Google Patents
High-density SiP packaging structure and packaging method Download PDFInfo
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- CN116487342A CN116487342A CN202310669323.9A CN202310669323A CN116487342A CN 116487342 A CN116487342 A CN 116487342A CN 202310669323 A CN202310669323 A CN 202310669323A CN 116487342 A CN116487342 A CN 116487342A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000012790 adhesive layer Substances 0.000 claims abstract description 10
- 239000003292 glue Substances 0.000 claims description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 6
- 239000000835 fiber Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229920000049 Carbon (fiber) Polymers 0.000 claims description 3
- 239000004917 carbon fiber Substances 0.000 claims description 3
- 239000012634 fragment Substances 0.000 claims description 3
- 239000003365 glass fiber Substances 0.000 claims description 3
- 229910002804 graphite Inorganic materials 0.000 claims description 3
- 239000010439 graphite Substances 0.000 claims description 3
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 14
- 230000002457 bidirectional effect Effects 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920001940 conductive polymer Polymers 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229920007019 PC/ABS Polymers 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002180 anti-stress Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Dispersion Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to a high-density SiP packaging structure and a packaging method. The high-density SiP packaging structure comprises a substrate, a shell, a packaging cover plate, a flip chip group, a bonding interconnection chip group and components, wherein: the substrate is provided with a first interface layer and a second interface layer; the second interface layer is fixedly connected with the first heat sink; the flip chip set comprises a first solder ball array layer, a TSV adapter plate, a second solder ball array layer, a first chip, a first heat conducting adhesive layer and a second heat sink. The flip chip group is connected to the packaging cover plate through the first heat conducting adhesive layer and the second heat sink which are arranged on the first chip, so that the flip chip group dissipates heat towards the direction of the packaging cover plate, and the heat dissipation is provided for the flip chip group, the bonding interconnection chip group and the components through arranging the first heat sink on the second interface of the substrate, so that the heat of the high-density SiP packaging structure can be effectively reduced through the bidirectional heat dissipation channel.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a high-density SiP packaging structure and a packaging method.
Background
The SiP package (System in a Package system-in-package) is a package scheme that integrates multiple functional wafers, including a processor, a memory, and other functional wafers, into one package according to application scenarios, the number of package substrate layers, and other factors, so as to realize a substantially complete function. Sip packaging is commonly used in the field of high-end electronics such as aerospace, weapons, and the like.
However, with the continuous increase of information processing and transmission speed, the high-functional density integrated power density of the SiP package module is rapidly increasing, so how to ensure a good heat dissipation channel of the internal device, especially the internal flip chip, is a problem to be solved in the design of the high-density SiP package structure. The non-airtight heat dissipation technology of the single flip chip cannot well solve the problem of heat dissipation generated by integrating the flip chip and the chip set connected with the bonding together and other components in the cavity. Under the airtight packaging condition, the bonding reliability is ensured, and meanwhile, the interconnection process and the structural characteristics of the through silicon vias are considered, so that the system-in-package structure faces the reliability problems caused by thermal stress and mechanical stress; conventional non-hermetic flip chip packaging schemes are not satisfactory.
Disclosure of Invention
The invention aims to provide a high-density SiP packaging structure so as to solve the problem of heat dissipation in an airtight packaging structure.
A high-density SiP packaging structure comprises a substrate, a shell, a packaging cover plate, a flip chip set, a bonding interconnection chip set and a component, wherein the substrate is provided with an upper surface and a lower surface, and a first interface layer and a second interface layer are respectively arranged on the upper surface and the lower surface; the first interface layer is provided with a connecting circuit to realize electrical connection with the flip chip set, the bonding interconnection chip set and the components, and the second interface layer is fixedly connected with the first heat sink; the flip chip set comprises a first solder ball array layer, an inserter, a second solder ball array layer, a first chip, a first heat conducting glue layer and a second heat sink from bottom to top; wherein: the first heat sink (2) is a fence structure.
Further, the upper surface of the inserter is provided with a metal wiring layer, the lower surface of the inserter is provided with a re-wiring layer, and the metal wiring layer is electrically connected with the re-wiring layer through a silicon channel penetrating through the inserter; wherein:
further, the flip chip set is electrically connected with the silicon channel through the second solder ball array layer, and the substrate is electrically connected with the silicon channel through the first solder ball array layer.
Furthermore, the first interface layer of the substrate is also provided with a golden finger; the bonding interconnection chip set adopts a vertical stacking structure and comprises the following steps: the second heat conducting adhesive layer, the second chip, the silicon gasket and the third chip; the second chip and the third chip are connected with the golden finger through leads.
Further, on the first interface layer of the substrate, glue overflow preventing stop members are arranged around the projected edge of the inserter.
Further, the glue overflow preventing stop piece is a glue overflow preventing groove of the glue dispensing part and a glue overflow preventing groove of the diffusion part.
Further, the anti-overflow adhesive stop piece is an anti-overflow adhesive bulge.
A manufacturing method of a high-density SiP packaging structure comprises the following steps:
s1, finishing a wiring structure on a first interface layer of a substrate, and arranging an anti-overflow stop piece;
s2, welding the first chip and the inserter;
s3, welding the inserter and the substrate;
s4, coating heat-conducting glue on the substrate to paste a second chip, and finishing bonding of the lead and the golden finger;
s5, after the silicon gasket is added on the second chip, a third chip is covered, bonding of the lead and the golden finger is completed, and the chip and the substrate are linearly connected in a lead bonding mode;
s6, mounting components on the substrate;
s7, coating heat-conducting glue on the back surface of the first chip, and mounting a second heat sink;
s8, covering the packaging cover plate to complete the SiP internal packaging structure, and then installing the first heat sink on the second interface layer of the substrate.
A manufacturing method of an inserter applied to a SiP packaging structure comprises the following steps:
providing a substrate and a flip chip set, and bonding the lower surface of the substrate with a passivation layer and a bonding pad formed on the lower surface of the flip chip set;
coating photoresist on a silicon wafer, and etching by adopting an etching process to form a plurality of silicon through holes;
manufacturing side wall insulating layers of a plurality of silicon through holes;
electroplating and filling conductive materials in the plurality of through silicon vias;
exposing the conductive material of the current through silicon via by etching the sidewall insulating layer of any adjacent through silicon via;
and electroplating and filling conductive materials to form silicon channels penetrating up and down.
Further, the cross section of the silicon channel is trapezoidal or circular in shape.
Further, the conductive material is one of carbon fiber, graphite fiber, metal powder, metal fiber and fragments, metal plated glass fiber and any other novel conductive material.
Compared with the prior art, the invention has the remarkable advantages that:
1. the flip chip group dissipates heat in the direction of the packaging cover plate through the first heat conducting adhesive layer and the second heat sink which are arranged on the first chip and are connected to the packaging cover plate, and the heat dissipation is provided for the flip chip group, the bonding interconnection chip group and the components through the first heat sink which is arranged on the second interface of the substrate, so that the heat of the high-density SiP packaging structure can be effectively reduced through the bidirectional heat dissipation channel;
2. the glue overflow prevention stop piece is arranged on the first interface layer of the substrate, so that the influence of glue overflow on the wire bonding procedure of the bonding interconnection chip set is prevented;
3. according to the manufacturing method provided by the invention, the anti-overflow stopper is arranged on the substrate, so that the golden finger on the substrate can be effectively protected from being affected by dispensing in the flip procedure, and the yield is improved.
Drawings
Fig. 1 is a schematic view of an embodiment of a high-density SiP package structure according to the present invention.
Fig. 2 is a schematic view of another embodiment of the high-density SiP package structure of the present invention.
Fig. 3 is a schematic diagram illustrating steps S1 to S3 of a method for manufacturing a high-density SiP package structure according to the present invention.
Fig. 4 is a schematic diagram illustrating steps S4 to S6 of a method for manufacturing a high-density SiP package structure according to the present invention.
Fig. 5 is a schematic diagram of step S7 of the method for manufacturing a high-density SiP package structure according to the present invention.
Fig. 6 is a top view of a high density SiP package structure of the present invention.
In the figure: 1a is a first interfacial layer of a substrate; 1b is a second interfacial layer of the substrate; 1 is a substrate; 2 is a first heat sink; 3 is a packaging cover plate; 4 is a component; 5 is a third chip; 6 is a lead wire; 7 is a silicon gasket; 8 is a second chip; 9 is a second heat conducting glue layer; 11 is a first solder ball array layer; 12 is a TSV adapter plate; 13 is a first underfill layer; 14 is a second solder ball array layer; 15 is a first chip; 16 is a first layer of thermally conductive glue; 17 is a second heat sink; 18 is an anti-overflow groove of the dispensing part; 19 is a glue overflow preventing groove of the diffusion part; 20 is an anti-overflow rubber bump; 21 is a golden finger.
Description of the embodiments
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present disclosure.
It should be noted that when an element is referred to as being disposed on another element, it may be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this specification belongs. The terminology used herein in the description of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the specification. The term "and/or" as used herein "
Including any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the high-density SiP package structure includes a substrate 1, a housing, a package cover 3, and an internal flip-chip set, a bond interconnect chipset, and components 4. The high-density SiP packaging structure forms a closed space through the substrate 1, the substrate shell and the packaging cover plate 3. The substrate 1, the housing and the package cover 3 are sealed with ceramic in the prior art to improve the air tightness, and may be packaged with glass. The substrate 1, the shell and the packaging cover plate 3 form a closed cavity, and a flip chip set, a bonding interconnection chip set and a component 4 are arranged in the cavity. Since the substrate 1 has a certain thickness, as shown in fig. 1, the substrate 1 may be divided into upper and lower interfaces—a first interface layer 1a and a second interface layer 1b; the first interface layer 1a is provided with a connecting circuit to realize electrical connection with the flip chip set, the bonding interconnection chip set and the component 4, and the second interface layer 1b is fixedly connected with the first heat sink 2, wherein the first heat sink 2 is of a fence structure and can radiate heat for the whole packaging structure.
The flip chip set is located on the substrate and comprises the following components from bottom to top: the semiconductor device comprises a first solder ball array layer 11, a TSV adapter plate 12, a second solder ball array layer 14, a first chip 15, a first heat conducting adhesive layer 16 and a second heat sink 17. The first solder ball array layer 11 and the second solder ball array layer 14 are formed by a plurality of laterally and longitudinally arranged hammer balls (also referred to as bumps in the art), and the material may be gold, copper, solder or the like. The first ball array 11 differs from the second ball array 17 in the size and distribution density of the balls. The first ball array 11 has a larger hammer ball diameter than the second ball array 17. The TSV adapter plate 12 is responsible for combining and leading out power and ground in the first chip 15 respectively, so that the number of ports is reduced, and the assembly difficulty on the substrate 1 is reduced. In order to increase the packaging density of the first chips 15, a plurality of first chips 15 may be soldered on the TSV interposer 12 to meet the requirements.
Glue is filled between the first solder ball array layer 11 and the TSV interposer 12, and glue is filled between the second solder ball array layer 14 and the first chip 15, so that the anti-stress capability of the solder balls can be enhanced after the glue is cured by the glue, and heat dissipation can be performed on the integrated first chips, and the glue can be selected from epoxy resin and the like.
As shown in fig. 1, a first heat conducting glue layer 16 and a second heat sink 17 are further disposed on the back surface of the first chip 15 of the flip chip set. By arranging the second heat sink 17 with different thicknesses, good contact between the first chip 15 and the package cover plate 3 is realized through the second heat sink 17, and heat dissipation is provided. Meanwhile, the second heat sink 17 can also support the inside of the packaging structure, so that the rigidity of the whole high-density SiP packaging structure is improved, and the deformation of the high-density SiP packaging structure is restrained. The first chip 15 and the second heat sink 17 are adhered through the first heat conducting adhesive layer 16, and the first heat conducting adhesive layer 16 can further improve the connection firmness of the first chip and the second heat sink and fill gaps between the first chip and the second heat sink, so that the heat conducting efficiency is improved.
The bonding interconnection chip set adopts a vertical stacking structure, as shown in fig. 1, a second chip 8, a silicon gasket 7 and a third chip 5 are sequentially arranged after a second heat conducting glue layer 9 is coated on a first interface layer 1a of a substrate; the leads 6 of the second chip 8 and the third chip 5 are connected to the gold fingers 21 of the first interface layer 1a of the substrate.
There is a first underfill layer 13 between the first solder ball array layer 11 and the TSV interposer 12 due to the need for a flip-chip set. In the existing processing method, underfill is sprayed on the edge of the TSV adapter plate 12 by using a dispensing device through capillary driving type underfill, and the underfill flows into the bottom of the TSV adapter plate 12 fully distributed with connection solder balls under the combined action of fluid surface tension and capillary phenomenon, so that all gaps between the TSV adapter plate 12 and the substrate 1 are gradually filled. Because the first solder ball array layer of the TSV interposer 12 has a larger solder ball diameter, the "capillary" is thicker, resulting in voids and a greatly increased chance of delamination. In order to overcome the occurrence of the above phenomenon, the flip-chip bonding quality is improved, so that the amount of glue used in the actual production process is slightly larger. In addition, the state of dispensing equipment and personnel is changed, and the control accuracy of the glue amount is extremely high. Because the internal layout of the high-density SiP packaging structure is compact, when the glue quantity is controlled improperly (the glue quantity is too much), the glue can flow to the golden finger position to influence the subsequent wire bonding process, so that the anti-overflow glue stop pieces are arranged on the first interface layer 1a of the substrate around the projected edge of the TSV adapter plate.
The glue overflow preventing stop piece can be a glue overflow preventing groove, and the glue overflow preventing groove is etched by laser. Further, the glue overflow preventing groove is divided into a glue overflow preventing groove 18 of the glue dispensing part and a glue overflow preventing groove 19 of the diffusion part. The etching depth of the glue overflow preventing grooves 18 of the dispensing part is smaller than the depth of the glue overflow preventing grooves 19 of the diffusing part. Therefore, the amount of glue is reduced, and the excessive glue on one side of glue dispensing is prevented. Preferably, the glue overflow preventing grooves 18 of the glue dispensing part can be arranged in a shape of a straight line or an L shape according to the glue dispensing process, and the corresponding glue overflow preventing grooves 19 of the diffusion part are in a shape of a concave line or an L shape.
As shown in fig. 2, the glue overflow prevention stopper may also be a glue overflow prevention protrusion 20. The height of the anti-overflow adhesive convex structure is approximately equal to the diameter of the solder balls of the first solder ball array layer. The height and width of the anti-overflow protrusion 20 are not limited by the dispensing part and the diffusion part.
Further, the glue overflow preventing stop member can be arranged in a single mode or can be mixed, as shown in fig. 2, the glue overflow preventing protrusion 20 is arranged on the glue dispensing side, and the glue overflow preventing groove 9 is arranged on the glue spreading side. Both modes of use are within the scope of the invention, as exemplified above.
The high-density SiP packaging structure provided by the invention is implemented through a bidirectional heat dissipation channel: 1. the main heat dissipation channel is a first heat conduction adhesive layer on the back surface of the first chip, and the second heat sink is connected to the packaging cover plate; 2. the auxiliary heat dissipation channel is formed by connecting a first solder ball array layer of the first chip to the TSV adapter plate, connecting a second solder ball array layer to the substrate, and dissipating heat to the outside through a first heat sink connected with the substrate. The heat of the high-density SiP packaging structure can be effectively reduced through the bidirectional heat dissipation channel.
Correspondingly, the invention also provides a packaging method of the high-density SiP packaging structure. As shown in fig. 3 to 5, the method comprises the following steps:
s1, finishing a wiring structure on a first interface layer of a substrate, and arranging an anti-overflow stop piece;
s2, welding the first chip and the inserter;
s3, welding the inserter and the substrate;
s4, coating heat-conducting glue on the substrate to paste a second chip;
s5, covering a third chip after adding a silicon gasket on the second chip, wherein the chip and the substrate are linearly connected in a wire bonding mode;
s6, mounting components on the substrate;
s7, coating heat-conducting glue on the back surface of the first chip, and mounting a second heat sink;
s8, covering the packaging cover plate to complete the SiP internal packaging structure, and then installing a heat sink on the second interface layer of the substrate.
Further, the inspection of the flip chip set is performed twice after the first chip is soldered to the interposer and after the interposer is soldered to the substrate to ensure flip chip soldering quality.
Furthermore, the SiP internal packaging structure is completed by covering the packaging cover plate, and the module can be hermetically packaged by utilizing a laser melting sealing process.
A manufacturing method of an inserter applied to a SiP packaging structure comprises the following steps:
providing a substrate and a flip chip set, and bonding the lower surface of the substrate with a passivation layer and a bonding pad formed on the lower surface of the flip chip set;
coating photoresist on a silicon wafer, and etching by adopting an etching process to form a plurality of silicon through holes;
manufacturing side wall insulating layers of a plurality of silicon through holes;
electroplating and filling conductive materials in the plurality of through silicon vias;
exposing the conductive material of the current through silicon via by etching the sidewall insulating layer of any adjacent through silicon via;
and electroplating and filling conductive materials to form silicon channels penetrating up and down.
Specifically, the cross-section of the silicon channel is trapezoidal or circular in shape.
Specifically, the conductive filler dispersion method is a main method for producing conductive polymer materials, and can be used for manufacturing various conductive polymer materials. The conductive material adopts carbon fiber, graphite fiber, metal powder, metal fiber and fragments, metal-plated glass fiber and other various novel conductive materials.
The novel conductive material adopts a wide range of matrix resins, and common use is as follows: ABS, PE, EVA, PA, PC, PP, PET, POM, and modified PPO, PBT, PVC, blends PC/ABS, etc.
Claims (10)
1. The utility model provides a high density SiP packaging structure, includes base plate (1), shell, encapsulation apron (3), flip-chip set, bonding interconnection chipset, components and parts (4), its characterized in that: the substrate (1) has upper and lower surfaces, which are respectively a first interface layer (1 a) and a second interface layer (1 b); the first interface layer (1 a) is provided with a connecting circuit to realize electrical connection with the flip chip set, the bonding interconnection chip set and the component (4), and the second interface layer (1 b) is fixedly connected with the first heat sink (2); the flip chip set comprises a first solder ball array layer (11), an inserter (12), a second solder ball array layer (14), a first chip (15), a first heat conducting adhesive layer (16) and a second heat sink (17) from bottom to top; wherein: the first heat sink (2) is of a fence structure.
2. The high-density SiP package structure of claim 1, wherein: the upper surface of the inserter (12) is provided with a metal wiring layer, the lower surface of the inserter is provided with a re-wiring layer, and the metal wiring layer is electrically connected with the re-wiring layer through a silicon channel penetrating through the inserter (12); wherein:
the flip chip set is electrically connected with the silicon channel through the second solder ball array layer (14), and the substrate (1) is electrically connected with the silicon channel through the first solder ball array layer (11).
3. A high-density SiP package structure according to claim 1 or 2, wherein: the first interface layer (1 a) of the substrate (1) is also provided with a golden finger (21); the bonding interconnection chip set adopts a vertical stacking structure and comprises the following steps: the second heat conduction adhesive layer (9), the second chip (8), the silicon gasket (7) and the third chip (5); the second chip (8) and the third chip (5) are connected with the golden finger (21) through the lead (6).
4. A high-density SiP package structure according to claim 3, wherein: and on the first interface layer (1 a) of the substrate, glue overflow prevention stop pieces are arranged around the projected edge of the inserter (12).
5. The high-density SiP package structure of claim 4, wherein: the glue overflow preventing stop piece is a glue overflow preventing groove (18) of the glue dispensing part and a glue overflow preventing groove (19) of the diffusion part.
6. The high-density SiP package structure of claim 4, wherein: the anti-overflow stop piece is an anti-overflow protrusion (20).
7. The method for manufacturing a high-density SiP package structure according to claim 1, comprising the steps of:
s1, finishing a wiring structure on a first interface layer (1 a) of a substrate, and arranging an anti-overflow stop piece;
s2, the first chip (15) is welded with the inserter (12);
s3, the inserter (12) is welded with the substrate (1);
s4, coating heat-conducting glue on the substrate (1) to adhere the second chip (8), and finishing bonding of the lead (6) and the golden finger (21);
s5, after a silicon gasket (7) is added on the second chip (8), a third chip (5) is covered, bonding of the lead wire and the golden finger is completed, and the chip and the substrate are linearly connected in a lead bonding mode;
s6, mounting components (4) on the substrate;
s7, coating heat-conducting glue on the back surface of the first chip (15), and mounting a second heat sink (2);
s8, covering the packaging cover plate (3) to complete the SiP internal packaging structure, and then installing the first heat sink (2) on the second interface layer (1 b) of the substrate.
8. A manufacturing method of an inserter applied to a SiP packaging structure is characterized by comprising the following steps: the method comprises the following steps:
providing a substrate (1) and a flip chip group, and bonding the lower surface of the substrate (1) with a passivation layer and a bonding pad formed on the lower surface of the flip chip group;
coating photoresist on a silicon wafer, and etching by adopting an etching process to form a plurality of silicon through holes;
manufacturing a plurality of side wall insulating layers of the silicon through holes;
electroplating and filling conductive materials in the plurality of through silicon vias;
exposing the conductive material of the current through silicon via by etching the sidewall insulating layer of any adjacent through silicon via;
and electroplating and filling conductive materials to form silicon channels penetrating up and down.
9. The method for manufacturing the interposer for the SiP package structure according to claim 8, wherein: the cross section of the silicon channel is trapezoidal or circular in shape.
10. The method for manufacturing the interposer for the SiP package structure according to claim 8 or 9, wherein: the conductive material adopts one of carbon fiber, graphite fiber, metal powder, metal fiber and fragments, metal plated glass fiber and any other novel conductive material.
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| CN202310669323.9A CN116487342A (en) | 2023-06-07 | 2023-06-07 | High-density SiP packaging structure and packaging method |
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| CN202310669323.9A CN116487342A (en) | 2023-06-07 | 2023-06-07 | High-density SiP packaging structure and packaging method |
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