CN114497237A - Stack passivation structure of TOPCon battery and TOPCon battery - Google Patents
Stack passivation structure of TOPCon battery and TOPCon battery Download PDFInfo
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- 238000002161 passivation Methods 0.000 title claims abstract description 167
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 52
- 239000010703 silicon Substances 0.000 claims abstract description 52
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 32
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 17
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 5
- 238000003475 lamination Methods 0.000 claims abstract description 4
- 239000001257 hydrogen Substances 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 19
- -1 hydrogen ions Chemical class 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000006388 chemical passivation reaction Methods 0.000 claims description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 17
- 238000012360 testing method Methods 0.000 description 15
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000031700 light absorption Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000037406 food intake Effects 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses a TOPCon battery and a laminated passivation structure thereof, wherein the laminated passivation structure comprises an N-type silicon substrate, and a first dielectric passivation layer, a second dielectric passivation layer and a third dielectric passivation layer are sequentially arranged on the front surface of the N-type silicon substrate from inside to outside; the first dielectric passivation layer is an aluminum oxide layer, the second dielectric passivation layer is any one layer or a lamination of at least two of a silicon oxide layer, a silicon carbide layer or a silicon oxynitride layer, the thickness of the second dielectric passivation layer is less than 10nm, and the third dielectric passivation layer is a silicon nitride film. The laminated passivation structure has a good passivation effect on the positive surface of the TOPCon battery, and can also obviously improve surface light trapping and improve electrical property.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a TOPCon cell and a laminated passivation structure thereof.
Background
Solar cells are widely used as emerging energy sources, TOPCon cells are one of the future mass production process directions of high-efficiency solar cells, various battery manufacturers have a great deal of research on the process, and various companies have a great deal of research on the product process in order to improve the efficiency.
For example, CN113035997A discloses a solar cell manufacturing process, in which an aluminum oxide film and a silicon nitride film are deposited on the front surface, and before the step of depositing the two films is adjusted to the annealing step, the passivation capability of the aluminum oxide and the silicon nitride is fully activated by using the long-time high temperature during annealing, so as to improve the cell efficiency.
CN202585427U discloses a passivation structure of a solar cell, which comprises a composite stacked passivation film composed of silicon oxide/aluminum oxide/amorphous silicon nitride deposited on the P + layer of the front surface of the solar cell, and a stacked passivation film composed of silicon oxide/amorphous silicon nitride deposited on the N + layer of the back surface field. The passivation structure can effectively saturate dangling bonds, reduce surface states, reduce surface recombination speed, prolong the effective minority carrier lifetime of the cell, obtain higher open-circuit voltage and short-circuit current and improve the photoelectric conversion efficiency of the solar cell.
However, the passivation structure directly applied to the front surface of the TOPCon cell has poor passivation effect, and the optical performance and the electrical performance need to be improved.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a topocon battery and a stacked passivation structure thereof. The laminated passivation structure has a good passivation effect on the positive surface of the TOPCon battery, and can also obviously improve surface light trapping and improve electrical property.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the invention provides a stacked passivation structure of a TOPCon battery, which comprises an N-type silicon substrate, wherein a first dielectric passivation layer, a second dielectric passivation layer and a third dielectric passivation layer are sequentially arranged on the front surface of the N-type silicon substrate from inside to outside;
the first dielectric passivation layer is an aluminum oxide layer, the second dielectric passivation layer is any one layer or a lamination of at least two of a silicon oxide layer, a silicon carbide layer or a silicon oxynitride layer, the thickness of the second dielectric passivation layer is less than 10nm (such as 9nm, 8nm, 7nm, 6nm, 4nm, 3nm, 2nm or 1 nm), and the third dielectric passivation layer is a silicon nitride film (SiN is abbreviated as SiN for short)xA film).
In the laminated passivation structure, the first dielectric passivation layer is an aluminum oxide layer, so that the density of dangling bonds can be reduced, interface traps can be well controlled, and a chemical passivation effect is achieved; the third dielectric passivation layer is a silicon nitride film and has the functions of reducing light reflection, improving light absorption and improving current, so that the efficiency of the cell is improved; a second dielectric passivation layer of a specific thickness and type is disposed between the first dielectric passivation layer and the third dielectric passivation layer, which has two roles: firstly, avoided because silicon nitride film positive charge volume is higher and influence the field passivation effect of the aluminium oxide layer of taking the negative charge, secondly carry out supplementary passivation to the aluminium oxide layer, improve the efficiency of battery.
In one embodiment, the stacked passivation structure may provide a better hydrogen passivation effect during a sintering process in a manufacturing process of a battery, thereby improving battery efficiency.
The following is a preferred technical solution of the present invention, but not a limitation to the technical solution provided by the present invention, and the technical objects and advantageous effects of the present invention can be better achieved and achieved by the following preferred technical solution.
Preferably, the thickness of the first dielectric passivation layer is 1nm to 30nm, such as 1nm, 3nm, 5nm, 6nm, 8nm, 10nm, 12nm, 15nm, 20nm, 23nm, 25nm, 28nm, 30nm, or the like.
Preferably, the first dielectric passivation Layer is prepared by an Atomic Layer Deposition (ALD) method or a Chemical Vapor Deposition (CVD) method.
In the present invention, the CVD method includes any one of PECVD, LPCVD, and APCVD.
Preferably, the thickness of the second dielectric passivation layer is 1nm to 7nm, such as 1nm, 2nm, 3nm, 5nm, 6nm, 7nm, or the like.
Preferably, the second dielectric passivation layer contains hydrogen ions and/or hydrogen atoms. The second dielectric passivation layer contains hydrogen ions and/or hydrogen atoms, preferably contains a large amount of hydrogen ions, so that chemical passivation on the surface of the silicon wafer is facilitated, the passivation effect is improved, and the electrical property is improved.
Preferably, the second dielectric passivation layer is a hydrogenated silicon oxynitride layer.
Preferably, the second dielectric passivation layer is prepared by a CVD method.
Preferably, the thickness of the third dielectric passivation layer is 1nm to 50nm, such as 1nm, 3nm, 5nm, 6nm, 8nm, 10nm, 15nm, 20nm, 23nm, 24nm, 28nm, 30nm, 33nm, 36nm, 40nm, 45nm, 50nm, or the like.
Preferably, the third dielectric passivation layer contains hydrogen ions and/or hydrogen atoms, the ions being present in free form to facilitate passivation of the cell.
Preferably, the refractive index of the third dielectric passivation layer is 1.5 to 2.4 (e.g., 1.5, 1.6, 1.8, 2.0, 2.2, or 2.4), the third dielectric passivation layer is a stacked film composed of films with different refractive indexes, and the refractive indexes of the films in the stacked film are sequentially decreased along a direction away from the silicon substrate. The film layer design for reducing the refractive index layer by layer can reduce optical mismatch and has better antireflection effect.
As a preferable technical solution of the stacked passivation structure of the TOPCon battery of the present invention, a fourth dielectric passivation layer is disposed on a surface of the third dielectric passivation layer on a side away from the silicon substrate, and the fourth dielectric passivation layer is one or a stack of at least two of a silicon oxide layer, a silicon carbide layer, and a silicon oxynitride layer.
Through setting up the fourth dielectric passivation layer, the passivation effect can be optimized on the one hand, and on the other hand is favorable to the supplementary reflection that reduces light, improves the ingestion and the absorption of light, promotes the electric current to improve the efficiency of battery piece.
Preferably, the refractive index of the fourth dielectric passivation layer is lower than that of the third dielectric passivation layer, so that light absorption can be improved, surface light trapping can be improved, and the efficiency of the cell can be improved.
It should be noted that, if the fourth dielectric passivation layer is a stack of at least two layers, the refractive index of each layer in the fourth dielectric passivation layer decreases in sequence along a direction away from the silicon substrate, and the refractive index of the layer adjacent to the third dielectric passivation layer is lower than that of the third dielectric passivation layer.
Preferably, the fourth dielectric passivation layer has a thickness of 1nm to 200nm, such as 1nm, 3nm, 5nm, 6nm, 8nm, 10nm, 15nm, 20nm, 23nm, 24nm, 28nm, 30nm, 33nm, 36nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 125nm, 135nm, 140nm, 145nm, 155nm, 160nm, 170nm, 175nm, 180nm, 190nm, or 200nm, etc., preferably 90nm to 150 nm.
In the laminated passivation structure of the TOPCon battery, the thickness of the fourth dielectric passivation layer is preferably in a thicker range (90 nm-150 nm), and the thinner third dielectric passivation layer (1 nm-50 nm) is matched, so that the passivation effect can be better improved, and the light trapping can be improved.
Preferably, the fourth dielectric passivation layer contains hydrogen ions and/or hydrogen atoms, the free hydrogen ions and/or hydrogen atoms can reduce the recombination rate of the surface, the surface of the battery is passivated, and meanwhile, H can also diffuse into the silicon wafer body to passivate defects and impurities in the silicon wafer body.
Preferably, the fourth dielectric passivation layer is prepared by a CVD method.
Preferably, when the fourth dielectric passivation layer is disposed on the surface of the third dielectric passivation layer, the thickness of the third dielectric passivation layer is 1nm to 50 nm.
In the laminated passivation structure of the TOPCon battery, the optional fourth dielectric passivation layer has various colors, so that the requirements of various aesthetic components can be met, and the products of companies are enriched.
As a preferable technical scheme of the laminated passivation structure of the TOPCon battery, the thickness of the silicon substrate is 100-200 μm, such as 100 μm, 110 μm, 120 μm, 125 μm, 130 μm, 135 μm, 140 μm, 145 μm, 150 μm, 155 μm, 160 μm, 180 μm, 190 μm or 200 μm.
Preferably, the N-type silicon substrate is an N-type single crystal or single crystal-like silicon wafer, and the front surface of the N-type silicon substrate is subjected to texturing and boron doping treatment.
Methods of texturing and boron doping are well known to those skilled in the art and may be performed by those skilled in the art by reference to methods disclosed in the prior art.
Preferably, the front surface of the N-type silicon substrate is doped with boron by high temperature diffusion, and the thickness of the boron doped layer is 0 μm to 5 μm and does not contain 0 μm, for example, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.
Preferably, the stack passivation structure is chemical passivation and field passivation.
In a second aspect, the present invention provides a TOPCon battery comprising a stacked passivation structure as described in the first aspect.
Preferably, the outermost layer of the front surface of the silicon substrate is provided with a front silver layer.
Preferably, SiO is sequentially arranged on the back surface of the silicon substrate from inside to outside2Layer, polysilicon layer, silicon nitride layer and back silver layer.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the TOPCon battery lamination passivation structure, the aluminum oxide layer and the silicon nitride film are adopted, and the second dielectric passivation layer with specific thickness and type is arranged between the aluminum oxide layer and the silicon nitride film, so that the influence on the field passivation effect of the negatively charged aluminum oxide layer due to the high positive charge of the silicon nitride film is avoided, and the auxiliary passivation is carried out on the aluminum oxide layer, so that the battery efficiency is improved.
(2) By optimizing the composition of each layer in the laminated passivation structure of the TOPCon battery and the like and arranging the fourth dielectric passivation layer, the passivation effect is further improved, the light trapping effect is also improved, and the electrical property is improved.
Drawings
Fig. 1 is a schematic structural diagram of a TOPCon battery provided in embodiment 1 of the present invention.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
In the embodiment of the invention, the reaction gas containing hydrogen is selected from silane and/or ammonia gas, and can be ionized into hydrogen atoms and/or hydrogen ions under the action of plasma to participate in hydrogenation.
Example 1
The embodiment provides a stacked passivation structure of a TOPCon battery, which comprises a silicon substrate, wherein a first dielectric passivation layer, a second dielectric passivation layer, a third dielectric passivation layer and a fourth dielectric passivation layer are sequentially arranged on the front surface of the silicon substrate from inside to outside;
the first dielectric passivation layer is an aluminum oxide layer with the thickness of 20nm,
the second dielectric passivation layer is a silicon oxynitride layer containing hydrogen ions and having a thickness of 2nm,
the third dielectric passivation layer is a silicon nitride film which contains hydrogen ions and has a thickness of 50nm,
the fourth dielectric passivation layer is a silicon oxide layer which contains hydrogen ions and hydrogen atoms and is 120nm thick.
The embodiment also provides a TOPCon battery, which includes the above-mentioned stacked passivation structure, and the preparation method of the TOPCon battery includes the following steps:
1) using KOH to perform texturing on an N-type monocrystalline silicon wafer with the thickness of 170 mu m, and cleaning the N-type monocrystalline silicon wafer by an RCA cleaning method; forming a texture surface of a pyramid structure, wherein the reflectivity of the texture surface is 12%;
2) preparing a diffusion layer on the substrate obtained in the step 1) in a high-temperature diffusion mode, wherein the sheet resistance of the diffusion layer is 100 ohms;
3) etching the redundant diffusion layer at the edge completely by using etching liquid, wherein the etching liquid is HF solution (mass fraction of 40%) and HNO3The etching solution is obtained by mixing the solution (68 percent by mass) and water according to the volume ratio of 1:27: 46;
4) by means of the LPVCD, the system,back growth of SiO2A layer and a polysilicon layer having a thickness of 1.5nm and 180nm, respectively;
5) cleaning to remove the redundant polysilicon layer, and cleaning by an RCA method;
6) depositing aluminum oxide on the front surface in a PECVD mode, wherein the thickness is 20 nm;
7) and sequentially growing a silicon oxynitride layer, a silicon nitride film and a silicon oxide layer by a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the thicknesses of the silicon oxynitride layer, the silicon nitride film and the silicon oxide layer are respectively 2nm, 50nm and 120nm, and hydrogen atoms are contained in reaction gas of the PECVD when the three layers are grown.
8) Growing silicon nitride on the back surface in a PECVD mode;
9) printing silver paste on the front surface and the back surface, wherein the width of a main grid is 0.6mm, the number of the main grids is 9, the widths of front silver auxiliary grid lines and back silver auxiliary grid lines are both 35 mu m, the number of the front auxiliary grid lines is 100, and the number of the back auxiliary grid lines is 110;
10) using IV tester, according to IEC60904 standard at 25 deg.C, 1000W/m2The test results are shown in Table 1.
Example 2
The embodiment provides a stacked passivation structure of a TOPCon battery, which comprises a silicon substrate, wherein a first dielectric passivation layer, a second dielectric passivation layer and a third dielectric passivation layer are sequentially arranged on the front surface of the silicon substrate from inside to outside;
the first dielectric passivation layer is an aluminum oxide layer with the thickness of 10nm,
the second dielectric passivation layer is a silicon oxynitride layer containing hydrogen ions and having a thickness of 5nm,
the third dielectric passivation layer is a silicon nitride film which contains hydrogen ions and has a thickness of 65 nm.
The embodiment also provides a TOPCon battery, which includes the above-mentioned stacked passivation structure, and its structural schematic diagram is shown in fig. 1;
along the direction far away from the N-type monocrystalline silicon wafer 5, a first dielectric passivation layer 1 is arranged on the surface of the N-type monocrystalline silicon wafer 5, a second dielectric passivation layer 2 is arranged on the surface of the first dielectric passivation layer 1, a third dielectric passivation layer 3 is arranged on the surface of the second dielectric passivation layer 2, a fourth dielectric passivation layer 4 is arranged on the surface of the third dielectric passivation layer 3, and a front silver layer 9 is arranged on the surface of the fourth dielectric passivation layer 4;
the back of the N-type monocrystalline silicon piece 5 is provided with SiO along the direction far away from the N-type monocrystalline silicon piece 52Layer 6 of said SiO2The surface of the layer 6 is provided with a polysilicon layer 7, the surface of the polysilicon layer 7 is provided with a silicon nitride film 8, and the surface of the silicon nitride film 8 is provided with a back silver layer 10.
The embodiment also provides a preparation method of the TOPCon battery, which comprises the following steps:
1) using KOH to perform texturing on an N-type monocrystalline silicon wafer with the thickness of 140 mu m, and cleaning the N-type monocrystalline silicon wafer by an RCA cleaning method; forming a texture surface of a pyramid structure, wherein the reflectivity of the texture surface is 12%;
2) preparing a diffusion layer on the substrate obtained in the step 1) in a high-temperature diffusion mode, wherein the sheet resistance of the diffusion layer is 100 ohms;
3) etching the redundant diffusion layer at the edge completely by using etching liquid, wherein the etching liquid is HF solution (mass fraction of 40%) and HNO3The etching solution is obtained by mixing the solution (68 percent by mass) and water according to the volume ratio of 1:27: 46;
4) by means of LPVCD, SiO is grown on the back surface2A layer and a polysilicon layer having a thickness of 1.5nm and 170nm, respectively;
5) cleaning to remove the redundant polysilicon layer, and cleaning by an RCA method;
6) depositing aluminum oxide on the front surface by an ALD mode, wherein the thickness of the aluminum oxide is 10 nm;
7) and sequentially growing a silicon oxynitride layer and a silicon nitride layer by a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the thicknesses of the silicon oxynitride layer and the silicon nitride layer are respectively 5nm and 65nm, and hydrogen ions are contained in reaction gas of the PECVD when the two layers are grown.
8) Growing silicon nitride on the back surface in a PECVD mode;
9) printing silver paste on the front surface and the back surface, wherein the width of a main grid is 0.6mm, the number of the main grids is 9, the widths of front silver auxiliary grid lines and back silver auxiliary grid lines are both 35 mu m, the number of the front auxiliary grid lines is 100, and the number of the back auxiliary grid lines is 110;
the test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
Example 3
The difference between this example and example 2 is that step 7) is: and a silicon oxynitride layer, a silicon nitride layer and a silicon oxide layer are sequentially grown in a PECVD mode, the thicknesses of the silicon oxynitride layer, the silicon nitride layer and the silicon oxide layer are respectively 5nm, 35nm and 100nm, and hydrogen ions are contained in reaction gas of the PECVD when the three layers are grown. The test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
Example 4
The difference between this example and example 1 is that step 7) uses PECVD to sequentially grow a silicon oxynitride layer, a first silicon oxide layer, a silicon nitride film and a second silicon oxide layer with thicknesses of 2nm, 3nm, 50nm and 120nm, and the reaction gas of PECVD contains hydrogen atoms when growing these four layers.
The stack of the silicon oxynitride layer and the first silicon oxide layer constitutes a second dielectric passivation layer, the second dielectric passivation layer having a total thickness of 5 nm.
The test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
Example 5
This embodiment differs from embodiment 1 in that the third dielectric passivation layer is replaced with a stacked film of first silicon nitride, second silicon nitride, silicon oxynitride, and silicon oxide, each of which has a thickness of 10nm, 20nm, 25nm, and 30nm, respectively, and a refractive index of 2.1, 1.99, 1.81, and 1.6, respectively, in a direction away from the silicon substrate.
The test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
Comparative example 1
The present comparative example is different from example 1 in that step 7) was not performed, and in the stacked passivation structure of the TOPCon cell of the present comparative example, an aluminum oxide layer having a thickness of 20nm and a silicon nitride film having a thickness of 60nm were sequentially provided from the inside to the outside of the front surface of the silicon substrate.
In the TOPCon battery of the comparative example, the front surface only has two layers of the aluminum oxide film and the silicon nitride film from the silicon substrate, the positive charge of the silicon nitride film is higher, the field passivation effect of the aluminum oxide film with negative charges can be influenced, and meanwhile, the deposition power of the silicon nitride film is higher than that of the aluminum oxide film, and the passivation effect of the aluminum oxide film can be damaged in the deposition process. In addition, the refractive index of the silicon nitride film is about 2.0, the difference between the two is large, and the front light trapping is poor. The passivation structure of the comparative example has to be further improved in passivation ability, optical properties, and electrical properties.
The test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
Comparative example 2
This comparative example differs from example 1 in that no second dielectric passivation layer is provided.
The test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
Comparative example 3
This comparative example differs from example 1 in that the second dielectric passivation layer (i.e. the silicon oxynitride layer) has a thickness of 10 nm.
The test was carried out in the same manner as in example 1, and the test results are shown in Table 1.
TABLE 1
As can be seen from the comparison between example 1 and comparative example 1, in example 1, the silicon oxynitride layer is disposed between the aluminum oxide layer and the silicon nitride film, so that the passivation effect of the front aluminum oxide can be effectively improved, and the open-circuit voltage of the solar cell is increased by about 2mV, thereby increasing the conversion efficiency of the cell, and the conversion efficiency of the solar cell is increased by 0.08%. In addition, compared with the fourth dielectric layer silicon oxide layer added in the comparative example 1, the solar cell light absorption is effectively increased, the short-circuit current density is greatly improved, and the obvious efficiency gain is also brought in the comparative example 2.
It can be seen from the comparison between example 1 and comparative example 3 that the second dielectric passivation layer has too high a thickness, which causes optical mismatch to reduce current, and at the same time, the film layer is too thick, which causes contact resistance to increase, resulting in a decrease in fill factor, which is not favorable for improving the cell efficiency.
The applicant states that the present invention is illustrated in detail by the above examples, but the present invention is not limited to the above detailed methods, i.e. it is not meant that the present invention must rely on the above detailed methods for its implementation. It should be understood by those skilled in the art that any modification of the present invention, equivalent substitutions of the raw materials of the product of the present invention, addition of auxiliary components, selection of specific modes, etc., are within the scope and disclosure of the present invention.
Claims (10)
1. The stacked passivation structure of the TOPCon battery is characterized by comprising an N-type silicon substrate, wherein a first dielectric passivation layer, a second dielectric passivation layer and a third dielectric passivation layer are sequentially arranged on the front surface of the N-type silicon substrate from inside to outside;
the first dielectric passivation layer is an aluminum oxide layer,
the second dielectric passivation layer is any one layer or a lamination of at least two of a silicon oxide layer, a silicon carbide layer or a silicon oxynitride layer, the thickness of the second dielectric passivation layer is less than 10nm,
the third dielectric passivation layer is a silicon nitride film.
2. The topocon cell stack passivation structure of claim 1, wherein the first dielectric passivation layer has a thickness of 1nm to 30 nm;
preferably, the first dielectric passivation layer is prepared by an Atomic Layer Deposition (ALD) method or a Chemical Vapor Deposition (CVD) method.
3. The topocon cell stack passivation structure of claim 1 or 2, wherein the second dielectric passivation layer has a thickness of 1nm to 7 nm;
preferably, the second dielectric passivation layer contains hydrogen ions and/or hydrogen atoms;
preferably, the second dielectric passivation layer is a hydrogenated silicon oxynitride layer;
preferably, the second dielectric passivation layer is prepared by a CVD method.
4. The topocon cell stack passivation structure of any one of claims 1-3, wherein the third dielectric passivation layer has a thickness of 1nm to 65 nm;
preferably, the third dielectric passivation layer contains hydrogen ions and/or hydrogen atoms;
preferably, the refractive index of the third dielectric passivation layer is 1.5-2.4, the third dielectric passivation layer is a laminated film composed of films with different refractive indexes, and the refractive indexes of the films in the laminated film are sequentially reduced along the direction away from the silicon substrate.
5. The TOPCon cell stack passivation structure of any of claims 1 to 4, wherein a fourth dielectric passivation layer is provided on the surface of the third dielectric passivation layer on the side away from the silicon substrate, wherein the fourth dielectric passivation layer is a stack of at least two of a silicon oxide layer, a silicon carbide layer or a silicon oxynitride layer;
preferably, the refractive index of the fourth dielectric passivation layer is lower than the refractive index of the third dielectric passivation layer;
preferably, the thickness of the fourth dielectric passivation layer is 1nm to 200nm, preferably 90nm to 150 nm;
preferably, the fourth dielectric passivation layer contains hydrogen ions and/or hydrogen atoms;
preferably, the fourth dielectric passivation layer is prepared by a CVD method;
preferably, when the fourth dielectric passivation layer is disposed on the surface of the third dielectric passivation layer, the thickness of the third dielectric passivation layer is 1nm to 50 nm.
6. The TOPCon cell stack passivation structure according to any of the claims 1-5, wherein the silicon substrate has a thickness of 100-200 μm;
preferably, the N-type silicon substrate is an N-type monocrystalline silicon wafer or a quasi-monocrystalline silicon wafer, and the front surface of the N-type silicon substrate is subjected to texturing and boron doping treatment.
Preferably, the front surface of the N-type silicon substrate is subjected to boron doping treatment by using a high-temperature diffusion mode, and the thickness of the formed boron doped layer is 0-5 μm and does not contain 0 μm.
7. The stacked passivation structure of a TOPCon cell of any of claims 1-6, wherein the stacked passivation structure is chemical passivation and field passivation.
8. A TOPCon cell comprising the stacked passivation structure of any one of claims 1-7.
9. The TOPCon cell of claim 8, wherein the outermost layer of the front side of the silicon substrate is provided with a front side silver layer.
10. The topocon cell stack passivation structure of claim 8 or 9, characterized in that the back side of the silicon substrate is provided with SiO in sequence from inside to outside2Layer, polysilicon layer, silicon nitride layer and back silver layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115148832A (en) * | 2022-07-14 | 2022-10-04 | 上饶捷泰新能源科技有限公司 | N-TOPCon battery and manufacturing method thereof |
| CN117038799A (en) * | 2023-10-07 | 2023-11-10 | 正泰新能科技有限公司 | BC battery preparation method and BC battery |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115148832A (en) * | 2022-07-14 | 2022-10-04 | 上饶捷泰新能源科技有限公司 | N-TOPCon battery and manufacturing method thereof |
| CN117038799A (en) * | 2023-10-07 | 2023-11-10 | 正泰新能科技有限公司 | BC battery preparation method and BC battery |
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