CN114497027A - Passive filter and preparation method thereof - Google Patents

Passive filter and preparation method thereof Download PDF

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Publication number
CN114497027A
CN114497027A CN202210111884.2A CN202210111884A CN114497027A CN 114497027 A CN114497027 A CN 114497027A CN 202210111884 A CN202210111884 A CN 202210111884A CN 114497027 A CN114497027 A CN 114497027A
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China
Prior art keywords
inductor
capacitor
dielectric substrate
dielectric layer
substructure
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CN202210111884.2A
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Inventor
曹雪
肖月磊
李月
车春城
吴艺凡
安齐昌
常文博
周毅
冯昱霖
韩基挏
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to CN202210111884.2A priority Critical patent/CN114497027A/en
Publication of CN114497027A publication Critical patent/CN114497027A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The disclosure provides a passive filter and a preparation method thereof, and belongs to the technical field of radio frequency devices. The present disclosure provides a passive filter, comprising: the capacitor comprises a dielectric substrate, at least one capacitor and at least one inductor. The medium substrate comprises a slot arranged along the thickness direction of the medium substrate, the inner wall of the slot comprises a first part, and the extension direction of the tangent of at least part of points on the first part is intersected with the extension direction of the plane of the medium substrate. The capacitor comprises a first polar plate, a first interlayer dielectric layer and a second polar plate which are sequentially arranged in a direction deviating from the dielectric substrate, and the first polar plate of the capacitor, the second polar plate of the capacitor and the orthographic projection overlapping part of the first interlayer dielectric layer on the dielectric substrate at least cover the first part.

Description

Passive filter and preparation method thereof
Technical Field
The disclosure belongs to the technical field of radio frequency devices, and particularly relates to a passive filter and a preparation method thereof.
Background
In the modern times, the consumer electronics industry is developing more and more, mobile communication terminals represented by mobile phones, particularly 5G mobile phones, are developing rapidly, the frequency bands of signals to be processed by the mobile phones are more and more, the number of required radio frequency chips is also rising, and the mobile phone form enjoyed by consumers is continuously developing towards miniaturization, lightness and thinness and long endurance. In a traditional mobile phone, a large number of discrete devices such as resistors, capacitors, inductors, filters and the like exist on a radio frequency PCB, and the discrete devices have the defects of large volume, high power consumption, multiple welding points and large change of parasitic parameters, so that the radio frequency PCB is difficult to meet future requirements. The radio frequency chips are mutually interconnected, matched and the like, and the integrated passive device has the advantages of small required area, high performance and good consistency. Integrated passive devices currently on the market are mainly based on Si (silicon) substrates and GaAs (gallium arsenide) substrates. The Si-based integrated passive device has the advantage of low price, but the microwave loss of the device is high and the performance is general due to the fact that Si has trace impurities (poor insulation); the GaAs-based integrated passive device has the advantage of excellent performance, but is expensive.
Disclosure of Invention
The present disclosure is directed to at least one of the technical problems occurring in the prior art, and provides a passive filter and a method for manufacturing the same.
In a first aspect, the present disclosure provides a passive filter comprising: the capacitor comprises a dielectric substrate, at least one capacitor and at least one inductor; the dielectric substrate comprises a slot arranged along the thickness direction of the dielectric substrate; the inner wall of the slot comprises a first part, and the extension direction of a tangent line of at least part of points on the first part is intersected with the extension direction of a plane of the medium substrate; the capacitor comprises a first polar plate, a first interlayer dielectric layer and a second polar plate which are sequentially arranged in a direction deviating from the direction of the dielectric substrate; the first plate of the capacitor, the second plate of the capacitor and the orthographic projection overlapping part of the first interlayer dielectric layer on the dielectric substrate at least cover the first part.
The dielectric substrate further comprises a first connecting through hole penetrating along the thickness direction of the dielectric substrate, and a first surface and a second surface which are oppositely arranged along the thickness direction; the inductor comprises a first substructure arranged on the first surface of the dielectric substrate, a second substructure arranged on the second surface of the dielectric substrate, and a first connection electrode arranged in the first connection via, wherein the first connection electrode connects the first substructure and the second substructure; the inductor is electrically connected with the capacitor.
The inductor comprises a plurality of inductors, wherein the plurality of inductors comprise a first inductor and a second inductor; the passive filter includes a first conductive layer; the first conducting layer comprises a first substructure of the first inductor, a first substructure of the second inductor, and a first plate of the capacitor; the passive filter includes a second conductive layer; the second conductive layer comprises a second substructure of the first inductor and a second substructure of the second inductor; and the first lead end of the first inductor is connected with the first pole plate of the capacitor, and the second lead end of the second inductor is connected with the first pole plate of the capacitor.
Wherein, the orthographic projection of the first interlayer dielectric layer on the dielectric substrate covers the first substructure and the orthographic projection of the first plate of the capacitor on the dielectric substrate; the passive filter further comprises: the second interlayer dielectric layer is arranged on one side, away from the dielectric substrate, of the first interlayer dielectric layer and the second plate of the capacitor; the third interlayer dielectric layer is arranged on one side, away from the dielectric substrate, of the second interlayer dielectric layer; the first connecting pad, the second connecting pad and the third connecting pad are arranged on one side departing from the second dielectric layer; the first connecting bonding pad is connected with a second lead end of the first inductor through a second connecting through hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer; the second connecting pad is connected with the first lead end of the second inductor through a third connecting through hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer; and the third connecting bonding pad is connected with the second plate of the capacitor through a fourth connecting through hole penetrating through the second interlayer dielectric layer.
Wherein, the fluting is blind groove.
The blind grooves comprise hemispherical blind grooves, cylindrical blind grooves and cubic blind grooves.
The first polar plate of the capacitor, the second polar plate of the capacitor and the orthographic projection overlapped part of the first interlayer dielectric layer on the dielectric substrate completely cover the inner wall of the slot.
Wherein the dielectric substrate comprises a glass substrate or a silicon substrate.
In a second aspect, the present disclosure also provides a method for manufacturing a passive filter, where the method includes: providing a dielectric substrate, wherein the dielectric substrate comprises a slot arranged along the thickness direction of the dielectric substrate; the inner wall of the slot comprises a first part, and the extension direction of a tangent line of at least part of points on the first part is intersected with the extension direction of a plane of the medium substrate; forming at least one capacitor and at least one inductor; the step of forming the capacitor comprises: forming a first polar plate of the capacitor, a first interlayer dielectric layer and a second polar plate of the capacitor in sequence on one side departing from the dielectric substrate; the first polar plate of the capacitor, the second polar plate of the capacitor and the orthographic projection overlapped part of the first interlayer dielectric layer on the dielectric substrate cover the first part.
Wherein the open slot comprises a blind slot; the dielectric substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the dielectric substrate; the providing a dielectric substrate includes: and forming the blind groove on the first surface of the dielectric substrate along the thickness direction of the dielectric substrate.
Wherein, the providing a dielectric substrate further comprises: and forming a first connecting through hole in the dielectric substrate along the thickness direction of the dielectric substrate.
Wherein the first connecting via and the slot are formed by an etching process.
Wherein the step of forming the first connecting via and the blind via comprises: carrying out laser modification on the dielectric substrate; so that when the medium substrate is subjected to the primary etching process, the medium substrate can be subjected to the isotropic etching and the anisotropic etching simultaneously; and forming the slot and the first connecting through hole by one-time etching process.
Wherein the step of forming at least one of the inductors further comprises forming a first inductor and a second inductor; the step of forming the first inductor and the second inductor comprises: forming a first connection electrode in the first connection via; the medium substrate comprises a first surface and a second surface which are oppositely arranged; forming a first substructure of the first inductor and a first substructure of the second inductor on the first surface of the dielectric substrate; forming a second substructure of the first inductor and a second substructure of the second inductor on the second surface of the dielectric substrate; the first substructure of the first inductor, the second substructure of the first inductor and the first connection electrode constitute a coil structure of the first inductor; the first substructure of the second inductor, the second substructure of the second inductor, and the first connection electrode constitute a coil structure of the second inductor.
Wherein, the preparation method also comprises the following steps: forming a second interlayer dielectric layer on one side of the dielectric substrate, which is far away from the first surface, and forming a second connecting through hole and a third connecting through hole which penetrate through the first interlayer dielectric layer and the second interlayer dielectric layer, and a fourth connecting through hole which penetrates through the second interlayer dielectric layer; forming a third interlayer dielectric layer on one side of the dielectric substrate, which is far away from the second surface;
the method for preparing the substrate further comprises: forming a first connection bonding pad, a second connection bonding pad and a third connection bonding pad on one side departing from the second interlayer dielectric layer;
the first connection pad is connected with the first substructure of the first inductor through the second connection via hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer; the second connection pad is connected with the first substructure of the second inductor through a third connection via hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer; and the third connecting bonding pad is connected with the second plate of the capacitor through a fourth connecting through hole penetrating through the second interlayer dielectric layer.
Drawings
Fig. 1 is a schematic cross-sectional view of a passive filter according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a capacitor in an embodiment of the disclosure;
FIG. 3 is a schematic diagram of an inductor in an embodiment of the present disclosure;
fig. 4 is a circuit diagram of a passive filter of an embodiment of the present disclosure;
fig. 5 is a cross-sectional schematic view of an integrated filter according to an embodiment of the disclosure;
fig. 6 is a schematic flow chart illustrating a process for manufacturing a passive filter according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of step S10 of the disclosed embodiment;
fig. 8 is a schematic flow chart illustrating the preparation process of step S10 according to the embodiment of the present disclosure;
fig. 9 and 10 are schematic diagrams of step S102 of an embodiment of the present disclosure;
fig. 11 is a schematic diagram of step S104 according to an embodiment of the disclosure;
fig. 12 is a schematic diagram of step S11 of the disclosed embodiment;
fig. 13 is a schematic diagram of step S12 of the disclosed embodiment;
fig. 14 is a schematic diagram of step S13 of the disclosed embodiment;
fig. 15 is a schematic diagram of step S14 of an embodiment of the present disclosure;
fig. 16 is a schematic diagram of step S15 of the disclosed embodiment;
fig. 17 is a schematic diagram of step S16 according to the embodiment of the present disclosure.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The embodiment of the disclosure provides a passive filter and a preparation method thereof. As shown in fig. 1, fig. 1 is a schematic cross-sectional view of a passive filter in an embodiment of the disclosure. The passive filter in the embodiment of the present disclosure includes: the capacitor comprises a dielectric substrate 1, at least one capacitor C and at least one inductor; the dielectric substrate 1 comprises a slot 6 arranged along the thickness direction of the dielectric substrate 1; the inner wall of the slot 6 comprises a first part, and the extension direction of the tangent of at least part of points on the first part is intersected with the extension direction of the plane of the medium substrate 1; the capacitor C comprises a first polar plate 2, a first interlayer dielectric layer 3 and a second polar plate 4 which are sequentially arranged in the direction departing from the dielectric substrate 1; the orthographic projection overlapping part of the first polar plate 2 of the capacitor C, the second polar plate 4 of the capacitor C and the first interlayer dielectric layer 3 on the dielectric substrate 1 at least covers the first part.
Specifically, referring to fig. 1, in the embodiment of the present disclosure, since the slot 6 is provided, and the first portion in the inner wall of the slot 6 extends in a direction intersecting with a plane in which the dielectric substrate 1 is located, at least a part of a tangent line of a point extends, that is, the first portion in the slot 6 has a component perpendicular to the surface direction of the dielectric substrate 1. In the passive filter shown in fig. 1, the first part, i.e. the part of the first plate of the capacitor, covers the inner wall of the slot. The part of the capacitor C where the orthographic projections of the first plate 2, the second plate 4 and the first interlayer dielectric layer 3 on the dielectric substrate 1 are overlapped is the part of the capacitor C which accumulates charges during actual operation, i.e. the part which actually forms a capacitor structure. When the part actually forming the capacitor structure covers the first part in the inner wall of the slot 6, the capacitor C now also has a component perpendicular to the dielectric substrate 1 along its surface, since the first part has a component perpendicular to the dielectric substrate 1 along its surface. When the capacitance value of the capacitor C is constant, because the capacitor C has a component perpendicular to the thickness direction of the dielectric substrate 1, compared with the conventional capacitor C which is directly horizontally arranged on the surface of the dielectric substrate 1, the area occupied by the capacitor C on the dielectric substrate 1 along the surface direction is reduced. Because the area occupied by the capacitor C on the dielectric substrate 1 along the surface direction is reduced, more capacitors C can be arranged on the dielectric substrate 1 with the same size, and the density of the capacitors C in the passive filter is improved. Meanwhile, for the capacitor C with a certain capacitance value, the occupied area of the capacitor C on the dielectric substrate 1 along the surface direction of the dielectric substrate can be reduced, the overall size of the passive filter is reduced, and the integration level of the passive filter is improved.
In some embodiments, with continued reference to fig. 1, the orthographic projections of the first plate 2 of the capacitor C, the second plate 4 of the capacitor C, and the first interlayer dielectric layer 3 on the dielectric substrate 1 overlap to completely cover the inner wall of the slot 6, where the inner wall of the slot includes at least the first portion. In the embodiment of the present disclosure, the overlapping portion of the orthographic projections of the first plate 2, the second plate 4 and the first interlayer dielectric layer 3 of the capacitor C on the dielectric substrate 1 is the portion of the capacitor C that accumulates charges during actual operation, that is, the portion actually forming the capacitor structure, that is, the capacitor structure completely covers the inner wall of the slot 6. At this time, the surface area of the slot 6 can be calculated by the structure of the slot 6, the surface areas of the first polar plate 2 and the second polar plate 4 of the capacitor C can be calculated by the surface area of the slot 6, and finally the capacitance value of the capacitor C can be calculated. In this way, the capacitance value of the capacitor C in the passive filter can be set more simply. It should be noted that, in some embodiments, a plurality of capacitors C may be disposed on the inner wall of the slot 6 according to an actually required capacitance value, and each of the plurality of capacitors C completely covers the inner wall of the slot 6, which is also within the protection scope of the embodiments of the present disclosure.
In some embodiments, as shown in fig. 1, the slot 6 may be a blind slot. The possibility of short circuit between the capacitor C and the conductive structure arranged on the surface of the dielectric substrate 1 is reduced through the method. In some embodiments, the blind slot may be one including, but not limited to: a hemispherical blind groove, a cylindrical blind groove and a cubic blind groove. In the embodiment of the present disclosure, when the open groove 6 is a hemispherical blind groove, the first portion may be any portion of the inner wall of the hemispherical blind groove, for example: the first part can be the whole structure of the inner wall of the hemispherical blind groove or the partial structure of the inner wall of the hemispherical blind groove; when the slot 6 is a cylindrical blind slot, the first portion may comprise at least part of the side wall of the cylindrical blind slot, for example: the first part can be the whole structure of the side wall and the bottom wall of the cylindrical blind groove, the whole structure of the side wall and the partial structure of the bottom wall of the cylindrical blind groove, or only the partial structure of the side wall of the cylindrical blind groove; when the slot 6 is a cubic blind slot, the first portion may be at least part of a cubic blind slot sidewall. For example: the first portion may be the full structure of the side walls and the bottom wall of the cubic blind groove, the full structure of the side walls and the partial structure of the bottom wall of the cubic blind groove, or only the partial structure of the side walls of the cubic blind groove. It should be noted that the blind groove of the embodiment of the present disclosure is not limited thereto, and for example, an irregular shape recessed blind groove may also be used, and all of them are within the scope of the embodiment of the present disclosure. In some embodiments, it is preferable that the blind groove on the dielectric substrate 1 may be a hemispherical blind groove, and the blind groove with this structure is simple in preparation process. Therefore, in the embodiment of the present disclosure, only the blind groove on the dielectric substrate 1 is taken as a hemispherical blind groove for example.
Specifically, referring to fig. 2A, when the radius of the hemispherical blind groove is R, the surface area of the hemispherical blind groove is S1＝2πR2Therefore, the capacitance value of the capacitor C completely covering the inner wall of the slot 6 is C0＝ε0*ε*2πR2Where d is the thickness of the dielectric layer, ε is the relative dielectric constant of the dielectric layer, ε0The dielectric constant of a vacuum. And the area of the capacitor C in the region occupied by the dielectric substrate 1 along the surface direction is S2＝πR2. If there is no blind trench structure, referring to fig. 2B, the capacitance value of the capacitor structure disposed in the region is C1＝ε0*ε*πR2And d. Therefore, in the embodiment of the present disclosure, in a manner that the capacitor C completely covers the inner wall of the slot 6, the capacitance value of the capacitor C is doubled under the condition that the dielectric substrate 1 occupies the same area along the surface direction. Therefore, for the capacitor C with a certain capacitance value, the area of the capacitor C occupied by the dielectric substrate 1 along the surface direction thereof can be reduced by reducing the radius of the hemispherical blind groove, the overall size of the passive filter is reduced, and the integration level of the passive filter is improved.
In some embodiments, the dielectric substrate 1 further includes a first connecting via 5 penetrating in a thickness direction thereof and a first surface and a second surface oppositely disposed in the thickness direction; the inductor comprises a first substructure 7 arranged on the first surface of the dielectric substrate 1, a second substructure 8 arranged on the second surface of the dielectric substrate 1, and a first connection electrode 9 arranged in the first connection via 5, and the first connection electrode 9 connects the first substructure 7 and the second substructure 8; the inductor is electrically connected with the capacitor C.
Specifically, in the embodiment of the present disclosure, referring to fig. 3, fig. 3 is a top view of an inductor according to the embodiment of the present disclosure. Each first substructure 7 of the inductor extends along a first direction and is arranged side by side along a second direction; each second substructure 8 of the inductor extends in the third direction and is arranged side by side in the second direction. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction are intersected and non-perpendicular to each other. Of course, the extending directions of the first substructure 7 and the second substructure 8 may be interchanged, all within the scope of the embodiments of the present disclosure. In addition, in the present embodiment, the inductor includes N first sub-structures 7 and N-1 second sub-structures 8 as an example, where N ≧ 2 and N are integers. The first end and the second end of the first substructure 7 each at least partially overlap with a first connecting via 5 in an orthographic projection on the glass substrate. And the first end and the second end of one first substructure 7 correspond to different first connecting vias 5, i.e. one first substructure 7 at least partially overlaps two first connecting vias 5 in an orthographic projection on the glass substrate. At this time, the first end of the ith second substructure 8 of the inductor is connected with the first end of the ith first substructure 7 and the second end of the (i + 1) th first substructure 7 to form an inductor coil, wherein i is greater than or equal to 1 and less than or equal to N-1, and i is an integer.
It should be noted that the first lead terminal 10 is connected to the second terminal of the first substructure 7 of the inductor, and the second lead terminal 11 is connected to the first terminal of the nth first substructure 7. Further, the first lead terminal 10 and the second lead terminal 11 may be disposed on the same layer as the second sub-structure 8 and made of the same material, and at this time, the first lead terminal 10 may be connected to the second terminal of the first sub-structure 7 through the first connecting via 5, and correspondingly, the second lead terminal 11 may be connected to the first terminal of the nth first sub-structure 7 through the first connecting via 5.
In some embodiments, the inductance in the passive filter is multiple, the multiple inductances including a first inductance L1 and a second inductance L2. The passive filter comprises a first conductive layer comprising the first substructure 7 of the first inductance L1, the first substructure 7 of the second inductance L2 and the first plate 2 of the capacitance C. The passive filter further comprises a second conductive layer comprising the second substructure 8 of the first inductance L1 and the second substructure 8 of the second inductance L2. And the first lead terminal 10 of the first inductor L1 is connected to the first plate 2 of the capacitor C, and the second lead terminal 11 of the second inductor L2 is connected to the first plate 2 of the capacitor C.
In the disclosed embodiment, referring to fig. 4 in particular, fig. 4 is a circuit diagram of the passive filter shown in fig. 1, and referring to fig. 4, the passive filter at least includes a first inductor L1, a second inductor L2, and a capacitor C. The second lead terminal 11 of the first inductor L1 is connected to the signal Input terminal Input, and the first lead terminal 10 of the first inductor L1 is connected to the first plate 2 of the first capacitor C and the second lead terminal 11 of the second inductor L2. The second lead terminal 11 of the second inductor L2 is connected to the first lead terminal 10 of the first inductor L1 and the first plate 2 of the first capacitor C, and the first lead terminal 10 of the second inductor L2 is connected to the signal Output terminal Output. The first plate 2 of the capacitor C is connected to the first lead terminal 10 of the first inductor L1 and the second lead terminal 11 of the second inductor L2, and the second plate 4 of the capacitor C is connected to the ground GND. Through this kind of connected mode, realize passive filter's basic structure. It should be noted that the passive filter of the present disclosure is described by taking only the example including the first inductor L1, the second inductor L2, and the capacitor C, and a passive filter including passive devices such as a plurality of inductors or a plurality of capacitors is also within the scope of the present disclosure.
In the embodiment of the present disclosure, in order to more clearly illustrate the specific structure of the passive filter shown in fig. 4, the structure of each film layer of the passive filter is described. With particular continued reference to fig. 1, the passive filter includes a dielectric substrate 1, and a capacitor C, a first inductor L1 and a second inductor L2 are integrated on the dielectric substrate 1. The dielectric substrate 1 includes a blind via and a first connecting via 5 provided along a thickness direction thereof, and a first surface and a second surface oppositely provided along the thickness direction thereof. A first connecting electrode 9 is arranged in the first connecting via hole 5, a first conductive layer is arranged on the first surface of the dielectric substrate 1, and a second conductive layer is arranged on the second surface of the dielectric substrate 1. The first conductive layer comprises the first substructure 7 of the first inductance L1, the first substructure 7 of the second inductance L2 and the first plate 2 of the capacitor C. The second conductive layer comprises the second substructure 8 of the second inductance L2 and the second substructure 8 of the first inductance L1. In this way, the first substructure 7 of the first inductor L1, the first substructure 7 of the second inductor L2, and the first plate 2 of the capacitor C are formed in one patterning process, and the first substructure 7 of the first inductor L1 and the first substructure 7 of the second inductor L2 are formed in one patterning process. And the first substructure 7 of the first inductor L1 and the second substructure 8 of the first inductor L1 are connected by the first connecting electrode 9 to form an inductor structure as shown in fig. 3; the first substructure 7 of the second inductor L2 and the second substructure 8 of the second inductor L2 form an inductor structure as shown in fig. 3 by means of the first connection electrode 9. The first lead terminal 10 of the first inductor L1 is connected to the first plate 2 of the capacitor C, and the second lead terminal 11 of the second inductor L2 is connected to the first plate 2 of the capacitor C. The first polar plate 2 of the capacitor C, the first interlayer dielectric layer 3 and the second polar plate 4 of the capacitor C are sequentially arranged on one side, away from the medium, of the first surface of the dielectric substrate 1. The orthographic projection overlapping parts of the first polar plate 2 of the capacitor C, the first interlayer dielectric layer 3 and the second polar plate 4 of the capacitor C on the dielectric substrate 1 completely cover the inner wall of the blind slot.
In some embodiments, with continued reference to fig. 1, an orthographic projection of the first interlayer dielectric layer 3 on the dielectric substrate 1, and an orthographic projection of the first plate 2 covering the first substructure 7 and the capacitor C on the dielectric substrate 1. In this way, the first interlayer dielectric layer 3 of the capacitor C is used as an interlayer insulating layer in the passive filter to protect the first inductor L1, the second inductor L2 and the capacitor C from water and oxygen. The passive filter further comprises: the second interlayer dielectric layer 12 is arranged on one side of the first interlayer dielectric layer 3 and the second plate 4 of the capacitor C, which is far away from the dielectric substrate 1, the third interlayer dielectric layer 13 is arranged on one side of the second interlayer dielectric layer 12, which is far away from the dielectric substrate 1, and the first connecting pad 14, the second connecting pad 15 and the third connecting pad 16 are arranged on one side, which is far away from the second dielectric layer. The second interlayer dielectric layer 12 and the third interlayer dielectric layer 13 are respectively used as a planarization layer on the first surface side of the dielectric substrate 1 and a planarization layer on the second surface side of the dielectric substrate 1, so as to planarize the film layer on the first surface side of the dielectric substrate 1 and the film layer on the second surface side of the dielectric substrate 1. The first connection pad 14 is connected to the second sub-structure 8 by a second connection via passing through the first interlayer dielectric layer 3 and the second interlayer dielectric layer 12. The second connection pad 15 is connected to the second substructure 8 by a third connection via that penetrates through the first and second interlayer dielectric layers 3 and 12. The third connection pad 16 is connected to the second plate 4 of the capacitor C through a fourth connection via penetrating the second interlayer dielectric layer 12. The first connection pad 14 may be a signal Input terminal, the second connection pad 15 may be a signal Output terminal, and the third connection pad 16 may be a ground terminal GND. It should be noted that, in some embodiments, the first connection pad 14 and the second connection pad 15 may be interchanged, that is, the first connection pad 14 is the signal Output terminal Output, and the second connection pad 15 is the signal Input terminal Input, and also fall within the protection scope of the present disclosure.
In some embodiments, the dielectric substrate 1 includes, but is not limited to, any one of a glass-based, a silicon-based, a flexible substrate, an interlayer dielectric layer including at least an organic insulating layer. Since the integrated circuit has the advantages of small size, light weight, high performance, low power consumption, etc. when the integrated circuit is integrated on a glass substrate, the dielectric substrate 1 in the embodiment of the present disclosure is a glass substrate. The following description will be given only by taking the dielectric substrate 1 as a glass substrate.
In some embodiments, the passive filter of embodiments of the present disclosure may be applied in an integrated filter, as shown in fig. 5. Referring specifically to fig. 5, the integrated filter shown in fig. 5 includes a passive filter, an rf sub-circuit 17 and a package carrier 18. The first connection pad 14, the second connection pad 15 and the third connection pad 16 in the passive filter are connected to corresponding signal terminals on the package carrier 18, and the connection signal terminals in the rf sub-circuit 17 are connected to corresponding signal terminals on the package carrier 18, so as to form a complete integrated filter. The integrated filter may be a radio frequency front end device. The application field of the radio frequency identification device is almost all over all radio frequency directions, including 5G communication, vehicle-mounted radar and the like. It should be noted that the integrated filter shown in fig. 5 is only illustrated by taking a passive filter and a radio frequency sub-circuit 17 as an example, and an integrated filter including a plurality of passive filters and a plurality of radio frequency sub-circuits 17 is also within the scope of the present disclosure.
The structural parameters of the components of the passive filter according to the embodiment of the present disclosure are explained one by one in the following manufacturing method, and thus will not be described in detail here.
Specifically, an embodiment of the present disclosure provides a method for manufacturing a passive filter, where the passive filter may be the substrate described above, and the method includes the following steps:
providing a dielectric substrate 1, wherein the dielectric substrate 1 comprises a slot 6 arranged along the thickness direction of the dielectric substrate 1; the inner wall of the slot 6 comprises a first part, and the extension direction of the tangent of at least part of points on the first part is intersected with the extension direction of the plane of the medium substrate 1;
forming at least one capacitor C and at least one inductor; the step of forming the capacitor C comprises:
a first polar plate 2 of a capacitor C, a first interlayer dielectric layer 3 and a second polar plate 4 of the capacitor C are sequentially formed on one side of the dielectric substrate 1; the orthographic projection of the first plate 2 of the capacitor C, the second plate 4 of the capacitor C and the first interlayer dielectric layer 3 on the dielectric substrate 1 is overlapped to at least cover the first part.
In order to clarify the manufacturing method in the embodiments of the present disclosure, the following describes a manufacturing method of a passive filter in the embodiments of the present disclosure with reference to the drawings and specific embodiments. The steps in which the passive filter is formed are shown in fig. 6.
S10, providing a dielectric substrate 1, and processing the dielectric substrate 1 to form the slot 6 and the first connection via hole 5, as shown in fig. 7.
In some embodiments, the dielectric substrate 1 selected in step S10 is glass-based, and the formed slot 6 may be a blind slot. Specifically, as shown in fig. 8, step S10 may include the following steps;
and S101, the medium substrate 1 enters a cleaning machine for cleaning.
In some embodiments, the dielectric substrate 1 has a thickness of about 0.3mm to 2 mm.
And S102, gluing the first surface of the dielectric substrate 1, and exposing and developing.
In some embodiments, the photoresist 19 is uniformly applied on the dielectric substrate 1 to the first surface of the dielectric substrate 1, as shown in fig. 9. And the photoresist 19 where the first connection through holes 5 and the blind recesses are preformed is exposed by light. The photosensitive photoresist 19 is removed by chemical means and the non-photosensitive photoresist 19 is cured. Finally the first surface where the first connection through holes 5 and the blind recesses are preformed is exposed to the environment, as shown in fig. 10.
And S103, performing laser modification on the first surface of the dielectric substrate 1.
In some embodiments, laser modification is performed on the first surface exposed in the external environment in step S102 at a position corresponding to the preformed first connection via 5, so that anisotropic etching may be performed on the first surface at a position corresponding to the preformed first connection via 5, and isotropic etching is performed on the first surface at the preformed blind slot. By the method, the first connecting through hole 5 and the blind groove can be formed simultaneously by adopting a one-time etching process, and the process is simple.
In some embodiments, when the precision of the laser is sufficiently high, the order of step S103 and step S102 may be interchanged.
S104, forming a blind via and a first connection via 5 by an etching process, as shown in fig. 11.
In some embodiments, the dielectric substrate 1 processed in step S103 is etched by using an isotropic etching liquid. Since the first surface where the first connecting via hole 5 is formed can be anisotropically etched by laser processing, the etching speed of the dielectric substrate 1 in the longitudinal direction thereof is much greater than that in the horizontal plane, and finally the first connecting via hole 5 in the thickness direction of the dielectric substrate 1 is formed. Meanwhile, isotropic etching is carried out at the position where the blind groove is formed, so that the etching speed of the dielectric substrate 1 at the position along each direction is basically the same, and finally, a hemispherical blind groove can be formed. In this way, the first connecting via hole 5 and the blind via are formed in one etching process. And the formed blind groove is a hemispherical blind groove, so that the capacitor C is easily formed on the side wall of the blind groove, the capacitance value is easy to calculate, and the design of the passive filter is facilitated.
It should be noted that in some embodiments, the blind grooves may be formed by partially etching isotropically and partially anisotropically, in which different structures of the blind grooves may be formed.
And S105, removing the photoresist 19 on the surface of the dielectric substrate 1.
This completes the preparation of step S10. The first connecting through hole 5 and the blind groove formed in the mode have simple and mature process and are easy to prepare.
It should be noted that in some embodiments, the first connection through-hole 5 and the slot 6 may be formed by different punching processes and in different steps, respectively. For example: in some embodiments, the first connection through hole 5 may be prepared by: mechanical punching, laser punching, dry etching, wet etching and the like. In some embodiments, slot 6 may be prepared by: mechanical punching, laser punching, dry etching, wet etching and the like. In some embodiments, the gouging 6 and the first connecting via 5 may be formed by forming the gouging 6 and then forming the first connecting via 5, or by forming the first connecting via 5 and then forming the gouging 6, which are all within the scope of the embodiments of the present disclosure. Also, in some embodiments, the slot 6 and the first connection through hole 5 may be formed using the same manufacturing method, respectively, or may be formed using different manufacturing methods, respectively, which are within the scope of the embodiments of the present disclosure.
S11, forming the first connection electrode 9 in the first connection through-hole 5, as shown in fig. 12.
In some embodiments, step S11 may specifically include the following steps:
(1) growing a seed layer: depositing a first metal material on the first surface of the dielectric substrate 1 by means of magnetron sputtering, turning the dielectric substrate 1 over, and depositing the first metal material on the second surface by means of magnetron sputtering, wherein the first metal material is formed on the sidewall of the first connection via hole 5 as a seed layer.
In some embodiments, the first metal material includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal material is about 0.2 μm to 10 μm. In the following description, the material of the first metal film 201 is copper as an example.
In some embodiments, to increase the adhesion of the first metal material to the first surface of the glass substrate 10, an auxiliary metal film layer may be formed on the first surface of the glass substrate 10 by means including, but not limited to, magnetron sputtering prior to forming the first metal material. The auxiliary metal film layer is made of at least one of nickel (Ni), molybdenum (Mo) alloy and titanium (Ti) alloy, for example, MoNb is adopted, and the thickness of the auxiliary metal film layer is about 2nm-20 nm.
(2) Electroplating: putting the dielectric substrate 1 on an electroplating machine carrier, pressing a power-on pad (pad), putting the dielectric substrate into a hole-filling electroplating bath (special hole-filling electrolyte is used in the bath), applying current, keeping the electroplating solution continuously and rapidly flowing on the first surface of the dielectric substrate 1, obtaining electrons from cations in the electroplating solution on the inner wall of the first connecting through hole 5 to form atoms to be deposited on the inner wall, and depositing metal copper (with the deposition speed of 0.5-3um/min) in the first connecting through hole at a high speed mainly through the special hole-filling electrolyte with special proportion, wherein the first surface and the second surface of the dielectric substrate 1 are flat areas, and the deposition speeds of the metal copper on the two surfaces are extremely small (0.005-0.05 um/min). With the increase of time, the metal copper on the inner wall of the first connecting via hole 5 gradually grows to be thick to form a first metal film layer, and at the moment, the first metal film layer grows more than 5 microns compared with the first metal material. At this time, the first connection via 5 is filled with the first metal film layer.
In some embodiments, the first metal film layer may not fill the first connection via 5, and a filling structure is formed in the first connection via 5 to support the film layer structure on the dielectric substrate 1. The material of the filling structure may include an organic insulating material including, for example, resin-based materials such as polyimide, epoxy, acryl, polyester, photoresist, polyacrylate, polyamide, siloxane, and the like. As another example, the organic insulating material includes an elastic material, such as urethane, Thermoplastic Polyurethane (TPU), or the like.
It should be noted that, in the embodiment of the present disclosure, the first metal film layer is taken as an example to fill the first connection via 5.
S12, forming the first substructure 7 and the first plate 2 of the capacitor C, as shown in fig. 13.
Depositing a second metal film layer on the first surface of the dielectric substrate 1 and in the blind groove, gluing, exposing and developing the second metal film layer, then etching, removing the glue from the strip after etching, and completing patterning of the second metal film layer, thereby forming a first conductive layer comprising the first substructure 7 of the first inductor L1, the first substructure 7 of the second inductor L2, and the first plate 2 of the capacitor C. In the disclosed embodiment, the first plate 2 of the capacitor C completely covers the side wall of the blind via.
S13, forming a first interlayer dielectric layer 3, and forming a pattern of the second plate 4 of the capacitor C on the side of the first interlayer dielectric layer 3 away from the dielectric substrate 1, as shown in fig. 14.
In some embodiments, the material of the first interlayer dielectric layer 3 is an inorganic insulating material. For example: the first interlayer dielectric layer 3 is an inorganic insulating layer formed of silicon nitride (SiNx) or silicon oxide (SiO)2) Inorganic insulating layer formed, or SiNx inorganic insulating layer and SiO2Several stacked composite layers of inorganic insulating layers. In some embodiments, the first interlayer dielectric layer 3 covers the first substructure 7 of the first inductor L1, the first substructure 7 of the second inductor L2, and the first plate 2 of the capacitor C, so that it functions as an interlayer dielectric layer of the capacitor C and also as an interlayer insulating layer of the passive filter to protect the structure between the first interlayer dielectric layer 3 and the dielectric substrate 1 from water and oxygen.
In some embodiments, the second plate 4 of the capacitor C may form a third metal film layer on the side of the first interlayer dielectric layer 3 away from the dielectric substrate 1 by magnetron sputtering, then perform glue coating, exposure, development, and wet etching, and strip photoresist removal after etching is performed to form a pattern including the second plate 4 of the capacitor C.
S14, forming a second interlayer dielectric layer 12 on a side of the second plate 4 of the capacitor C away from the dielectric substrate 1, and forming a second connection via penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer 12, a third connection via penetrating through the second interlayer dielectric layer 12, and a fourth connection via penetrating through the second interlayer dielectric layer 12, as shown in fig. 15.
The material of the second interlayer dielectric layer 12 may be the same as the material of the first interlayer dielectric layer 3, and therefore, the detailed description thereof is not repeated here. The second connecting via hole at least partially overlaps with the orthographic projection of the second lead terminal 11 of the first inductor L1 on the dielectric substrate 1, the third connecting via hole at least partially overlaps with the orthographic projection of the first lead terminal 10 of the second inductor L2 on the dielectric substrate 1, and the fourth connecting via hole at least partially overlaps with the orthographic projection of the second plate 4 of the capacitor C on the dielectric substrate 1.
S15, the dielectric substrate 1 is turned over, and a pattern including the second substructure 8 is formed through a patterning process, as shown in fig. 16.
In some embodiments, step S15 may include forming a fourth metal film layer on the second surface of the dielectric substrate 1 by magnetron sputtering, then performing glue coating, exposure, development, and subsequent etching, and strip removing the glue after the etching is completed to form the second conductive layer including the pattern of the second substructure 8 of the first inductor L1 and the pattern of the second substructure 8 of the second inductor L2.
Wherein the thickness of the fourth metal film layer is more than 5 μm. The material of the fourth metal film layer may be the same as that of the first metal film layer, and thus, the description thereof is omitted.
S16, forming a third interlayer dielectric layer 13 on the side of the second substructure 8 facing away from the dielectric substrate 1, as shown in fig. 17.
In some embodiments, the material of the third interlayer dielectric layer 13 may be the same as the material of the second interlayer dielectric layer 12, and thus, the detailed description thereof is not repeated.
S17, the dielectric substrate 1 is turned over again, and the first connection pad 14, the second connection pad 15 and the third connection pad 16 are formed in the second connection via, the third connection via and the fourth connection via, respectively. Among them, the first connection pad 14, the second connection pad 15, and the third connection pad 16 may be solder.
Thus, the preparation of the passive filter is completed.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims (15)

1. A passive filter, comprising: the capacitor comprises a dielectric substrate, at least one capacitor and at least one inductor; the dielectric substrate comprises a slot arranged along the thickness direction of the dielectric substrate; the inner wall of the slot comprises a first part, and the extension direction of a tangent line of at least part of points on the first part is intersected with the extension direction of a plane of the medium substrate;
the capacitor comprises a first polar plate, a first interlayer dielectric layer and a second polar plate which are sequentially arranged in a direction deviating from the direction of the dielectric substrate; the first plate of the capacitor, the second plate of the capacitor and the orthographic projection overlapping part of the first interlayer dielectric layer on the dielectric substrate at least cover the first part.
2. The passive filter according to claim 1, wherein the dielectric substrate further includes a first connection via penetrating in a thickness direction thereof and a first surface and a second surface disposed opposite to each other in the thickness direction;
the inductor comprises a first substructure arranged on the first surface of the dielectric substrate, a second substructure arranged on the second surface of the dielectric substrate, and a first connection electrode arranged in the first connection via, wherein the first connection electrode connects the first substructure and the second substructure; the inductor is electrically connected with the capacitor.
3. The passive filter of claim 2, wherein the inductor is plural, the plural inductors including a first inductor and a second inductor;
the passive filter includes a first conductive layer; the first conducting layer comprises a first substructure of the first inductor, a first substructure of the second inductor, and a first plate of the capacitor;
the passive filter includes a second conductive layer; the second conductive layer comprises a second substructure of the first inductor and a second substructure of the second inductor;
and the first lead end of the first inductor is connected with the first pole plate of the capacitor, and the second lead end of the second inductor is connected with the first pole plate of the capacitor.
4. The passive filter of claim 3, wherein an orthographic projection of the first interlayer dielectric layer on the dielectric substrate covers the orthographic projection of the first substructure and the first plate of the capacitor on the dielectric substrate;
the passive filter further comprises: the second interlayer dielectric layer is arranged on one side, away from the dielectric substrate, of the first interlayer dielectric layer and the second plate of the capacitor; the third interlayer dielectric layer is arranged on one side, away from the dielectric substrate, of the second interlayer dielectric layer; the first connecting pad, the second connecting pad and the third connecting pad are arranged on one side departing from the second dielectric layer;
the first connecting bonding pad is connected with a second lead end of the first inductor through a second connecting through hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer;
the second connecting pad is connected with the first lead end of the second inductor through a third connecting through hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer;
and the third connecting bonding pad is connected with the second plate of the capacitor through a fourth connecting through hole penetrating through the second interlayer dielectric layer.
5. The passive filter of claim 1, wherein the slot is a blind slot.
6. The passive filter of claim 5, wherein the blind slots comprise hemispherical blind slots, cylindrical blind slots, and cubic blind slots.
7. The passive filter of claim 1, wherein the overlapping portions of the orthographic projections of the first plate of the capacitor, the second plate of the capacitor, and the first interlayer dielectric layer on the dielectric substrate completely cover the inner walls of the slot.
8. A passive filter according to any of claims 1-7, characterized in that the dielectric substrate comprises a glass-or silicon-based substrate.
9. The preparation method of the passive filter is characterized by providing a dielectric substrate, wherein the dielectric substrate comprises a slot arranged along the thickness direction of the dielectric substrate; the inner wall of the slot comprises a first part, and the extension direction of a tangent line of at least part of points on the first part is intersected with the extension direction of a plane of the medium substrate;
forming at least one capacitor and at least one inductor; the step of forming the capacitor comprises:
forming a first polar plate of the capacitor, a first interlayer dielectric layer and a second polar plate of the capacitor in sequence on one side departing from the dielectric substrate; the first polar plate of the capacitor, the second polar plate of the capacitor and the orthographic projection overlapped part of the first interlayer dielectric layer on the dielectric substrate cover the first part.
10. The method of manufacturing of claim 9, wherein the open slots comprise blind slots; the dielectric substrate comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the dielectric substrate;
the providing a dielectric substrate includes: and forming the blind groove on the first surface of the dielectric substrate along the thickness direction of the dielectric substrate.
11. The method of claim 9, wherein providing a dielectric substrate further comprises: and forming a first connecting through hole in the dielectric substrate along the thickness direction of the dielectric substrate.
12. The method of claim 11, wherein an etching process forms the first connecting via and the moat.
13. The method of claim 12, wherein the step of forming the first connecting via and the blind via comprises:
carrying out laser modification on the dielectric substrate; so that when the medium substrate is subjected to the primary etching process, the medium substrate can be subjected to the isotropic etching and the anisotropic etching simultaneously; and forming the slot and the first connecting through hole by one-time etching process.
14. The method of manufacturing of claim 11 or 12, wherein the step of forming at least one of the inductors further comprises forming a first inductor and a second inductor;
the step of forming the first inductor and the second inductor comprises:
forming a first connection electrode in the first connection via; the medium substrate comprises a first surface and a second surface which are oppositely arranged; forming a first substructure of the first inductor and a first substructure of the second inductor on the first surface of the dielectric substrate; forming a second substructure of the first inductor and a second substructure of the second inductor on the second surface of the dielectric substrate; the first substructure of the first inductor, the second substructure of the first inductor and the first connection electrode constitute a coil structure of the first inductor; the first substructure of the second inductor, the second substructure of the second inductor, and the first connection electrode constitute a coil structure of the second inductor.
15. The method of manufacturing according to claim 14, further comprising: forming a second interlayer dielectric layer on one side of the dielectric substrate, which is far away from the first surface, and forming a second connecting through hole and a third connecting through hole which penetrate through the first interlayer dielectric layer and the second interlayer dielectric layer, and a fourth connecting through hole which penetrates through the second interlayer dielectric layer; forming a third interlayer dielectric layer on one side of the dielectric substrate, which is far away from the second surface;
the method for preparing the substrate further comprises: forming a first connecting pad, a second connecting pad and a third connecting pad on one side departing from the second interlayer dielectric layer;
the first connection pad is connected with the first substructure of the first inductor through the second connection via hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer; the second connection pad is connected with the first substructure of the second inductor through a third connection via hole penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer; and the third connecting bonding pad is connected with the second plate of the capacitor through a fourth connecting through hole penetrating through the second interlayer dielectric layer.
CN202210111884.2A 2022-01-29 2022-01-29 Passive filter and preparation method thereof Pending CN114497027A (en)

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