CN109473405A - A kind of the fan-out-type wafer level packaging structure and its method of silicon etching through-hole - Google Patents
A kind of the fan-out-type wafer level packaging structure and its method of silicon etching through-hole Download PDFInfo
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- CN109473405A CN109473405A CN201811494478.9A CN201811494478A CN109473405A CN 109473405 A CN109473405 A CN 109473405A CN 201811494478 A CN201811494478 A CN 201811494478A CN 109473405 A CN109473405 A CN 109473405A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- Engineering & Computer Science (AREA)
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- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
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Abstract
The invention discloses a kind of fan-out-type wafer level packaging structures of silicon etching through-hole, comprising: chip；Block of dielectric material, the block of dielectric material and the chip by chip；Capsulation material, the capsulation material encapsulates the chip and the block of dielectric material, wherein the chip has first surface and second surface, there are active area and at least two pads on the first surface, there is salient point on each pad, the top surface of the salient point, the top surface of block of dielectric material and the top surface of capsulation material flush, constitute a plane, the first conducting wire is provided on the top surface of the salient point and the top surface of capsulation material, the second conducting wire and/or device are provided on the top surface of block of dielectric material, first conducting wire is electrically connected with second conducting wire and/or device.
Description
Technical field
The embodiment of the present invention is related to semiconductor packaging.Specifically, the present invention relates to a kind of silicon etching through-holes
Fan-out-type wafer level packaging structure and method.
Background technique
With the trend of electronic product multifunction and miniaturization, high density microelectronic mounting technology is produced in electronics of new generation
Mainstream is increasingly becoming on product.In order to cooperate the development of electronic product of new generation, especially smart phone, palm PC, ultrabook
The development of equal products, the size of chip is higher to density, speed faster, smaller, the more low direction of cost develops.Fan-out-type
The appearance of Board level packaging technology (Fanout Panel Level Package, F0PLP), as fan-out-type Wafer level packaging
The upgrade technique of (Fanout Wafer Level Package, F0WLP), possesses broader development prospect.
In high frequency electronic equipment, the copper sheet of circuit the preceding paragraph special shape also may be constructed an inductance, capacitor or electricity
This device, is usually called passive device by resistance etc..Intelligent series of products acceptance and use modern times for greatly improving of degree
Society, the production capacity of high frequency passive device are also surging therewith.With the development of miniaturization of electronic products, the nothings such as inductance, capacitor, antenna
The volume of source device has been reduced to physics limit.The developing direction of the following passive device be it is integrated, provide for client convenient for making
Holonomic system.Miniaturization will be the direction of most of electronic equipment, we have seen that touch-screen mobile phone, liquid crystal electricity
Depending on the lightening trend of, tablet computer, therefore, passive device is frivolous small-sized, high as component indispensable in circuit system
It is inevitable trend that effect is integrated.
Existing integrated fan-out-type InFO (Integrated Fan-Out) encapsulation scheme, encapsulation are mostly packaged in single side
Wiring, signal line is all only in the single side of encapsulation.Low frequency signal and high-frequency signal all pass through a plane routing, often signal it
Than more serious, the integrality of signal is relatively difficult to ensure for preceding mutual crosstalk.
In addition, InFO encapsulation scheme, is routed mostly on plastic packaging organic material, capsulation material is as dielectric material.It is limited
In the material property of organic material, such as conductivity, dielectric constant, loss angle, often it is limited in some applications larger.It can not
Realize certain opering characteristics of electric apparatus.Such as high Q value inductance, capacitor, Antenna Design etc..
Therefore, this field needs a kind of fan-out-type wafer level packaging structure and its method suitable for high-frequency signal
Summary of the invention
Aiming at the problems existing in the prior art, the present invention proposes a kind of RDL wiring based on TSV, by the non-high frequency in part
Signal is directed to the back of encapsulation, realizes arranged apart, the reduction signal cross-talk of high-frequency signal and low frequency signal.
According to an aspect of the present invention, a kind of fan-out-type wafer level packaging structure of silicon etching through-hole is provided, comprising:
Chip；
Block of dielectric material, the block of dielectric material and the chip by chip；
Capsulation material, the capsulation material encapsulate the chip and the block of dielectric material,
Wherein the chip has first surface and second surface, has active area and at least two on the first surface
A pad, has salient point on each pad, and the top surface of the top surface of the salient point, the top surface of block of dielectric material and capsulation material is neat
It is flat, a plane is constituted, is provided with the first conducting wire, block of dielectric material on the top surface of the salient point and the top surface of capsulation material
Top surface on be provided with the second conducting wire and/or device, first conducting wire and second conducting wire and/or device
Part electrical connection,
The second surface is opposite with the first surface, and the second surface is flushed with the back side of capsulation material, and again
Wiring layer and external pad are distributed on the back side of second surface and capsulation material, and described second, which reroutes layer, passes through one or more
A hole TSV is electrically connected with one or more formed in the salient point, and wherein the hole TSV extends to corresponding salient point from second face
Pad, and the hole TSV inside be filled with conductive metal.
In one embodiment of the invention, the salient point includes believing for the salient point of high frequency signal transmission and for low frequency
Number transmission salient point.
In one embodiment of the invention, the fan-out-type wafer level packaging structure of silicon etching through-hole further includes being arranged in institute
State the soldered ball on external pad.
In one embodiment of the invention, second conducting wire is high-frequency signal line.
In one embodiment of the invention, the device is inductance, capacitor or antenna.
In one embodiment of the invention, block of dielectric material is low conductivity material.
According to another embodiment of the invention, a kind of system of the fan-out-type wafer level packaging structure of silicon etching through-hole is provided
Make method, comprising:
Chip to be packaged is provided, the chip has first surface and second surface, have on first surface active area with
And at least two salient point；
The hole TSV is formed at the back side of one or more of the salient point, the hole TSV extends to correspondence from second surface
The pad at the salient point back side；
Metal is filled in the hole TSV；
The chip and block of dielectric material are fixed on the first support plate, wherein the salient point of chip is contacted with support plate；
The chip and block of dielectric material are subjected to whole plastic packaging operation, form plastic-sealed body；
The plastic-sealed body is separated from the first support plate；
The back side of plastic-sealed body is bonded on the second support plate, the front of the salient point comprising chip is ground, is exposed convex
The metal covering of point；
Conducting wire and/or device are formed on the front after the grinding of plastic-sealed body；
First medium layer is covered on conducting wire and/or device；
Plastic-sealed body is separated from second support plate；
The front of plastic-sealed body is bonded on third support plate, the back side is ground, exposes TSV mesoporous metal；
It is formed on TSV mesoporous metal and reroutes layer and external pad.
In another embodiment of the present invention, this method further includes forming soldered ball on external pad.
In another embodiment of the present invention, conducting wire and/or device are formed on the front after the grinding of plastic-sealed body
Part includes: to form the first conducting wire on the top surface of the salient point and the top surface of capsulation material, in the top surface of block of dielectric material
The second conducting wire of upper formation and/or device, first conducting wire are electrically connected with second conducting wire and/or device
It connects.
In another embodiment of the present invention, the material of the block of dielectric material is different from capsulation material.
The embodiment of the present invention is greatly reduced the wiring difficulty of encapsulation, is improved using encapsulation front and back sides double-sided wiring
The quantity of the input/output pads of encapsulation.The embodiment of the present invention is using other dielectric materials placed in advance as substrate material
Material, is disposed thereon face for key signal, to promote the performance of specific structure, such as the Q value of inductance capacitance, antenna performance etc..
The present invention uses the packing forms of wafer scale, and production efficiency is higher, and cost advantage is bigger.The present invention is based on InFO to be fanned out to encapsulation
Technology is fanned out to scheme compared to embedded wafer scale ball grid array EWLB, and the technique realizability of RDL wiring is higher, reliably
Property is more preferable.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows the high frequency fan-out-type wafer level packaging structure of silicon etching through-hole according to an embodiment of the invention
100 diagrammatic cross-section.
Fig. 2 shows show the high frequency fan-out-type wafer-level packaging for forming silicon etching through-hole according to one embodiment of present invention
The flow chart of structure.
Fig. 3 A to 3R shows the high frequency fan-out-type wafer scale envelope for forming silicon etching through-hole according to one embodiment of present invention
The diagrammatic cross-section of assembling structure process.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
The present invention is based on traditional to be fanned out to encapsulation InFO technique, proposes the double-sided wiring based on the hole TSV.It not only reduces whole
The wiring difficulty of body encapsulation, while high frequency and low frequency signal being separated from each other, reduce the crosstalk each other between signal.
In addition, in the embodiment of the present invention, using the dielectric material different from capsulation material as certain device wiring layer
Base material.Solve disadvantage of the capsulation material as dielectric material.Improve the electric property entirely encapsulated.
Fig. 1 shows the high frequency fan-out-type wafer level packaging structure of silicon etching through-hole according to an embodiment of the invention
100 diagrammatic cross-section.
As shown in Figure 1, high frequency fan-out-type wafer level packaging structure 100 include the first chip 110, with 110 phase of the first chip
The capsulation material 130 of adjacent block of dielectric material 120 and encapsulating the first chip 110 and block of dielectric material 120.
First chip 110 has first surface 111 and second surface 112.With active area and extremely on first surface 111
Lack two pad (not shown), there is salient point 113 and 114 on each pad.Salient point 113 can be for high frequency signal transmission
Salient point, and salient point 114 can be the salient point for low frequency signal transmission.
It will be apparent to those skilled in the art above-mentioned salient point 113 and 114 is only schematically, in specific encapsulation knot
In structure, the first chip may include more salient points, and a portion salient point, which can be used for low frequency signal, to be transmitted, and another part salient point
For high frequency signal transmission.
The second surface 112 and first surface 111 of first chip 110 are opposite, and have and reroute layer 115 and external pad
116.It reroutes layer 115 and is electrically connected by one or more TSV through hole 117 with one or more salient points formation, wherein TSV through hole
117 extend to the pad of corresponding salient point from the second face of the first chip 110, and conductive metal is filled with inside through-hole.
In an embodiment of the present invention, soldered ball 118 can be set on external pad 116.
The top surface of salient point 113 and 114 and the top surface of block of dielectric material 120 are substantially flush.The top surface of salient point 113 and 114 is situated between
The top surface of material block 120 and capsulation material constitute a plane.
Conducting wire and/or device 140 are formed on the top surface of block of dielectric material 120.In an embodiment of the present invention,
Device can be the devices such as inductance, capacitor, antenna.Conducting wire can be the signal wire with particular requirement, e.g., high-frequency signal
Line.According to different electric property applications, it is fast that different dielectric materials may be selected.For example, when device when the inductance of high q-factor,
The material of block of dielectric material selection low conductivity.
It is formed with conducting wire on the top surface of salient point 113 and 114 and capsulation material, the conducting wire and block of dielectric material
Conducting wire and/or device 140 on 120 top surfaces form electrical connection.
The surface of wire line and/or device is covered with dielectric layer, for protecting wire line and/or device, specific
Position can be open to dielectric layer, expose following conductive circuit layer as pad.
Encapsulating structure shown in FIG. 1 is based on the hole TSV and realizes double-sided wiring, not only reduces the wiring difficulty of overall package,
High frequency and low frequency signal can be separated from each other simultaneously, reduce the crosstalk each other between signal.
Fig. 2 shows show the high frequency fan-out-type wafer-level packaging for forming silicon etching through-hole according to one embodiment of present invention
The flow chart of structure.Fig. 3 A to 3R shows the high frequency fan-out-type wafer for forming silicon etching through-hole according to one embodiment of present invention
The diagrammatic cross-section of class encapsulation structure process.The high frequency to form silicon etching through-hole is described in detail below with reference to Fig. 2 and Fig. 3 A to 3R
The detailed process of fan-out-type wafer level packaging structure.
Firstly, providing chip to be packaged in step 201.Single chip arranged distribution is in each region of whole wafer, such as
Shown in Fig. 3 A.The sectional view of single chip is further shown in detail in Fig. 3 B.Chip 310 has first surface 311 and the second table
Face 312.There are active area and at least two salient points 313 and 314 on first surface 311.Salient point 313 can be to be believed for high frequency
Number transmission salient point, and salient point 314 can be for low frequency signal transmission salient point.It will be apparent to those skilled in the art,
Above-mentioned salient point 313 and 314 is only schematically that in specific encapsulating structure, chip may include more salient points, wherein one
Salient point is divided to can be used for low frequency signal transmission, and another part salient point is used for high frequency signal transmission.
In step 202, the hole TSV 315 is formed at the pad back side of salient point 314.Specifically, chip 310 is rotated 180
Degree, downwards by first.TSV etched hole technique is carried out at 314 back side of salient point of low frequency signal, as shown in Figure 3 C.
In step 203, metal is filled in the hole TSV, signal is guided into the second face from the first face pad, as shown in Figure 3D.
Metal filling can be carried out by techniques such as plating, chemical plating, evaporation, sputterings.
In step 204, chip 310 and block of dielectric material 320 are fixed on support plate 330, wherein the salient point of chip 310 with
Support plate contact, as shown in FIGURE 3 E.Support construction of the support plate 330 as subsequent technique has certain mechanical strength.Support plate 330
Material can be square piece, disk or other shapes of the ingredients such as silicon, silica, ceramics, glass, metal, alloy, organic material
The plate of shape is also possible to that the board device of heating and temperature control can be carried out.EDS maps have many above-mentioned chip attachment thereon
Structure.Fig. 3 F shows and many unit package structures is distributed on the support plate of wafer shape according to an embodiment of the invention
Body, formation are fanned out to layout structure.Fig. 3 G shows the partial enlarged view that layout structure is fanned out to shown in Fig. 3 F.
Chip 310 and block of dielectric material 320 can be fixed on support plate by interim bonded layer (not shown).Firstly,
Using modes such as rolling, spin coating, spraying, printing, non-rotating coating, hot pressing, vacuum pressing-combining, immersion, pressure fittings on support plate
Cover interim bonded layer.The interim bonded layer can be thermoplastic or heat curing type organic material, be also possible to containing Cu, Ni, Cr, Co
The inorganic material of equal ingredients.Interim bonded layer can be removed by modes such as heating, machinery, chemistry, laser, freezings.
In step 205, chip and block of dielectric material are subjected to whole plastic packaging operation.Using capsulation material, by chip and Jie
Material integrally wraps up, as shown in figure 3h.Capsulation material can be organic insulation resin or the organic insulation containing filler
Resin.
In step 206, the plastic-sealed body that plastic packaging is finished is separated from support plate.According to the material of interim bonded layer, can choose
Support plate is removed by modes such as heating, machinery, chemistry, laser, freezings.
In step 207, plastic-sealed body is overturn into 180 degree, makes facing up for the salient point comprising chip, by the back side of plastic-sealed body
It is bonded on the second support plate 340, as shown in fig. 31.Support construction of second support plate 340 as subsequent technique has certain machine
Tool intensity.The material of second support plate 340 can be the ingredients such as silicon, silica, ceramics, glass, metal, alloy, organic material
Square piece, disk or other shapes plate, be also possible to that the board device of heating and temperature control can be carried out.Equally, can pass through
The back side of plastic-sealed body is bonded on the second support plate by interim bonded layer.
In step 208, the front of plastic-sealed body is ground.Chemical mechanical grinding CMP process, which can be selected, subtracts plastic-sealed body
Thin certain thickness, the salient point of chip is ground, and exposes corresponding metal covering, as shown in figure 3j.Meanwhile by block of dielectric material
Certain thickness is ground, guarantees the profile pattern of dielectric material.Body structure surface after grinding is very smooth, after being conducive to
Phase carries out RDL wiring processing.
In step 209, conducting wire and/or device are formed on flat surfaces after grinding, as shown in Fig. 3 K.In this hair
In bright embodiment, can by with particular/special requirement device and/or conducting wire be arranged in block of dielectric material.For example, device
It can be the devices such as inductance, capacitor, antenna.Fig. 3 L shows the top view of antenna according to an embodiment of the invention.It is conductive
Route can be the signal wire with particular requirement, e.g., high-frequency signal line.According to different electric property applications, may be selected not
Same dielectric material is fast.For example, block of dielectric material selects the material of low conductivity when device when the inductance of high q-factor.
Conducting wire and/or device may include that can pass through plating, chemical plating, evaporation, sputtering by one or more layers metal
Etc. techniques formed.
Conducting wire is electrically connected with device and chip bump formation.
In step 210, the blanket dielectric layer on conducting wire and/or device, for protect chip, block of dielectric material,
Conductive circuit layer and/or device, as shown in fig.3m.Dielectric layer can by rolling, spin coating, spraying, printing, it is non-rotating coating,
The modes such as hot pressing, vacuum pressing-combining, immersion, pressure fitting cover.
In step 211, plastic-sealed body is separated from the second support plate, and overturn 180 degree, make comprising chip bump just towards
Under, front is bonded on third support plate 350 by interim bonded layer, as shown in Fig. 3 N.The separation of plastic-sealed body and interim bonding
Method is similar with methods as described herein above, therefore is not described in detail.
In step 212, the back side of plastic-sealed body is ground.Chemical mechanical grinding CMP process, which can be selected, subtracts plastic-sealed body
Thin certain thickness, the TSV mesoporous metal on the second face of exposed chip, as shown in figure 3j.Body structure surface after grinding is very
It is smooth, be conducive to later period progress RDL wiring processing.
In step 213, conducting wire and dielectric layer 315 are formed on TSV mesoporous metal, and pass through photoetching work in specific position
Skill is open in the dielectric layer, exposes conductive circuit layer as external pad, as shown in Fig. 3 P.It is routed with the RDL of chip bonding pad layer
It compares, this sandwich circuit is all normal signal, the requirement such as not harsh high speed, impedance matching.Dielectric layer be photosensitive resin or
The resin of figure, such as polyimides, photosensitive type epoxy resin, welding resistance oil can be formed by techniques such as dry or wet etch
Black, green paint, dry film, photosensitive type increasing layer material, BCB (double benzocyclobutene resins) or PBO (phenyl benzo dioxazole resin).It is situated between
Matter layer can pass through the modes such as rolling, spin coating, spraying, printing, non-rotating coating, hot pressing, vacuum pressing-combining, immersion, pressure fitting
Covering.
In step 214, salient point or soldered ball 318 are formed at external pad, as shown in Fig. 3 Q.It can be by being electroplated or planting ball work
Skill is realized.
In step 215, whole layout structure is cut, is divided into independent single package body, then removes afterwards
Three support plates ultimately form a complete encapsulation, as shown in Fig. 3 R.
The embodiment of the present invention is greatly reduced the wiring difficulty of encapsulation, is improved using encapsulation front and back sides double-sided wiring
The quantity of the input/output pads of encapsulation.The embodiment of the present invention is using other dielectric materials placed in advance as substrate material
Material, is disposed thereon face for key signal, to promote the performance of specific structure, such as the Q value of inductance capacitance, antenna performance etc..
The present invention uses the packing forms of wafer scale, and production efficiency is higher, and cost advantage is bigger.The present invention is based on InFO to be fanned out to encapsulation
Technology is fanned out to scheme compared to embedded wafer scale ball grid array EWLB, and the technique realizability of RDL wiring is higher, reliably
Property is more preferable.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. a kind of fan-out-type wafer level packaging structure of silicon etching through-hole, comprising:
Chip；
Block of dielectric material, the block of dielectric material and the chip by chip；
Capsulation material, the capsulation material encapsulate the chip and the block of dielectric material,
Wherein the chip has first surface and second surface, has active area and at least two welderings on the first surface
Disk has salient point on each pad, and the top surface of the top surface of the salient point, the top surface of block of dielectric material and capsulation material flushes,
A plane is constituted, is provided with the first conducting wire on the top surface of the salient point and the top surface of capsulation material, block of dielectric material
The second conducting wire and/or device, first conducting wire and second conducting wire and/or device are provided on top surface
Electrical connection,
The second surface is opposite with the first surface, and the second surface is flushed with the back side of capsulation material, and reroutes
Layer and external pad are distributed on the back side of second surface and capsulation material, and the second rewiring layer passes through one or more
The hole TSV is electrically connected with one or more formed in the salient point, and wherein the hole TSV extends to corresponding salient point from second face
Pad, and conductive metal is filled with inside the hole TSV.
2. the fan-out-type wafer level packaging structure of silicon etching through-hole as described in claim 1, which is characterized in that the salient point packet
Include the salient point for high frequency signal transmission and the salient point for low frequency signal transmission.
3. the fan-out-type wafer level packaging structure of silicon etching through-hole as described in claim 1, which is characterized in that further include setting
Soldered ball on the external pad.
4. the fan-out-type wafer level packaging structure of silicon etching through-hole as described in claim 1, which is characterized in that described second leads
Electric line is high-frequency signal line.
5. the fan-out-type wafer level packaging structure of silicon etching through-hole as described in claim 1, which is characterized in that the device is
Inductance, capacitor or antenna.
6. the fan-out-type wafer level packaging structure of silicon etching through-hole as described in claim 4 or 5, which is characterized in that medium material
Expect that block is low conductivity material.
7. a kind of manufacturing method of the fan-out-type wafer level packaging structure of silicon etching through-hole, comprising:
There is provided chip to be packaged, the chip has first surface and second surface, has active area and extremely on first surface
Few two salient points；
The hole TSV is formed at the back side of one or more of the salient point, the hole TSV extends to corresponding salient point from second surface
The pad at the back side；
Metal is filled in the hole TSV；
The chip and block of dielectric material are fixed on the first support plate, wherein the salient point of chip is contacted with support plate；
The chip and block of dielectric material are subjected to whole plastic packaging operation, form plastic-sealed body；
The plastic-sealed body is separated from the first support plate；
The back side of plastic-sealed body is bonded on the second support plate, the front of the salient point comprising chip is ground, salient point is exposed
Metal covering；
Conducting wire and/or device are formed on the front after the grinding of plastic-sealed body；
First medium layer is covered on conducting wire and/or device；
Plastic-sealed body is separated from second support plate；
The front of plastic-sealed body is bonded on third support plate, the back side is ground, exposes TSV mesoporous metal；
It is formed on TSV mesoporous metal and reroutes layer and external pad.
8. the method for claim 7, which is characterized in that further include forming soldered ball on external pad.
9. the method for claim 7, which is characterized in that form conducting wire on the front after the grinding of plastic-sealed body
And/or device includes: to form the first conducting wire on the top surface of the salient point and the top surface of capsulation material, in block of dielectric material
Top surface on form the second conducting wire and/or device, first conducting wire and second conducting wire and/or device
Electrical connection.
10. the method for claim 7, which is characterized in that the material of the block of dielectric material is different from capsulation material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811494478.9A CN109473405A (en) | 2018-12-07 | 2018-12-07 | A kind of the fan-out-type wafer level packaging structure and its method of silicon etching through-hole |
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| CN201811494478.9A CN109473405A (en) | 2018-12-07 | 2018-12-07 | A kind of the fan-out-type wafer level packaging structure and its method of silicon etching through-hole |
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