CN216290855U

CN216290855U - Tunable filter

Info

Publication number: CN216290855U
Application number: CN202120841204.3U
Authority: CN
Inventors: 杜国琛; 谢振宇; 常珊; 林家强
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Sensor Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Sensor Technology Co Ltd
Priority date: 2021-04-23
Filing date: 2021-04-23
Publication date: 2022-04-12
Anticipated expiration: 2031-04-23

Abstract

The disclosure provides an adjustable filter and a preparation method thereof, and belongs to the technical field of electronics. The tunable filter of the present disclosure, comprising: a substrate base plate having a first surface and a second surface oppositely disposed in a thickness direction thereof; the substrate base plate is provided with a first connecting through hole penetrating along the thickness direction of the substrate base plate; at least one inductor and at least one capacitor integrated on the substrate base plate; wherein each of the at least one inductor comprises a first substructure disposed on the first surface, a second substructure disposed on the second surface, and a first connection electrode disposed in the first connection via, and the first connection electrode connects the first substructure with the second substructure to form the coil structure of the inductor.

Description

Tunable filter

Technical Field

The disclosure belongs to the technical field of electronics, and particularly relates to an adjustable filter.

Background

In the modern times, the consumer electronics industry is developing more and more, mobile communication terminals represented by mobile phones, particularly 5G mobile phones, are developing rapidly, the frequency bands of signals to be processed by the mobile phones are more and more, the number of required radio frequency chips is also rising, and the mobile phone form enjoyed by consumers is continuously developing towards miniaturization, lightness and thinness and long endurance. In a traditional mobile phone, a large number of discrete devices such as resistors, capacitors, inductors, filters and the like exist on a radio frequency PCB, and the discrete devices have the defects of large volume, high power consumption, multiple welding points and large change of parasitic parameters, so that the radio frequency PCB is difficult to meet future requirements. The radio frequency chips are mutually interconnected, matched and the like, and the integrated passive device has the advantages of small required area, high performance and good consistency. Integrated passive devices currently on the market are mainly based on Si (silicon) substrates and GaAs (gallium arsenide) substrates. The Si-based integrated passive device has the advantage of low price, but the microwave loss of the device is higher and the performance is poorer due to the fact that Si has trace impurities (poor insulation); the GaAs-based integrated passive device has the advantage of excellent performance, but is expensive.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to at least one of the problems of the prior art, and provides a tunable filter.

The disclosed embodiment provides a tunable filter, which includes:

a substrate base plate having a first surface and a second surface oppositely disposed in a thickness direction thereof; the substrate base plate is provided with a first connecting through hole penetrating along the thickness direction of the substrate base plate;

at least one inductor and at least one capacitor disposed on the substrate base; wherein each of the at least one inductor comprises a first sub-structure disposed on the first surface, a second sub-structure disposed on the second surface, and a first connection electrode disposed in the first connection via, and the first connection electrode connects the first sub-structure with the second sub-structure.

Wherein the at least one capacitance comprises a first capacitance and a second capacitance; the number of the inductors is one; the second capacitor comprises a first polar plate and a second polar plate which are sequentially arranged along the direction departing from the substrate, and the second capacitor is positioned between the first polar plate and the second polar plate and is arranged on the P-type semiconductor layer, the intrinsic semiconductor layer and the N-type semiconductor layer in a laminated manner;

a first lead end of the inductor is connected with a first signal end, and a second lead end of the inductor is connected with the second signal end and a first polar plate of the first capacitor; the second plate of the first capacitor is connected with the second plate of the second capacitor and a first bias voltage end; and the first polar plate of the second capacitor is connected with a second bias voltage end.

The second substructure of the inductor, the first polar plate of the first capacitor and the first polar plate of the second capacitor are arranged in the same layer and made of the same material; and/or the presence of a gas in the gas,

the first polar plate of the first capacitor and the second polar plate of the second capacitor are arranged on the same layer and made of the same material.

A first interlayer dielectric layer is arranged on one side, away from the substrate base plate, of the second plate of the second capacitor, and the first signal end, the second signal end, a first bias voltage end and the second bias voltage end are formed on one side, away from the substrate base plate, of the first interlayer dielectric layer;

the first signal end is connected with the first lead end of the inductor through a second connecting through hole penetrating through the first interlayer dielectric layer; the second signal end is connected with a second plate of the second capacitor through a third connecting through hole penetrating through the first interlayer dielectric layer; the first bias voltage end is connected with the second plate of the second capacitor through a fourth connecting through hole penetrating through the first interlayer dielectric layer; and the second bias voltage end is connected with the first plate of the second capacitor through a fifth connecting through hole penetrating through the first interlayer dielectric layer.

The substrate comprises a first signal end, a second signal end, a first bias voltage end and a second bias voltage end, wherein the substrate further comprises a first connecting pad, a second connecting pad, a third connecting pad and a fourth connecting pad which are positioned on one side, away from the substrate base plate, of a layer where the first signal end, the second signal end, the first bias voltage end and the second bias voltage end are positioned;

the first connecting pad covers one side of the first signal end, which is far away from the substrate base plate; the second connecting pad covers one side of the second signal end, which is far away from the substrate base plate; the third connecting pad covers one side of the first bias voltage end, which is far away from the substrate base plate; the fourth connection pad covers a side of the second bias voltage terminal facing away from the substrate base plate.

Wherein the at least one inductor comprises a first inductor and a second inductor; the at least one capacitor comprises a third capacitor and a fourth capacitor;

the tunable filter comprises a first resonance unit, a second resonance unit, a first switching transistor, a second switching transistor and a third switching transistor; wherein the first resonance unit comprises a first inductor and a third capacitor; the second resonance unit comprises a second inductor and a fourth capacitor;

a first lead end of the first inductor is connected with a third signal end, and a second lead end of the first inductor is connected with a first pole plate of the third capacitor; the second plate of the third capacitor is connected with the first pole of the first switch transistor; a second pole of the first switching transistor is connected with a fourth signal end; the control electrode of the first switch transistor is connected with a first control signal end and the first electrode of the second switch transistor; a second pole of the second switching transistor is connected with a reference voltage end; the control electrode of the second switching transistor is connected with a second control signal end and the control electrode of the third switching transistor; the first pole of the third switching transistor is connected with the second pole plate of the third capacitor; a second pole of the third switching transistor is connected with a second pole plate of the fourth capacitor; a first pole plate of the fourth capacitor is connected with a second lead end of the second inductor; and the first lead wire end of the second inductor is connected with a fifth signal end.

The second substructure of the first inductor, the second substructure of the second inductor, the first plate of the third sub-capacitor, the first plate of the fourth capacitor, the first and second poles of the first switch transistor, the first and second poles of the second switch transistor, and the first and second poles of the third switch transistor are arranged in the same layer and made of the same material; and/or the presence of a gas in the gas,

the second electrode plate of the third capacitor, the second electrode plate of the fourth capacitor, the control electrode of the first switching transistor, the control electrode of the second switching transistor and the control electrode of the third switching transistor are arranged in the same layer and made of the same material.

A first interlayer dielectric layer is arranged on one side, away from the substrate base plate, of the second plate of the second capacitor, and the third signal end, the fourth signal end and the fifth signal end are formed on one side, away from the substrate base plate, of the first interlayer dielectric layer; the first control signal terminal and the second control signal terminal;

the third signal end is connected with the first lead end of the first inductor through a sixth connecting through hole penetrating through the first interlayer dielectric layer; the fourth signal end is connected with the second plate of the third capacitor through a seventh connecting through hole penetrating through the first interlayer dielectric layer; the fifth signal end is connected with the first lead end of the second inductor through an eighth connecting through hole penetrating through the first interlayer dielectric layer; the first control signal end is connected with the control electrode of the first switch transistor through a ninth connecting through hole penetrating through the first interlayer dielectric layer; the second control signal terminal is connected with the control electrode of the second switching transistor and the control electrode of the third switching transistor through a tenth connecting through hole penetrating through the first interlayer dielectric layer.

The tunable filter further comprises a fifth connection pad, a sixth connection pad, a seventh connection pad, an eighth connection pad and a ninth connection pad, wherein the fifth connection pad, the sixth connection pad, the seventh connection pad, the eighth connection pad and the ninth connection pad are positioned on one side, away from the substrate, of a layer where the third signal end, the fourth signal end, the fifth signal end, the first control signal end and the second control signal end are positioned;

the fifth connecting pad covers one side of the third signal end, which is far away from the substrate base plate; the sixth connecting pad covers one side of the fourth signal end, which is far away from the substrate base plate; the seventh connecting pad covers one side of the fifth signal end, which is far away from the substrate base plate; the eighth connecting pad covers one side of the first control signal end, which is far away from the substrate base plate; the ninth connection pad covers one side of the second control signal end, which is far away from the substrate base plate.

Wherein the substrate base plate comprises a glass base.

The embodiment of the disclosure provides a preparation method of an adjustable filter, which includes:

providing a substrate base plate, wherein the substrate base plate is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate base plate; the substrate base plate is provided with a first connecting through hole penetrating along the thickness direction of the substrate base plate;

integrating at least one inductor and at least one capacitor on the substrate base plate; wherein,

forming the inductor includes:

forming a first substructure of the inductor on the first surface, forming a second substructure of the inductor on the second surface, and forming a first connection electrode in the first connection via; the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor.

Drawings

Fig. 1 is a circuit diagram of a tunable filter according to an embodiment of the present disclosure.

Fig. 2 is a top view of an inductor according to an embodiment of the present disclosure.

Fig. 3 is a cross-sectional view of the low pass filter shown in fig. 2.

Fig. 4 is a schematic structural diagram formed in step S11 in a method for manufacturing a tunable filter according to an embodiment of the disclosure.

Fig. 5 is a schematic structural diagram formed in step S12 in a method for manufacturing a tunable filter according to an embodiment of the disclosure.

Fig. 6 is a schematic structural diagram formed in step S13 in a method for manufacturing a tunable filter according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram formed in step S14 of a method for manufacturing a tunable filter according to an embodiment of the present disclosure.

Fig. 8 is a circuit diagram of another tunable filter according to an embodiment of the present disclosure.

Fig. 9a is a layout of the tunable filter shown in fig. 8.

Fig. 9b is a cross-sectional view of the tunable filter shown in fig. 8.

Fig. 10a is a layout formed in step S21 of another tunable filter manufacturing method according to the embodiment of the present disclosure.

Fig. 10b is a schematic structural diagram formed in step S21 of a method for manufacturing a tunable filter according to an embodiment of the disclosure.

Fig. 11a is a layout formed in step S22 of another tunable filter manufacturing method according to the embodiment of the present disclosure.

Fig. 11b is a schematic structural diagram formed in step S22 of a method for manufacturing a tunable filter according to an embodiment of the disclosure.

Fig. 12a is a layout formed in step S23 of another tunable filter manufacturing method according to the embodiment of the present disclosure.

Fig. 12b is a schematic structural diagram formed in step S23 of a method for manufacturing a tunable filter according to an embodiment of the disclosure.

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The disclosed embodiments provide a tunable filter and a method for manufacturing the same, wherein the tunable filter can be a low-pass filter, a high-pass filter, a band-stop filter, a duplexer, and the like. It follows that the tunable filter comprises at least a capacitance and an inductance L. The capacitor gates high-frequency signals and prevents low-frequency signals from passing through; the inductor L gates low-frequency signals and prevents high-frequency signals from passing through. Fig. 1 is a circuit diagram of a tunable filter according to an embodiment of the present disclosure; as shown in fig. 1, the tunable filter is a low-pass filter, which includes a first signal terminal, a second signal terminal, a first Bias voltage terminal Bias, a second Bias voltage terminal, an inductor L, a first capacitor C1, and a second capacitor C2; the first signal terminal is used as a signal Input terminal, and the second signal terminal is used as a signal Output terminal. The second capacitor C2 is an adjustable capacitor, for example: the adjustable capacitor comprises a first polar plate, a second polar plate, a P-type semiconductor, an intrinsic semiconductor and an N-type semiconductor which are arranged between the first polar plate and the second polar plate and are sequentially stacked. At this time, the capacitance can be adjusted by controlling the bias voltage applied to the first plate and the second plate.

Specifically, the first lead terminal 22 of the inductor L is connected to the signal Input terminal Input, the second lead terminal 23 of the inductor L is connected to the first plate 31 of the first capacitor C1, the second plate 32 of the first capacitor C1 is connected to the second plate 32 of the second capacitor C2 and the first Bias voltage terminal Bias, and the first plate 31 of the second capacitor C2 is connected to the second Bias voltage terminal Bias. In the embodiment of the present disclosure, taking the second Bias voltage terminal as the ground terminal GND as an example, in this case, the size of the second capacitor C2 can be changed by only changing the voltage input to the first Bias voltage terminal Bias, so as to implement the function of adjusting the frequency of the filter.

In order to make the specific structure of the tunable filter shown in fig. 1 more clear, the structure of each film layer of the tunable filter will be described. The inductor L, the first capacitor C1 and the second capacitor C2 in the tunable filter are integrated on the substrate. For example: the inductor L adopts a snake-shaped coil and is formed on the substrate; the first plate 31 of the first capacitor C1 and the first plate 31 of the second capacitor C2 may be disposed in the same layer as the inductor L and may be made of the same material. A P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer are sequentially formed on one side, away from the substrate, of the first plate 31 of the second capacitor C2, and an interlayer dielectric layer is formed on one side, away from the substrate, of the first plate 31 of the first capacitor C1. The second plate 32 of the first capacitor C1 is formed on the side of the interlayer dielectric layer away from the substrate, and the interlayer dielectric layer is used as an intermediate medium between the first plate 31 and the second plate of the first capacitor C1. A second plate 32 of a second capacitor C2 is formed on the side of the N-type semiconductor layer facing away from the substrate base plate. A first interlayer dielectric layer 40 is formed on one side of the second plate 32 of the first capacitor C1 and the second plate 32 of the second capacitor C2, which is far away from the substrate, a signal Input end, a signal Output end, a first Bias voltage end Bias and a ground end GND are formed on one side of the first interlayer dielectric layer 40, which is far away from the substrate, the signal Input end is connected with the first lead end 22 of the inductor L through a second connecting via hole 41 penetrating through the first interlayer dielectric layer 40, the signal Output end Output is connected with the second plate 32 of the second capacitor C2 of the inductor L through a third connecting via hole 42 penetrating through the first interlayer dielectric layer 40, and the first Bias voltage end Bias is connected with the second plate 32 of the second capacitor C2 through a fourth connecting via hole 43 penetrating through the first interlayer dielectric layer 40; the ground terminal GND is connected to the first plate 31 of the second capacitor C2 through a fifth connection via 44 penetrating through the first interlayer dielectric layer 40. Of course, the tunable filter in the embodiment of the present disclosure may further include a first connection pad 51, a second connection pad 52, a third connection pad 53, and a fourth connection pad 54 formed on a side of the layer where the signal Input end Input, the signal Output end Output, the first Bias voltage end Bias, and the second Bias voltage end are located, which is away from the substrate base plate; the first connection pad 51 covers the side of the signal Input end Input departing from the substrate; the second connection pad 52 covers one side of the signal Output end Output, which is far away from the substrate; the third connection pad 53 covers a side of the first Bias voltage terminal Bias facing away from the substrate base; the fourth connection pad 54 covers the side of the ground GND facing away from the substrate base.

In some examples, the substrate includes, but is not limited to, any one of a glass substrate 10, a flexible substrate, and an interlayer dielectric layer including at least an organic insulating layer. Since passive devices are integrated on the glass substrate 10, the substrate is preferably made of the glass substrate 10 in the embodiment of the present disclosure, which has advantages of small size, light weight, high performance, low power consumption, and the like. Hereinafter, the transparent dielectric layer will be described using the glass substrate 10 as an example.

In some examples, to implement a small size filter, the glass substrate 10 may be processed to form a solid inductor L to reduce the size of the filter. For example: fig. 2 is a top view of an inductor L according to an embodiment of the present disclosure; referring to fig. 2, each of the first substructures 211 of the inductor L extends along a first direction and is arranged side by side along a second direction; each second substructure 212 of the inductor L extends along the third direction and is arranged side by side along the second direction. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction are intersected and non-perpendicular to each other. Of course, the extending directions of the first substructure 211 and the second substructure 212 may be interchanged, all within the scope of the embodiments of the present disclosure. In addition, in the present embodiment, the inductor L includes N first sub-structures 211 and N-1 second sub-structures 212, where N ≧ 2, and N is an integer. The first end and the second end of the first substructure 211, respectively, at least partially overlap with an orthographic projection of one first connecting via 11 on the glass substrate 10. And the first end and the second end of one first sub-structure 211 correspond to different first connecting vias 11, i.e. one first sub-structure 211 at least partially overlaps with two first connecting vias 1111 in an orthographic projection on the glass substrate 10. At this time, the first end of the ith second substructure 212 of the inductor L is connected to the first end of the ith first substructure 211 and the second end of the (i + 1) th first substructure 211 to form an inductor L coil, where i is greater than or equal to 1 and less than or equal to N-1, and i is an integer.

It should be noted that the first lead terminal 22 is connected to the second terminal of the first substructure 211 of the inductor L, and the second lead terminal 23 is connected to the first terminal of the nth first substructure 211. Further, the first lead terminal 22 and the second lead terminal 23 may be disposed on the same layer as the second sub-structure 212 and made of the same material, in which case the first lead terminal 22 may be connected to the second terminal of the first sub-structure 211 through the first connecting via 11, and correspondingly, the second lead terminal 23 may be connected to the first terminal of the nth first sub-structure 211 through the first connecting via 11.

FIG. 3 is a cross-sectional view of the low pass filter shown in FIG. 2; as shown in fig. 3, the first substructure 211 in the inductance L of the low-pass filter is arranged on the first surface of the glass substrate 10 and the second substructure 212 is arranged on the second surface of the glass substrate 10. A first capacitor C1 and a second capacitor C2 of the low-pass filter are also arranged on the second surface.

For example: the second substructure 212 of the inductor L-coil is disposed in the same layer as the first plate 31 of the first capacitor C1 and the first plate 31 of the second capacitor C2, and is made of the same material. A P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer are sequentially formed on one side, away from the substrate, of the first plate 31 of the second capacitor C2, and an interlayer dielectric layer is formed on one side, away from the substrate, of the first plate 31 of the first capacitor C1. The second plate 32 of the first capacitor C1 is formed on the side of the interlayer dielectric layer away from the substrate, and the interlayer dielectric layer is used as an intermediate medium between the first plate 31 and the second plate of the first capacitor C1. A second plate 32 of a second capacitor C2 is formed on the side of the N-type semiconductor layer facing away from the substrate base plate. A first interlayer dielectric layer 40 is formed on one side of the second plate 32 of the first capacitor C1 and the second plate 32 of the second capacitor C2, which is far away from the substrate, a signal Input end, a signal Output end, a first Bias voltage end Bias and a ground end GND are formed on one side of the first interlayer dielectric layer 40, which is far away from the substrate, the signal Input end is connected with the first lead end 22 of the inductor L through a second connecting via hole 41 penetrating through the first interlayer dielectric layer 40, the signal Output end Output is connected with the second plate 32 of the second capacitor C2 of the inductor L through a third connecting via hole 42 penetrating through the first interlayer dielectric layer 40, and the first Bias voltage end Bias is connected with the second plate 32 of the second capacitor C2 through a fourth connecting via hole 43 penetrating through the first interlayer dielectric layer 40; the ground terminal GND is connected to the first plate 31 of the second capacitor C2 through a fifth connection via 44 penetrating through the first interlayer dielectric layer 40. Of course, the tunable filter in the embodiment of the present disclosure may further include a first connection pad 51, a second connection pad 52, a third connection pad 53, and a fourth connection pad 54 formed on a side of the layer where the signal Input end Input, the signal Output end Output, the first Bias voltage end Bias, and the second Bias voltage end are located, which is away from the substrate base plate; the first connection pad 51 covers the side of the signal Input end Input departing from the substrate; the second connection pad 52 covers one side of the signal Output end Output, which is far away from the substrate; the third connection pad 53 covers a side of the first Bias voltage terminal Bias facing away from the substrate base; the fourth connection pad 54 covers the side of the ground terminal GND facing away from the substrate base.

In addition, in the tunable filter according to the embodiment of the disclosure, because the P-type semiconductor layer, the intrinsic semiconductor layer, and the N-type semiconductor layer are disposed between the first plate and the second plate of the capacitor, the magnitude of the bias voltage applied to the first plate and the second plate can be controlled, so that the tuning effect of the capacitor is realized, and the frequency tunable function of the filter is realized. For example: the larger the value of the capacitance, the stronger the rejection of low frequency signals.

In order to make the structure of the low-pass filter shown in fig. 3 more clear, the following description is made in conjunction with a method for manufacturing the low-pass filter. It should be noted that fig. 3 only illustrates the structures of the second capacitor C2 and the inductor L, and the first capacitor C1 is not illustrated in fig. 3, wherein the first plate 31 of the first capacitor C1 and the first plate 31 of the second capacitor C2 are prepared by a one-step patterning process, and the second plate 32 of the first capacitor C1 and the second plate 32 of the second capacitor C2 are prepared by a one-step patterning process, so in the following description, only the preparation processes of the inductor L and the second capacitor C2 are described.

The preparation method of the low-pass filter shown in fig. 3 specifically includes the following steps:

s11, providing a glass substrate 10, and forming a first connecting via 11 penetrating through the glass substrate 10 in the thickness direction, as shown in fig. 4.

In some examples, the first connecting via 11 on the glass substrate 10 may be formed by means including, but not limited to, mechanical drilling, laser drilling, photolithography drilling, and the like. The process of forming the first connection via 11 will be described below by taking laser drilling as an example.

In some examples, step S11 may specifically include the following steps:

(1) cleaning: the glass substrate 10 enters a cleaning machine for cleaning.

In some examples, the glass substrate 10 has a thickness of about 0.1mm to 1.1 mm.

(2) Laser drilling: a laser is used to strike the surface of the glass substrate 10 at a normal incidence of the laser beam to form a plurality of first connecting through holes 11 in the glass substrate 10. Specifically, when the laser beam interacts with the glass substrate 10, the atoms in the glass substrate 10 are ionized and projected out of the surface of the glass substrate 10 due to the higher energy of the laser photons, and the holes drilled are gradually deepened with time until the whole glass substrate 10 is drilled, i.e., a plurality of first connecting through holes 11 are formed. The laser wavelength can be 532nm, 355nm, 266nm, 248nm, 197nm, 1-100fs, 1-100ps, 1-100ns, continuous laser, pulse laser, etc. The laser drilling method may include, but is not limited to, the following two methods. In the first mode, when the diameter of a light spot is large, the relative position of a laser beam and the glass substrate 10 is fixed, the glass substrate 10 is directly punched through by means of high energy, the shape of the first connecting through hole 11 formed at the moment is an inverted circular truncated cone, and the diameter of the inverted circular truncated cone is sequentially reduced from top to bottom (from the second surface to the first surface). In the second mode, when the diameter of a light spot is small, a laser beam scans the glass substrate 10 in a circle, the focal point of the light spot is constantly changed, the depth of the focal point is constantly changed, a spiral line is drawn from the lower surface (first surface) of the glass substrate 10 to the upper surface (second surface) of the glass substrate 10, the radius of the spiral line is sequentially reduced from bottom to top, the glass substrate 10 is cut into a circular truncated cone shape by the laser, the glass substrate falls down due to the action of gravity, a first connecting through hole 11 is formed, and the first connecting hole is in the shape of a circular truncated cone.

In some examples, the first connecting via 11 is formed to have an aperture of about 10 μm-1 mm.

(3) And (3) HF etching: since a stress region is formed in a region of about 5 to 20 μm near the hole on the upper surface of the inner wall of the first connecting via hole 11 during the laser drilling process, the surface of the glass substrate 10 in the region is rugged, exhibits molten state and is burred, and has a large number of micro cracks and macro cracks, and residual stress is present. At this time, 2% -20% of HF etching liquid is used, wet etching is carried out for a certain time at a proper temperature, the glass in the stress area is etched, the area, close to the hole, inside and on the surface of the first connecting through hole 11 is smooth and flat, microcracks and macro cracks do not exist, and the stress area is completely etched.

S12, forming a first substructure 211 of an inductor L-coil on the first surface of the glass substrate 10 completing the step S11, forming a second substructure 212 and a first plate 31 of a second capacitor C2 on the second surface, and a first connection electrode 213 positioned in the first connection via 11, as shown in fig. 5.

In some examples, step S12 may specifically include the following steps:

(1) growing a seed layer: in the process, the first metal film is deposited on the inner wall of the first connection via hole 11, and then the glass substrate 10 is turned over, and the first metal film is formed on the second surface of the glass substrate 10 by using the measurement and control sputtering method, although the first metal film on the second surface also serves as the plating seed layer.

In some examples, the material of the first metal thin film includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal thin film is about 100nm to 500nm, and further may be about 50nm to 35 μm. In the following description, the material of the first metal thin film is copper as an example.

In some examples, to increase the adhesion of the first metal film to the glass substrate 10, an auxiliary metal film may be formed on the first and second surfaces of the glass substrate 10 by means including, but not limited to, magnetron sputtering prior to forming the deposited first metal film. The auxiliary metal film is made of at least one of nickel (Ni), molybdenum (Mo) alloy and titanium (Ti) alloy, such as MoNb, and has a thickness of about 2-20 nm.

(2) Electroplating and hole filling: putting the glass substrate 10 on a carrier of an electroplating machine, pressing an electric bonding pad (pad), putting the glass substrate into a hole-filling electroplating bath (special hole-filling electrolyte is used in the bath), applying current, keeping the electroplating bath continuously and rapidly flowing on the surface of the glass substrate 10, obtaining electrons from cations in the electroplating bath on the inner wall of the first connecting through hole 11, forming atoms to be deposited on the inner wall, and depositing metal copper (with the deposition speed of 0.5-3um/min) mainly in the first connecting hole at a high speed through the special hole-filling electrolyte with special proportion, wherein the first surface and the second surface of the glass substrate 10 are flat areas, and the deposition speeds of the metal copper on the two surfaces are extremely small (0.005-0.05 um/min). With the increase of time, the metal copper on the inner wall of the first connection hole gradually grows thick, and even the first connection through hole 1111 can be completely filled, that is, a connection part of the inductor L coil is formed (that is, the preparation of the spiral area of the inductor L is completed), and finally the glass is taken out and washed by deionized water.

(3) Patterning of the first surface metal: turning the glass substrate 10 (with the first surface facing upward), gluing, exposing and developing on the metal copper layer on the first surface, then performing wet etching on copper, removing glue from strip after etching, and completing patterning of the metal on the first surface, thereby forming a first substructure 211 of an inductance L-line on the first surface.

(4) Second surface metal patterning: turning the glass substrate 10 (with the second surface facing upward), applying glue on the metal copper layer on the second surface, exposing, developing, then performing wet etching on the copper, removing the glue from the strip after etching, and completing patterning of the metal on the second surface, thereby forming the second substructure 212 of the L-coil 21 on the second surface and the first plate 31 of the second capacitor C2.

In some examples, after (3) patterning the first surface metal in step two and before (4) patterning the second surface metal, forming a first protection layer 60 on the first surface of the glass substrate 10 on which the first substructure 211 of the inductor L coil is formed to prevent the first substructure 211 from being oxidized due to exposure.

The material of the first protective layer 60 is an inorganic insulating material. For example: the first protective layer 60 is an inorganic insulating layer formed of silicon nitride (SiNx), or silicon oxide (SiO)₂) Inorganic insulating layer formed, or SiNx inorganic insulating layer and SiO₂Several stacked composite layers of inorganic insulating layers.

S13, a P-type semiconductor layer, an intrinsic semiconductor layer, an N-type semiconductor layer, and a second plate of the second capacitor C2 are formed on the glass substrate 10 completing the step S12, as shown in fig. 6.

In some examples, step S13 may include depositing a P-type semiconductor film, an intrinsic semiconductor film, an N-type semiconductor film, and a second metal film in sequence on a side of the first plate 31 of the second capacitor C2 away from the glass substrate 10, coating, exposing, developing, and then performing wet etching, and strip removing after etching, and simultaneously forming a pattern including the P-type semiconductor layer, the intrinsic semiconductor layer, the N-type semiconductor layer, and the second plate of the second capacitor C2. In some examples, the material of the second metal film may be the same as the material of the first metal film, and thus is not described herein again. The material of the P-type semiconductor film can be P-amorphous silicon, the material of the intrinsic semiconductor film can be amorphous silicon, and the material of the N-type semiconductor film can be N-amorphous silicon.

S14, forming a first interlayer dielectric layer 40 on the glass substrate 10 after the step S13 is completed, and forming a second connecting via 41, a third connecting via 42, a fourth connecting via 43 and a fifth connecting via 44 penetrating the first interlayer dielectric layer 40, as shown in fig. 7. The second connection via hole 41 is used for connecting the first lead end 22 of the inductor L coil with a signal Input end to be formed; the third connecting via 42 is used for connecting the second plate 32 of the second capacitor C2 with the signal Output end Output to be formed; the fourth connecting via 43 is for connecting the second plate 32 of the second capacitance C2 with a first bias voltage line to be formed; the fifth connecting via 44 is used to connect the first plate 31 of the second capacitor C2 with the ground GND to be formed.

In some examples, step S14 may include forming the first interlayer dielectric layer 40 on the side of the second plate 32 of the second capacitor C2 away from the glass substrate 10 by Plasma Enhanced Chemical Vapor Deposition (PECVD), applying glue, exposing, developing on the first interlayer dielectric layer 40, performing dry etching, and removing the glue from strip after etching to obtain the second connecting via 41, the third connecting via 42, the fourth connecting via 43, and the fifth connecting via 44.

The first interlayer dielectric layer 40 is made of an inorganic insulating material. For example: the first interlayer dielectric layer 40 is an inorganic insulating layer formed of silicon nitride (SiNx) or silicon oxide (SiO)₂) Inorganic insulating layer formed, or SiNx inorganic insulating layer and SiO₂Several stacked composite layers of inorganic insulating layers.

S15, forming a signal Input end, a signal Output end, a first Bias voltage end Bias and a ground end GND on the glass substrate 10 after the step S14 is completed; wherein, the signal Input end is connected with the first lead end 22 of the L-coil inductor through the second connection via hole 41; the signal Output end Output is connected with the second plate 32 of the second capacitor C2 through a third connection via 42 and a third connection via 4242; the first bias voltage line is connected to the second plate 32 of the second capacitor C2 through a fourth connection; the ground GND is connected to the first plate 31 of the second capacitor C2 through the fifth connection via 44.

In some examples, step S15 may include depositing a third metal film by magnetron sputtering, then performing glue coating, exposure, development, and wet etching, and removing the glue from strip after etching to form a pattern including a signal Input terminal Input, a signal Output terminal Output, a first Bias voltage terminal Bias, and a ground terminal GND. The material of the third metal film may be the same as the material of the first metal film, and therefore, the description thereof is omitted.

S16, forming the first connection pads 51, the second connection pads 52, the third connection pads 53, and the fourth connection pads 54 on the glass substrate 10 completing the step S15. The first connection pad 51 covers the signal Input terminal, the second connection pad 52 covers the signal Output terminal, the third connection pad 53 covers the first Bias voltage terminal Bias, and the fourth connection pad 54 covers the ground terminal GND, as shown in fig. 3.

In some examples, the first connection pad 51, the second connection pad 52, the third connection pad 53, and the fourth connection pad 54 include, but are not limited to, solder.

Thus, the preparation of the low-pass filter is completed.

FIG. 8 is a circuit diagram of another tunable filter according to an embodiment of the present disclosure; as shown in fig. 8, the filter includes a third signal terminal, a fourth signal terminal, a fifth signal terminal, a first control signal terminal, a second control signal terminal, a first tuning unit, a second tuning unit, a first switching transistor T1, a second switching transistor T2, and a third switching transistor T3. The third signal terminal serves as the signal Input terminal, the fourth signal terminal serves as the first signal Input terminal, the fifth signal terminal serves as the second signal Output terminal Output2, and the reference signal terminal may be the ground terminal GND. The first tuning unit comprises a first inductor L1 and a third capacitor C3, and is configured to select a main frequency signal; the second tuning unit includes a second inductor L2 and a fourth capacitor C4 configured to cooperate with the first resonant unit to screen the frequency converted signal.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, the source and the drain are not different. In the embodiments of the present disclosure, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the gate electrode inputs a high level, the source electrode and the drain electrode are conducted, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the disclosed embodiments. In the embodiment of the present disclosure, since the transistor is an N-type transistor, the working level signal in the embodiment of the present disclosure refers to a high level signal, and the non-working level signal refers to a low level signal.

Specifically, with continued reference to fig. 8, in the tunable filter, the first lead terminal 22 of the first inductor L1 is connected to the signal Input terminal, and the second lead terminal 23 of the first inductor L1 is connected to the first plate 31 of the third capacitor C3; the second plate 32 of the third capacitor C3 is connected to the source of the first switching transistor T1; the drain of the first switching transistor T1 is connected to a first signal Output terminal Output 1; a gate of the first switching transistor T1 is connected to the first control signal terminal and the source of the second switching transistor T2; the drain of the second switching transistor T2 is connected to the ground GND; a gate of the second switching transistor T2 is connected to the second control signal terminal and the gate 103 of the third switching transistor T3; the source of the third switching transistor T3 is connected to the second plate 32 of the third capacitor C3; the drain of the third switching transistor T3 is connected to the second plate 32 of the fourth capacitor C4; the first plate 31 of the fourth capacitor C4 is connected to the second lead terminal 23 of the second inductor L2; the first lead terminal 22 of the second inductor L2 is connected to the second signal Output terminal Output 2.

For example: when the first control signal terminal inputs a high level signal and the second control signal terminal inputs a low level signal, the first switching transistor T1 is turned on, and the second switching transistor T2 and the third switching transistor T3 are turned off; the Input signal of the signal Input terminal is Output through the first signal Output terminal Output1 via the first resonant unit (the first inductor L1 and the third capacitor C3). When the second control signal terminal inputs a high level signal and the first control signal terminal inputs a low level signal, the second switching transistor T2 and the third switching transistor T3 are turned on, and the first switching transistor T1 is turned off; at this time, the signal Input by the signal Input terminal passes through the first tuning unit (the first inductor L1 and the third capacitor C3) and the second tuning unit (the second inductor L2 and the fourth capacitor C4), and is output through the second output terminal, so that the screening of the variable frequency signal is realized.

In order to make the specific structure of the filter more clear, the structure of each film layer of the specific structure of the filter is described below. The filter comprises a first inductor L1 and a third capacitor C3 in a first resonance unit, a second inductor L2 and a fourth capacitor C4 in a second resonance unit; the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 may all be formed on the integrated glass substrate 10. For example: the first inductor L1 and the second inductor L2 both adopt a serpentine coil structure and are disposed on the glass substrate 10, the first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 may be disposed in the same layer as the first inductor L1 and the second inductor L2, and the same material is used, and at the same time, the source and the drain 81 of the first switch transistor T1, the source and the drain 82 of the second switch transistor T2, and the source and the drain 83 of the third switch transistor T3 may also be disposed in this layer structure. A second interlayer dielectric layer is formed on the first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 on the side away from the glass substrate 10, and an active layer 91 of the first switching transistor T1, an active layer 92 of the second switching transistor T2, and an active layer 93 of the third switching transistor T3. The second electrode plate 32 of the third capacitor C3, the second electrode plate 32 of the fourth capacitor C4, the gate of the first switch transistor T1, the gate of the second switch transistor T2 and the gate 103 of the third switch transistor T3 are formed on the side of the second interlayer dielectric layer, which faces away from the glass substrate 10. A first interlayer dielectric layer 40 is formed on the second plate 32 of the third capacitor C3, the second plate 32 of the fourth capacitor C4, and the side of the layer where the gate electrode 103 of the first switch transistor T1, the gate electrode 103 of the second switch transistor T2 and the gate electrode 103 of the third switch transistor T3 are away from the glass substrate 10. Forming a signal Input end, a first signal Output end Output1, a second signal Output end Output2, a first control signal end and a second control signal end on one side of the first interlayer dielectric layer 40, which is far away from the glass substrate 10; the signal Input end is connected with the first lead end 22 of the first inductor L1 through a sixth connecting via hole penetrating through the first interlayer dielectric layer 40; the first signal Output end 1 is connected to the second plate 32 of the third capacitor C3 through a seventh connection via penetrating through the first interlayer dielectric layer 40; the second signal Output terminal Output2 is connected to the first lead terminal 22 of the second inductor L2 through an eighth connecting via hole penetrating through the first interlayer dielectric layer 40; the first control signal terminal is connected with the gate of the first switching transistor T1 through a ninth connection via hole penetrating through the first interlayer dielectric layer 40; the second control signal terminal is connected to the gates of the second and third switching transistors T2 and T3 through a tenth connection via penetrating the first interlayer dielectric layer 40. A fifth connection pad 55, a sixth connection pad 56, a seventh connection pad 57, an eighth connection pad 58 and a ninth connection pad 59 on a side of the layer where the signal Input end, the first signal Output end 1, the second signal Output end 2, the first control signal end and the second control signal end are located away from the glass substrate 10; the fifth connection pad 55 covers the side of the signal Input end facing away from the substrate; the sixth connection pad 56 covers a side of the first signal Output terminal Output1 facing away from the substrate base plate; the seventh connection pad 57 covers a side of the second signal Output terminal Output2 facing away from the substrate base plate; the eighth connection pad 58 covers a side of the first control signal terminal facing away from the substrate base plate; the ninth connection pad 59 covers a side of the second control signal terminal facing away from the substrate base plate.

In some examples, to implement a small size filter, the glass substrate 10 may be processed to form a solid inductor L to reduce the size of the filter. That is, the first inductor L1 and the second inductor L2 in the filter may also adopt the structure of fig. 2, that is, a three-dimensional inductor L structure. FIG. 9a is a layout of the tunable filter shown in FIG. 8; figure 9b is a cross-sectional view of the tunable filter shown in figure 8; as shown in fig. 9a and 9b, the glass substrate 10 has a first connecting via 11 penetrating through a thickness direction thereof. Each of the first inductor L1 and the second inductor L2 includes a first sub-structure 211 disposed on the first surface of the glass substrate 10, a second sub-structure 212 disposed on the second surface, and a first connection electrode 213 disposed in the first connection through hole 11. The first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 may be disposed in the same layer as the second substructure 212 of the first inductor L1 and the second substructure 212 of the second inductor L2, and may be made of the same material, and at the same time, the source and drain 81 of the first switching transistor T1, the source and drain 82 of the second switching transistor T2, and the source and drain 83 of the third switching transistor T3 may be disposed in the layer. A second interlayer dielectric layer is formed on the first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 on the side away from the glass substrate 10, and an active layer 91 of the first switching transistor T1, an active layer 92 of the second switching transistor T2, and an active layer 93 of the third switching transistor T3. The second electrode plate 32 of the third capacitor C3, the second electrode plate 32 of the fourth capacitor C4, the gate of the first switch transistor T1, the gate of the second switch transistor T2 and the gate 103 of the third switch transistor T3 are formed on the side of the second interlayer dielectric layer, which faces away from the glass substrate 10. A first interlayer dielectric layer 40 is formed on the second plate 32 of the third capacitor C3, the second plate 32 of the fourth capacitor C4, and the side of the layer where the gate electrode 103 of the first switch transistor T1, the gate electrode 103 of the second switch transistor T2 and the gate electrode 103 of the third switch transistor T3 are away from the glass substrate 10. Forming a signal Input end, a first signal Output end Output1, a second signal Output end Output2, a first control signal end and a second control signal end on one side of the first interlayer dielectric layer 40, which is far away from the glass substrate 10; the signal Input end is connected with the first lead end 22 of the first inductor L1 through a sixth connecting via hole penetrating through the first interlayer dielectric layer 40; the first signal Output end 1 is connected to the second plate 32 of the third capacitor C3 through a seventh connection via penetrating through the first interlayer dielectric layer 40; the second signal Output terminal Output2 is connected to the first lead terminal 22 of the second inductor L2 through an eighth connecting via hole penetrating through the first interlayer dielectric layer 40; the first control signal terminal is connected with the gate of the first switching transistor T1 through a ninth connection via hole penetrating through the first interlayer dielectric layer 40; the second control signal terminal is connected to the gates of the second and third switching transistors T2 and T3 through a tenth connection via penetrating the first interlayer dielectric layer 40. A fifth connection pad 55, a sixth connection pad 56, a seventh connection pad 57, an eighth connection pad 58 and a ninth connection pad 59 on a side of the layer where the signal Input end, the first signal Output end 1, the second signal Output end 2, the first control signal end and the second control signal end are located away from the glass substrate 10; the fifth connection pad 55 covers the side of the signal Input end facing away from the substrate; the sixth connection pad 56 covers a side of the first signal Output terminal Output1 facing away from the substrate base plate; the seventh connection pad 57 covers a side of the second signal Output terminal Output2 facing away from the substrate base plate; the eighth connection pad 58 covers a side of the first control signal terminal facing away from the substrate base plate; the ninth connection pad 59 covers a side of the second control signal terminal facing away from the substrate base plate.

In order to make the structure of the tunable filter shown in fig. 8 more clear, a method for manufacturing a filter having such a structure will be described below.

S21, providing a glass substrate 10, and forming a first connecting via 11 penetrating through the glass substrate 10 in the thickness direction, as shown in fig. 10a and 10 b.

In some examples, step 21 may be formed in the same manner as step S11 described above, and therefore, the description thereof is not repeated here.

S22, forming a first substructure 211 of an inductor L coil on the first surface of the glass substrate 10 completing the step S21, forming a second substructure 212 on the second surface, the first plate 31 of the third capacitor C3, the first plate 31 of the fourth capacitor C4, the source and drain 81 of the first switching transistor T1, the source and drain 82 of the second switching transistor T2, the source and drain 83 of the third switching transistor T3, and the first connection electrode 213 positioned in the first connection through hole 11, as shown in fig. 11a and 11 b.

In some examples, step S22 may be the same as the process of step S12 described above, except that the first plate 31 of the third capacitance C3, the first plate 31 of the fourth capacitance C4, the source and drain 81 of the first switching transistor T1, the source and drain 82 of the second switching transistor T2, and the source and drain 83 of the third switching transistor T3 are formed while forming the second sub-structure 212 on the second surface. The detailed process step of step S22 is not described again.

S23, forming the active layer 91 of the first switching transistor T1, the active layer 92 of the second switching transistor T2, and the active layer 93 of the third switching transistor T3 on the glass substrate 10 completing the step S22 as shown in fig. 12a and 12b, and forming a second interlayer dielectric layer on the side of the active layer 91 of the first switching transistor T1, the active layer 92 of the second switching transistor T2, and the active layer 93 of the third switching transistor T3 facing away from the glass substrate 10.

It should be noted that the second interlayer dielectric layer serves as an intermediate medium between the first plate 31 and the second plate of the third capacitor C3, and also serves as an intermediate medium between the first plate 31 and the second plate of the fourth capacitor C4, and therefore, the second interlayer dielectric layer may be only disposed at the positions of the first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4. Of course, the second interlayer dielectric layer may cover the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the active layer 93 of the third switch transistor T3, and the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the first plate 31 of the third capacitor C3, and the first plate 31 of the fourth capacitor C4, so that it is not necessary to form an interlayer insulating layer on the side of the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, and the active layer 93 of the third switch transistor T3 away from the glass substrate 10. In the embodiment of the present disclosure, the second interlayer dielectric layer may also cover the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the active layer 93 of the third switch transistor T3, and the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the first plate 31 of the third capacitor C3, and the first plate 31 of the fourth capacitor C4.

In some examples, step S23 may include depositing a semiconductor material layer by using a plasma chemical vapor deposition method, applying glue, exposing, developing on the semiconductor material layer, then performing dry etching, and strip removing after etching to obtain a pattern including the active layer 91 of the first switching transistor T1, the active layer 92 of the second switching transistor T2, and the active layer 93 of the third switching transistor T3. And then, depositing a second interlayer dielectric layer by adopting plasma chemical vapor deposition. The material of the semiconductor material layer includes, but is not limited to, metal oxide, polysilicon, amorphous silicon, and the like. The material of the second interlayer dielectric layer may be the same as that of the first interlayer dielectric layer 40 described above.

S24, forming a gate of the first switching transistor T1, a gate of the second switching transistor T2, a gate 103 of the third switching transistor T3, a second plate 32 of the third capacitor C3, and a second plate 32 of the fourth capacitor C4 on the glass substrate 10 completing the step S23. In some examples, in step S24, a fourth metal film may be deposited by magnetron sputtering, and then glue coating, exposure, and development are performed, followed by wet etching, and strip is removed after etching, so as to form a pattern including the gate of the first switching transistor T1, the gate of the second switching transistor T2, the gate 103 of the third switching transistor T3, the second plate 32 of the third capacitor C3, and the second plate 32 of the fourth capacitor C4; as shown in fig. 9a and 9 b.

The material of the fourth metal film may be the same as that of the first metal film, and thus, the description thereof is not repeated herein.

And S25, forming the first interlayer dielectric layer 40 on the glass substrate 10 after the step S24 is completed, and forming a sixth connecting via, a seventh connecting via, an eighth connecting via, a ninth connecting via and a tenth connecting via. The sixth connecting via is used for connecting the signal Input end to be formed with the first lead end 22 of the first inductor L1; the seventh connecting via is used for connecting the first signal Output end Output1 and the second plate 32 of the third capacitor C3 to be formed; the eighth connecting via is used for connecting the second signal Input end to be formed with the first lead terminal 22 of the second inductor L2; the ninth connection via is to connect the first control signal terminal to be formed with the gate of the first switching transistor T1; the tenth connection via is to connect the second control signal terminal to be formed with the gate of the second switching transistor T2 and the gate 103 of the third switching transistor T3.

In some examples, step S25 may include forming the first interlayer dielectric layer 40 on the side of the second plate 32 of the second capacitor C2 away from the glass substrate 10 by Plasma Enhanced Chemical Vapor Deposition (PECVD), applying glue, exposing, developing on the first interlayer dielectric layer 40, performing dry etching, and removing the glue from the strip after etching to obtain the sixth connecting via, the seventh connecting via, the eighth connecting via, the ninth connecting via, and the tenth connecting via.

S26, forming a signal Input end, a first signal Output end Output1, a second signal Output end Output2, a first control signal end and a second control signal end on the glass substrate 10 after the step S25 is completed; the signal Input end is connected with the first lead end 22 of the first inductor L1 through a sixth connecting via hole penetrating through the first interlayer dielectric layer 40; the first signal Output end 1 is connected to the second plate 32 of the third capacitor C3 through a seventh connection via penetrating through the first interlayer dielectric layer 40; the second signal Output terminal Output2 is connected to the first lead terminal 22 of the second inductor L2 through an eighth connecting via hole penetrating through the first interlayer dielectric layer 40; the first control signal terminal is connected with the gate of the first switching transistor T1 through a ninth connection via hole penetrating through the first interlayer dielectric layer 40; the second control signal terminal is connected to the gate of the second switching transistor T2 and the gate 103 of the third switching transistor T3 through a tenth connection via penetrating the first interlayer dielectric layer 40, as shown in fig. 9a and 9 b.

In some examples, step S15 may include depositing a third metal film by magnetron sputtering, performing glue coating, exposure, development, performing wet etching, and removing strip after etching to form a pattern including a signal Input terminal Input, a first signal Output terminal Output1, a second signal Output terminal Output2, a first control signal terminal, and a second control signal terminal. The material of the third metal film may be the same as the material of the first metal film, and therefore, the description thereof is omitted.

S27, fifth connection pads 55, sixth connection pads 56, seventh connection pads 57, eighth connection pads 58 and ninth connection pads 59 are formed on the glass substrate 10 completing the step S26, as shown in fig. 9a and 9 b. The fifth connection pad 55 covers a side of the signal Input end, which is away from the substrate; the sixth connection pad 56 covers a side of the first signal Output terminal Output1 facing away from the substrate base plate; the seventh connection pad 57 covers a side of the second signal Output terminal Output2 facing away from the substrate base plate; the eighth connection pad 58 covers a side of the first control signal terminal facing away from the substrate base plate; the ninth connection pad 59 covers a side of the second control signal terminal facing away from the substrate base plate.

In some examples, fifth connection pad 55, sixth connection pad 56, seventh connection pad 57, eighth connection pad 58, and ninth connection pad 59 include, but are not limited to, solder.

The preparation of the tunable filter shown in fig. 8 is completed.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the utility model, and these modifications and improvements are also considered to be within the scope of the utility model.

Claims

1. A tunable filter, comprising:

2. The tunable filter of claim 1, wherein the at least one capacitor comprises a first capacitor and a second capacitor; the number of the inductors is one; the second capacitor comprises a first polar plate and a second polar plate which are sequentially arranged along the direction departing from the substrate, and the second capacitor is positioned between the first polar plate and the second polar plate and is arranged on the P-type semiconductor layer, the intrinsic semiconductor layer and the N-type semiconductor layer in a laminated manner;

a first lead end of the inductor is connected with a first signal end, and a second lead end of the inductor is connected with a second signal end and a first polar plate of the first capacitor; the second plate of the first capacitor is connected with the second plate of the second capacitor and a first bias voltage end; and the first polar plate of the second capacitor is connected with a second bias voltage end.

3. The tunable filter of claim 2, wherein the second substructure of the inductor, the first plate of the first capacitor, and the first plate of the second capacitor are disposed in the same layer and are made of the same material; and/or the presence of a gas in the gas,

4. The tunable filter according to claim 2 or 3, wherein a first interlayer dielectric layer is disposed on a side of the second plate of the second capacitor away from the substrate, and the first signal terminal, the second signal terminal, a first bias voltage terminal, and the second bias voltage terminal are formed on a side of the first interlayer dielectric layer away from the substrate;

5. The tunable filter of claim 4, further comprising a first connection pad, a second connection pad, a third connection pad, and a fourth connection pad on a side of a layer where the first signal terminal, the second signal terminal, the first bias voltage terminal, and the second bias voltage terminal are located away from the substrate base plate;

6. The tunable filter of claim 1, wherein the at least one inductor comprises a first inductor and a second inductor; the at least one capacitor comprises a third capacitor and a fourth capacitor;

the tunable filter comprises a first resonant unit, a second resonant unit, a first switching transistor, a second switching transistor and a third switching transistor; wherein the first resonance unit comprises a first inductor and a third capacitor; the second resonance unit comprises a second inductor and a fourth capacitor;

7. The tunable filter of claim 6, wherein the second substructure of the first inductor, the second substructure of the second inductor, the first plate of the third capacitor, the first plate of the fourth capacitor, the first and second poles of the first switch transistor, the first and second poles of the second switch transistor, and the first and second poles of the third switch transistor are disposed in the same layer and are made of the same material; and/or the presence of a gas in the gas,

8. The tunable filter according to claim 6 or 7, wherein a first interlayer dielectric layer is disposed on a side of the second plate of the third capacitor away from the substrate, and the third signal terminal, the fourth signal terminal, and the fifth signal terminal are formed on a side of the first interlayer dielectric layer away from the substrate; the first control signal terminal and the second control signal terminal;

9. The tunable filter of claim 8, further comprising a fifth connection pad, a sixth connection pad, a seventh connection pad, an eighth connection pad, and a ninth connection pad on a side of a layer where the third signal terminal, the fourth signal terminal, the fifth signal terminal, the first control signal terminal, and the second control signal terminal are located away from the substrate base plate;

10. The tunable filter of claim 1, wherein the substrate base plate comprises a glass base.