CN111341754A - Manufacturing method of super-thick adapter plate - Google Patents
Manufacturing method of super-thick adapter plate Download PDFInfo
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- CN111341754A CN111341754A CN202010132309.1A CN202010132309A CN111341754A CN 111341754 A CN111341754 A CN 111341754A CN 202010132309 A CN202010132309 A CN 202010132309A CN 111341754 A CN111341754 A CN 111341754A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
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Abstract
The invention discloses a method for manufacturing an ultra-thick adapter plate, which specifically comprises the following steps: 101) an upper surface treatment step, 102) a lower surface treatment step, 103) a cutting and forming step; the invention provides a method for manufacturing an ultra-thick adapter plate, which is convenient to manufacture, simplified in process, relatively small in size and high in thickness.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an ultra-thick adapter plate.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
In the background of the era of post moore's law, it has become more difficult to increase the degree of integration by means of conventional shrinking transistor dimensions. The existing electronic system is developing towards miniaturization, diversification and intellectualization, and finally a high-integration-level low-cost integrated electronic system with integration of multiple functions such as perception, communication, processing, transmission and the like is formed. The core technology of the multifunctional integrated electronic system is integration, and the multifunctional integrated electronic system is developing from plane integration to three-dimensional integration and from chip level to system level integration with higher integration level and complexity. The three-dimensional integrated system-in-package can solve the problem of integrating more transistors in the same area, and is a development direction in the future.
The structure of making the support plate or the cover plate to make the system-in-package through the adapter plate can change the plane layout of a chip into a stacked layout on the framework, and can integrate systems such as passive devices or discrete elements and the like to construct, so that the precision and the density are increased, the performance is greatly improved, the development trend of the future radio frequency integrated circuit technology is represented, and great advantageous characteristics exist in multiple aspects:
a) the three-dimensional heterogeneous integrated system-in-package adopts a chip shell to complete all interconnection of a system, so that the total welding spots are greatly reduced, the connecting line distance of elements is shortened, and the electrical property is improved.
b) Two or more chips are stacked in the same adapter plate chip in the three-dimensional heterogeneous integrated system-in-package (SIP) mode, the space in the Z direction is also utilized, package pins do not need to be added, the area ratio of the two chips stacked in the same shell to the chips is larger than 100%, and the stacking of the three chips can be increased to 250%;
c) small physical size and light weight. For example, the most advanced technology can realize the ultrathin thickness of 4-layer stacked chips with the thickness of only 1mm, and the weight of three-layer stacked chips is reduced by 35%;
different technologies (such as MEMS technology, SiGe HBT, SiGe BiCMOS, Si CMOS, III-V (InP, GaN, GaAs) MMIC technology and the like) and chips (such as radio frequency, biological, micro-electro-mechanical and photoelectric chips and the like) made of different materials (such as Si, GaAs and InP) and having different functions are assembled to form a system, so that the system has good compatibility and can be combined with integrated passive elements. There is data showing that passive components currently used in radio and portable electronic machines can be embedded at least 30-50%.
However, in practical application, the application of the adapter plate is not widely popularized, mainly because the process for manufacturing the adapter plate is too complex, and the thickness of the adapter plate is usually not more than 200um, a temporary bonding process is required in the manufacturing process, the input cost and the manufacturing cost are high, and the development of the adapter plate in the civil field is limited.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides the manufacturing method of the ultra-thick adapter plate with convenient manufacturing, simplified process, relatively small size and high thickness.
The technical scheme of the invention is as follows:
a manufacturing method of an ultra-thick adapter plate specifically comprises the following steps:
101) an upper surface treatment step: preparing an adapter plate, and manufacturing a groove on the upper surface of the adapter plate through photoetching and etching processes; depositing silicon oxide or silicon nitride on the upper surface of the adapter plate, or directly thermally oxidizing to form an insulating layer; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; electroplating metal to make the metal cover the surface of the groove to form a metal layer, and densifying the metal layer at 200-500 ℃ to make the metal layer denser; flattening the upper surface of the adapter plate by a CMP process;
filling the groove by using a spin coating process or a pressing process, wherein the filling material is photoresist, epoxy resin, thermosetting adhesive, glass powder or an inorganic material, and removing the filling material overflowing the surface of the groove by using an etching or grinding process to only leave the filling material in the groove; depositing a seed layer on the upper surface of the adapter plate by using a PVD (physical vapor deposition) process, and manufacturing an RDL (remote direct memory) and an interconnection pad by using photoetching and electroplating processes;
102) a lower surface treatment step: thinning the lower surface of the adapter plate, wherein the thinning thickness is between 10um and 1000um, forming a cavity on the lower surface of the adapter plate through photoetching and etching processes, wherein the bottom of the cavity is in contact with the bottom of the groove, and the metal layer at the bottom of the groove is exposed;
depositing silicon oxide or silicon nitride on the lower surface of the adapter plate to form an insulating layer, and removing the insulating layer covering the metal layer at the bottom of the cavity through dry etching; covering a seed layer on the lower surface of the adapter plate by a physical sputtering, magnetron sputtering or evaporation process; electroplating metal to cover the surface of the cavity to form a metal layer, and densifying the metal layer at 200-500 ℃ to make the metal layer denser;
filling the cavity by using a spin coating process or a pressing process, wherein the filling material is photoresist, epoxy resin, thermosetting adhesive, glass powder or an inorganic material, and removing the filling material overflowing the surface of the cavity by using an etching or grinding process to only leave the filling material in the cavity; depositing a seed layer on the lower surface of the adapter plate by using a PVD (physical vapor deposition) process, and manufacturing an RDL (remote direct memory) and an interconnection pad by using photoetching and electroplating processes;
103) cutting and forming: and cutting the interconnected grooves and cavities to obtain the required adapter plate which is interconnected up and down, and pasting a chip on the surface of the adapter plate through an FC (fiber channel) process to form an adapter plate chip.
Furthermore, the openings of the groove and the cavity are circular, oval or rectangular, the diameter or side length range of the groove and the cavity is 10nm to 1000um, and the depth range is 10nm to 1000 um;
the thickness of the insulating layer ranges from 10nm to 100 um;
the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Furthermore, the size of the adapter plate is one of 4, 6, 8 and 12 inches, the thickness of the adapter plate is 200um to 2000um, and the adapter plate is made of one of silicon, glass, quartz, silicon carbide, aluminum oxide, epoxy resin or polyurethane.
Further, in step 101), before filling the groove on the interposer, removing the insulating layer on the surface of the interposer by using a dry etching or wet etching process.
Furthermore, before a seed layer is deposited on the upper surface of the adapter plate by using a PVD (physical vapor deposition) process, an insulating layer is deposited and generated.
Furthermore, the adapter plate is made of a silicon wafer with an SOI layer, and the bottom of the groove just penetrates through the SOI layer.
Compared with the prior art, the invention has the advantages that: according to the invention, the grooves and the cavities with the metal layers on the two surfaces are manufactured on the adapter plate wafer, so that the upper surface and the lower surface of the adapter plate wafer can be electrically interconnected, the adapter plate wafer can be conveniently manufactured without a temporary bonding process, the manufacturing cost of the adapter plate is greatly reduced, and the popularization of the adapter plate is powerfully promoted.
Drawings
FIG. 1 is a schematic view of an adapter plate of the present invention;
FIG. 2 is a schematic view of the present invention illustrating the formation of grooves in FIG. 1;
FIG. 3 is a schematic view of the electroplated metal layer of FIG. 2 in accordance with the present invention;
FIG. 4 is a schematic view of the groove of FIG. 3 of the present invention in a circular shape;
FIG. 5 is an elliptical shape of the groove of FIG. 3 according to the present invention;
FIG. 6 is a schematic view of the invention with the groove of FIG. 3 being rectangular;
FIG. 7 is a schematic view of a cavity formed in the lower surface of the interposer of FIG. 3 according to the present invention;
FIG. 8 is a schematic view of the metal layer of FIG. 7 according to the present invention;
FIG. 9 is a schematic illustration of the groove and cavity filling material of FIG. 8 according to the present invention;
FIG. 10 is a schematic view of the present invention of FIG. 9 cut to form individual interposer chips;
FIG. 11 is a schematic view of an interposer with SOI layer according to the present invention;
FIG. 12 is a schematic view of the invention illustrating the formation of grooves in FIG. 11;
FIG. 13 is a schematic view of the electroplated metal layer of FIG. 12 in accordance with the present invention;
FIG. 14 is a schematic view of a cavity formed in the lower surface of the interposer of FIG. 13 according to the present invention;
FIG. 15 is a schematic view of the metal layer of FIG. 14 according to the present invention;
FIG. 16 is a schematic illustration of the groove and cavity filling material of FIG. 15 according to the present invention;
FIG. 17 is a schematic view of the FIG. 16 cut to form individual interposer chips in accordance with the present invention.
The labels in the figure are: interposer 101, recess 102, metal layer 103.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
Example 1:
as shown in fig. 1 to 10, a method for manufacturing an ultra-thick interposer specifically includes the following steps:
101) an upper surface treatment step: preparing an adapter plate 101, and manufacturing a groove 102 on the upper surface of the adapter plate 101 through photoetching and etching processes, wherein the opening of the groove 102 can be in a shape of a circle, an ellipse, a rectangle and the like, the diameter or the side length range of the groove is 10nm to 1000um, and the depth range of the groove is 10nm to 1000 um. And depositing silicon oxide or silicon nitride on the upper surface of the adapter plate 101, or directly thermally oxidizing to form an insulating layer, wherein the thickness of the insulating layer ranges from 10nm to 100 um. A seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel. Electroplating metal to enable the metal to cover the surface of the groove 102 to form a metal layer 103, and densifying the metal layer 103 at the temperature of 200-500 ℃ to enable the metal layer 103 to be more dense; the upper surface of the interposer 101 is planarized by a CMP process. The insulating layer on the surface of the interposer 101 may be removed by dry etching or wet etching, and may be naturally retained.
The groove 102 is filled by spin coating or pressing, and the filling material may be photoresist, epoxy resin, thermosetting adhesive, glass powder, inorganic material, etc. The filling material overflowing the surface of the groove 102 is removed by etching or grinding process, and only the filling material in the groove 102 is left. A seed layer is deposited on the upper surface of the adapter plate 101 by a PVD (physical vapor deposition) process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel. The RDL and interconnect pads are fabricated by photolithography and electroplating processes.
102) A lower surface treatment step: the lower surface of the adapter plate 101 is thinned, the thinning thickness is 10um to 1000um, a cavity is formed in the lower surface of the adapter plate 101 through photoetching and etching processes, the bottom of the cavity is in contact with the bottom of the groove 102, and the metal layer 103 at the bottom of the groove 102 is exposed. The openings of the cavities are circular, oval or rectangular, the diameter or side length range of the cavities is 10nm to 1000um, and the depth range is 10nm to 1000 um.
And depositing silicon oxide or silicon nitride on the lower surface of the adapter plate 101 to form an insulating layer, and removing the insulating layer covering the metal layer 103 at the bottom of the cavity by dry etching. The seed layer is covered on the lower surface of the adapter plate 101 through a physical sputtering, magnetron sputtering or evaporation process, and the seed layer is made of conductive metal, so that part of the seed layer does not need to be removed. And electroplating metal to cover the surface of the cavity to form a metal layer 103, and densifying the metal layer 103 at a temperature of 200 to 500 ℃ to densify the metal layer 103.
Filling the cavity by using a spin coating process or a pressing process, wherein the filling material is photoresist, epoxy resin, thermosetting adhesive, glass powder or inorganic material, and removing the filling material overflowing the surface of the cavity by using an etching or grinding process to only leave the filling material in the cavity. Depositing a seed layer on the lower surface of the adapter plate 101 by using a PVD (physical vapor deposition) process, and manufacturing an RDL (remote direct memory) and an interconnection pad by using photoetching and electroplating processes; before the seed layer is deposited on the lower surface of the interposer 101 by PVD process, an insulating layer may be deposited.
103) Cutting and forming: and cutting the interconnected grooves 102 and cavities to obtain the required upper and lower interconnected adapter plate 101, and mounting a chip on the surface of the adapter plate 101 by an FC (chip on chip) process to form the chip of the adapter plate 101.
The size of the adapter plate 101 is one of 4 inches, 6 inches, 8 inches and 12 inches, the thickness of the adapter plate 101 is 200um to 2000um, the adopted material is a silicon wafer, and other materials can be adopted, including inorganic materials such as glass, quartz, silicon carbide and alumina, and organic materials such as epoxy resin and polyurethane can be adopted, and the main function of the adapter plate is to provide a supporting function.
Example 2:
embodiment 2 is the same as embodiment 1 as a whole except that a silicon wafer with an SOI layer is used for the interposer 101 and the bottom of the groove 102 just penetrates the SOI layer. The specific manufacturing process is shown in fig. 11 to 17 as follows:
101) an upper surface treatment step: preparing an adapter plate 101, manufacturing a groove 102 on the upper surface of the adapter plate 101 through photoetching and etching processes, wherein the groove 102 is stopped on an SOI layer, etching the groove 102 continuously by replacing etching gas, and etching is stopped on a silicon material below the SOI layer. The opening of the groove 102 may be circular, oval, rectangular, etc., and the diameter or side length range thereof is 10nm to 1000um, and the depth range thereof is 10nm to 1000 um.
And depositing silicon oxide or silicon nitride on the upper surface of the adapter plate 101, or directly thermally oxidizing to form an insulating layer, wherein the thickness of the insulating layer ranges from 10nm to 100 um. A seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel. Electroplating metal to enable the metal to cover the surface of the groove 102 to form a metal layer 103, and densifying the metal layer 103 at the temperature of 200-500 ℃ to enable the metal layer 103 to be more dense; the upper surface of the interposer 101 is planarized by a CMP process. The insulating layer on the surface of the interposer 101 may be removed by dry etching or wet etching, and may be naturally retained.
The groove 102 is filled by spin coating or pressing, and the filling material may be photoresist, epoxy resin, thermosetting adhesive, glass powder, inorganic material, etc. The filling material overflowing the surface of the groove 102 is removed by etching or grinding process, and only the filling material in the groove 102 is left. A seed layer is deposited on the upper surface of the adapter plate 101 by a PVD (physical vapor deposition) process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel. The RDL and interconnect pads are fabricated by photolithography and electroplating processes.
102) A lower surface treatment step: the lower surface of the adapter plate 101 is thinned, the thinning thickness is 10um to 1000um, a cavity is formed in the lower surface of the adapter plate 101 through photoetching and etching processes, the bottom of the cavity is in contact with the bottom of the groove 102, and the metal layer 103 at the bottom of the groove 102 is exposed. The openings of the cavities are circular, oval or rectangular, the diameter or side length range of the cavities is 10nm to 1000um, and the depth range is 10nm to 1000 um.
And depositing silicon oxide or silicon nitride on the lower surface of the adapter plate 101 to form an insulating layer, and removing the insulating layer covering the metal layer 103 at the bottom of the cavity by dry etching. The seed layer is covered on the lower surface of the adapter plate 101 through a physical sputtering, magnetron sputtering or evaporation process, and the seed layer is made of conductive metal, so that part of the seed layer does not need to be removed. And electroplating metal to cover the surface of the cavity to form a metal layer 103, and densifying the metal layer 103 at a temperature of 200 to 500 ℃ to densify the metal layer 103.
Filling the cavity by using a spin coating process or a pressing process, wherein the filling material is photoresist, epoxy resin, thermosetting adhesive, glass powder or inorganic material, and removing the filling material overflowing the surface of the cavity by using an etching or grinding process to only leave the filling material in the cavity. Depositing a seed layer on the lower surface of the adapter plate 101 by using a PVD (physical vapor deposition) process, and manufacturing an RDL (remote direct memory) and an interconnection pad by using photoetching and electroplating processes; before the seed layer is deposited on the lower surface of the interposer 101 by PVD process, an insulating layer may be deposited.
103) Cutting and forming: and cutting the interconnected grooves 102 and cavities to obtain the required upper and lower interconnected adapter plate 101, and mounting a chip on the surface of the adapter plate 101 by an FC (chip on chip) process to form the chip of the adapter plate 101.
The size of the adapter plate 101 is one of 4 inches, 6 inches, 8 inches and 12 inches, the thickness of the adapter plate 101 is 200um to 2000um, the adopted material is a silicon wafer, and other materials can be adopted, including inorganic materials such as glass, quartz, silicon carbide and alumina, and organic materials such as epoxy resin and polyurethane can be adopted, and the main function of the adapter plate is to provide a supporting function.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (6)
1. The manufacturing method of the ultra-thick adapter plate is characterized by comprising the following steps:
101) an upper surface treatment step: preparing an adapter plate, and manufacturing a groove on the upper surface of the adapter plate through photoetching and etching processes; depositing silicon oxide or silicon nitride on the upper surface of the adapter plate, or directly thermally oxidizing to form an insulating layer; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; electroplating metal to make the metal cover the surface of the groove to form a metal layer, and densifying the metal layer at 200-500 ℃ to make the metal layer denser; flattening the upper surface of the adapter plate by a CMP process;
filling the groove by using a spin coating process or a pressing process, wherein the filling material is photoresist, epoxy resin, thermosetting adhesive, glass powder or an inorganic material, and removing the filling material overflowing the surface of the groove by using an etching or grinding process to only leave the filling material in the groove; depositing a seed layer on the upper surface of the adapter plate by using a PVD (physical vapor deposition) process, and manufacturing an RDL (remote direct memory) and an interconnection pad by using photoetching and electroplating processes;
102) a lower surface treatment step: thinning the lower surface of the adapter plate, wherein the thinning thickness is between 10um and 1000um, forming a cavity on the lower surface of the adapter plate through photoetching and etching processes, wherein the bottom of the cavity is in contact with the bottom of the groove, and the metal layer at the bottom of the groove is exposed;
depositing silicon oxide or silicon nitride on the lower surface of the adapter plate to form an insulating layer, and removing the insulating layer covering the metal layer at the bottom of the cavity through dry etching; covering a seed layer on the lower surface of the adapter plate by a physical sputtering, magnetron sputtering or evaporation process; electroplating metal to cover the surface of the cavity to form a metal layer, and densifying the metal layer at 200-500 ℃ to make the metal layer denser;
filling the cavity by using a spin coating process or a pressing process, wherein the filling material is photoresist, epoxy resin, thermosetting adhesive, glass powder or an inorganic material, and removing the filling material overflowing the surface of the cavity by using an etching or grinding process to only leave the filling material in the cavity; depositing a seed layer on the lower surface of the adapter plate by using a PVD (physical vapor deposition) process, and manufacturing an RDL (remote direct memory) and an interconnection pad by using photoetching and electroplating processes;
103) cutting and forming: and cutting the interconnected grooves and cavities to obtain the required adapter plate which is interconnected up and down, and pasting a chip on the surface of the adapter plate through an FC (fiber channel) process to form an adapter plate chip.
2. The method for manufacturing the ultra-thick adapter plate according to claim 1, wherein the openings of the groove and the cavity are circular, elliptical or rectangular, the diameter or side length range of the groove and the cavity is 10nm to 1000um, and the depth range is 10nm to 1000 um;
the thickness of the insulating layer ranges from 10nm to 100 um;
the thickness of the seed layer ranges from 1nm to 100um, the seed layer is of one-layer or multi-layer structure, and the metal material of each layer is one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
3. The method of claim 1, wherein the adapter plate has a size of 4, 6, 8, or 12 inches, a thickness of 200um to 2000um, and is made of one of silicon, glass, quartz, silicon carbide, alumina, epoxy resin, or polyurethane.
4. The method for manufacturing the ultra-thick interposer as claimed in claim 1, wherein the insulating layer on the interposer surface is removed by dry etching or wet etching before the step 101) of filling the grooves on the interposer.
5. The method of claim 1, wherein an insulating layer is deposited on the upper surface of the interposer before the seed layer is deposited thereon by PVD.
6. The method of claim 1, wherein the interposer is a silicon wafer with an SOI layer, and the bottom of the trench passes through the SOI layer.
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