CN114446915A - 半导体器件和生产半导体器件的方法 - Google Patents

半导体器件和生产半导体器件的方法 Download PDF

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CN114446915A
CN114446915A CN202111282568.3A CN202111282568A CN114446915A CN 114446915 A CN114446915 A CN 114446915A CN 202111282568 A CN202111282568 A CN 202111282568A CN 114446915 A CN114446915 A CN 114446915A
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clip
semiconductor device
groove
solder
fillet
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里卡多·杨多克
安东尼·马修
马诺耶·巴拉克瑞南
亚当·布朗
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Nexperia BV
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Abstract

本发明的公开涉及一种半导体器件和生产半导体器件的方法，该半导体器件包括夹片和嵌条，其中夹片包括夹片槽并且嵌条包括沟槽。夹片和嵌条通过超声波焊接附接。沟槽和夹片槽至少部分地重叠以形成气体通路。

Description

半导体器件和生产半导体器件的方法
技术领域
本发明涉及一种形成半导体器件的方法。本发明还涉及一种生产半导体器件的方法。
背景技术
作为工业过程的超声波焊接是本领域已知的。超声波焊接利用了高频超声波声学振动(high-frequency ultrasonic acoustic vibration)，该高频超声波声学振动在压力下被局部施加至保持在一起的工件上以产生固态焊接部。超声波焊接通常用于塑料和金属工业中，并且它也可以用于接合异种材料。在超声波焊接中，没有用于将材料结合在一起所需的连接性螺栓、钉子、焊接材料或粘合剂。当超声波焊接用于金属时，这种方法的一个显著特征是温度保持远低于所涉及材料的熔点。这防止了可能由金属材料暴露于高温而引起的任何不希望的性质。
超声波焊接的已知应用是广泛的，并且可以在许多工业中找到应用，包括电气和计算机、汽车和航空航天、医药、包装、半导体工业等。两个物品是否可以被超声波焊接是由它们的厚度决定的。如果它们太厚，则这种工艺不会将它们接合在一起。这是金属焊接中的主要障碍。然而，导线、微电路连接部、金属片、箔、带和网经常使用超声波焊接来接合。
在半导体、电气和计算机工业中，通常使用超声波焊接来接合带有线的连接部并在小的精密半导体电路中形成连接。
最常使用超声波焊接并且新的研究和实验比较倾斜的领域之一是微电路。超声波焊接工艺对于微电路是理想的，因为它产生可靠的键合而不会在部件中引入杂质或热变形。半导体器件、晶体管和二极管通常使用超声波焊接通过细的铝线和金线连接起来。超声波焊接也用于将配线、带以及整个芯片键合至微电路。
与诸如软钎焊等传统接合技术相比，超声波焊接在提高功率循环可靠性和产量方面是有利的。
在MOSFET半导体器件的情况下，可以使用超声波焊接将嵌条焊接到夹片上。这种具有焊接嵌条的夹片被焊接到硅MOSFET裸片上。在这种情况下，在所述焊接期间可能截留气体，这可能导致形成焊料空隙。当该过程用于制造半导体晶体管器件时，这种过量的焊料可能沿着夹片的边缘扩散，这可能容易导致到晶体管的栅极或漏极端子的潜在桥接。
发明内容
各种示例性实施例针对如上的缺点和/或从以下公开内容可以变得明显的其他缺点。
根据本发明的实施例，半导体器件包括夹片和嵌条，其中，夹片包括夹片槽并且嵌条包括沟槽。夹片和嵌条通过超声波焊接彼此连接。沟槽和夹片槽至少部分地相互重叠以形成气体通路。沟槽定位在嵌条的底面上，其中嵌条经由该底面连接至夹片。
根据本发明的实施例，半导体器件还包括引线框架、定位在引线框架的顶部上的第一焊料、定位在第一焊料的顶部上的硅裸片、定位在硅裸片的顶部上的第二焊料，其中夹片定位在第二焊料的顶部上。
根据本发明的实施例，半导体器件包括至少两个沟槽和至少两个夹片槽。这些沟槽和夹片槽可以彼此完全或部分地重叠。这些沟槽和夹片槽可以是各种形状的。
根据本发明的实施例，沟槽和夹片槽显著地重叠，并且它们形成交叉形状或加号形状。
根据本发明的另一实施例，沟槽和夹片槽部分地重叠。沟槽和夹片槽形成矩形形状，其中沟槽对应于矩形形状的两条第一边，并且夹片槽对应于矩形形状的两条第二边，并且沟槽和夹片槽之间的重叠仅位于矩形形状的顶点处。
本发明还涉及一种生产根据以上实施例中所述的半导体器件的方法。
本发明涉及一种生产半导体器件的方法，该方法包括以下步骤：
-在裸片焊盘上进行焊料模板印刷，
-将裸片附接至裸片焊盘，
-将焊料分配在裸片的顶部上，
-使用超声波焊接将嵌条附接至夹片，其中嵌条包括沟槽并且其中夹片包括夹片槽，其中当将嵌条附接至夹片时沟槽和夹片槽至少部分地重叠，并且其中沟槽被定位在嵌条的用于将嵌条附接至夹片的一侧上，以及
-成型、PMC去飞边和镀覆。
根据本发明实施例的半导体器件显著地改善了可焊性和最终的焊料质量。这显著地降低了空隙的可能性。
如上所述，形成气体通路确保了将在焊料回流过程期间清除任何存在的气体。这降低了在裸片和夹片之间的焊料中形成空隙的机会。这意味着器件的最终热性能和电性能(例如RDSon)得到了提高。
附图说明
为了能够详细理解本发明的公开的特征，参考实施例进行更具体的描述，其中一些实施例在附图中示出。然而，应当注意，附图仅示出了典型的实施例，因此不应被认为是对其范围的限制。附图是为了便于理解本发明的公开，因此不一定按比例绘制。在结合附图阅读本说明书之后，所要求保护的主题的优点对于本领域技术人员将变得显而易见，在附图中，相似的附图标记用于表示相似的元件，并且其中：
图1a、图1b、图1c、图1d和图1e示出了根据本发明实施例的半导体器件；
图2示出了根据本发明实施例的半导体器件；
图3a、图3b和图3c示出了根据本发明实施例的半导体器件；
图4示出了根据本发明的三个实施例的三个半导体器件。
具体实施方式
根据本发明的实施例，半导体器件包括嵌条(slug)，该嵌条在嵌条的底面上包括沟槽或沟道。嵌条的底面被超声波焊接到用于双侧冷却封装件的带有槽的夹片(clip)上。
上述设计使得能够在焊料回流期间进行焊剂除气(flux outgassing)，因为沟槽产生了通道，使得气体能够通过该通道逸出。这是通过如下沟槽或沟道实现的：该沟槽或沟道可以定位成横跨嵌条的整个长度并且与夹片上的槽至少部分地重叠。
在本发明的各种实施例中，沟槽(一个或多个)和槽(一个或多个)可以(合理地)具有相同、相似或不同的几何形状。本发明的基本特征在于沟槽(一个或多个)和槽(一个或多个)彼此重叠。以这种方式，可以存在有如下连续路径：该连续路径从夹片下方的焊料开始，通过槽，进入嵌条的沟槽(一个或多个)，然后到达嵌条的外部。
槽和沟槽的重叠也有助于管理这些部件的热膨胀系数(CTE)，这显著地提高了半导体器件的可靠性。
本发明的上述实施例解决了如本领域已知的半导体器件中存在的所述缺点，因为本发明的实施例通过降低空隙的可能性改善了可焊性和最终的焊接质量。
通过在嵌条中使用与夹片槽至少部分重叠的沟槽或沟道，将形成通路，该通路将确保任何存在的气体将在焊料回流过程期间逸出(即，被清除)。这直接降低了在裸片和夹片之间的焊料中形成空隙的可能性。防止形成这些空隙是非常重要的，因为空隙会影响半导体器件的最终热和电性能，例如在晶体管半导体器件的情况下会影响漏源导通电阻(RDSon)。
在图1a、图1b、图1c、图1d和图1e中示出了本发明的实施例。半导体器件包括嵌条10，该嵌条10包括沟槽或沟道12。图1a、图1b和图1c分别示出了具有沟槽12的嵌条10的顶视图、底视图和剖面图。图1d和图1e分别示出了超声波焊接之后的具有沟槽的嵌条的顶视图和剖面图。
在图2中示出了本发明的实施例。从两个不同的剖面，第一剖面A-A 40和第二剖面B-B 42，示出了半导体器件50。半导体器件50包括：
-引线框架22，
-定位在引线框架22的顶部上的第一焊料18，
-定位在第一焊料18的顶部上的硅裸片16，
-定位在硅裸片16的顶部上的第二焊料17，
-夹片30，其中夹片包括夹片槽14，其中夹片30定位在第二焊料17的顶部上，
-嵌条10，其中嵌条包括沟槽或沟道12，其中嵌条10定位在夹片30的顶部上，
-其中，沟槽12和槽14至少部分地相互重叠，以形成气体通路20。
该气体通路20确保任何存在的气体将在焊料回流过程期间逸出(即，被清除)。如前所述，本发明实施例的这个特征将降低在硅裸片16与夹片30之间的焊料中形成空隙的机会。再一次，这将确保半导体器件的高质量热性能和电性能。
在图3a、图3b和图3c中示出了本发明的实施例。图3a、图3b和图3c分别示出了在超声波键合之前、期间和之后嵌条10和夹片30的相互位置。图3b中示出了超声波键合机60。如图3a所示，嵌条10的沟槽/沟道12相对于夹片30的夹片槽14对准，即沟槽/沟道12与夹片槽14完全重叠。以这种方式形成气体通路。
以这种方式形成的夹片30可以进一步用在夹片附接过程中，以用于构建双侧冷却封装件。
本发明的实施例涉及一种形成双侧冷却封装件的方法。该方法包括以下步骤：
-在裸片焊盘/引线框架上进行焊料模板印刷(solder stencil printing)，
-利用焊料将裸片附接至裸片焊盘引线框架，
-将焊料分配在裸片的顶部上，
-使用凹槽式超声波焊接(grooved ultrasonic welding)来附接夹片，该步骤在图3a、图3b和图3c中更详细地示出，以及
-成型、PMC去飞边(deflash)和镀覆。
沟槽和夹片槽的形状和位置不限于本发明的上述实施例。本发明包括沟槽和夹片槽的形状和相互位置的所有明显变型。
在图4所示的本发明的示例性实施例中，示出了交叉形状70和加号形状80的变型，其中沟槽和夹片槽彼此显著重叠。
在图4所示的本发明的另一示例性实施例中，沟槽和夹片槽彼此没有显著重叠。该实施例用附图标记90表示。在该实施例中，沟槽和夹片槽仅在四个重叠点92处部分地重叠。
在所附独立权利要求中阐述了本发明的特定和优选方面。从属和/或独立权利要求的特征的组合可以适当地组合，而不仅仅是如权利要求中所阐述的。
本发明的公开的范围包括其中明确地或隐含地公开的任何的新特征或特征的组合或其任何概括，而不管是否涉及所要求保护的发明或减轻本发明解决的任何或所有问题。申请人特此提请注意，在本申请或从其导出的任何这种进一步申请的审查期间，可以针对这些特征提出新的权利要求。特别地，参考所附权利要求，来自从属权利要求的特征可以与独立权利要求的特征组合，并且来自各个独立权利要求的特征可以以任何适当的方式组合，而不仅仅是在权利要求中列举的特定组合。
在单独实施例的上下文中描述的特征也可以在单个实施例中组合提供。相反，为简洁起见在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合提供。
术语“包括”不排除其他元件或步骤，术语“一”或“一个”不排除多个。权利要求中的附图标记不应被解释为限制权利要求的范围。

Claims (8)

1.一种半导体器件，包括：
-夹片，其中所述夹片包括夹片槽，以及
-嵌条，其中所述嵌条包括沟槽，
-其中所述沟槽和所述夹片槽至少部分地重叠以形成气体通路。
2.根据权利要求1所述的半导体器件，其中，所述夹片和所述嵌条通过超声波焊接连接。
3.根据前述权利要求中任一项所述的半导体器件，其中，所述半导体器件还包括：
-引线框架，
-定位在所述引线框架的顶部上的第一焊料，
-定位在所述第一焊料的顶部上的硅裸片，
-定位在所述硅裸片的顶部上的第二焊料，
-所述夹片和所述嵌条定位在所述第二焊料的顶部上。
4.根据前述权利要求中任一项所述的半导体器件，其中，所述半导体器件包括至少两个沟槽和至少两个夹片槽。
5.根据权利要求4所述的半导体器件，其中，所述沟槽和所述夹片槽彼此重叠，并且所述沟槽和所述夹片槽均形成交叉形状或加号形状。
6.根据权利要求4所述的半导体器件，其中，所述沟槽和所述夹片槽彼此部分地重叠，并且所述沟槽和所述夹片槽形成矩形形状，所述沟槽对应于所述矩形形状的两条第一边，并且所述夹片槽对应于所述矩形形状的两条第二边，并且所述沟槽与所述夹片槽之间的重叠位于所述矩形形状的顶点处。
7.一种生产根据前述权利要求中任一项所述的半导体器件的方法。
8.一种生产半导体器件的方法，所述方法包括以下步骤：
-在裸片焊盘上进行焊料模板印刷，
-将裸片附接至所述裸片焊盘，
-将焊料分配在所述裸片的顶部上，
-使用超声波焊接将嵌条附接至夹片，其中所述嵌条包括沟槽，并且所述夹片包括夹片槽，当将所述嵌条附接至所述夹片时所述沟槽和所述夹片槽至少部分地重叠，并且所述沟槽被定位在所述嵌条的用于将所述嵌条附接所述夹片的一侧上，以及
-成型、PMC去飞边和镀覆。
CN202111282568.3A 2020-11-04 2021-11-01 半导体器件和生产半导体器件的方法 Pending CN114446915A (zh)

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