CN114388640A - Preparation method of silicon-based heterojunction solar cell - Google Patents

Preparation method of silicon-based heterojunction solar cell Download PDF

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CN114388640A
CN114388640A CN202011133338.6A CN202011133338A CN114388640A CN 114388640 A CN114388640 A CN 114388640A CN 202011133338 A CN202011133338 A CN 202011133338A CN 114388640 A CN114388640 A CN 114388640A
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silicon wafer
layer
silicon
diffusion
amorphous silicon
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许志
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Xifeng 2d Fujian Material Technology Co ltd
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Xifeng 2d Fujian Material Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a preparation method of a silicon-based heterojunction solar cell, which comprises the following steps: providing an N-type monocrystalline silicon wafer; chemical polishing: processing the mechanical damage layer of the silicon wafer to remove impurities on the surface of the silicon wafer; forming a phosphorus diffusion layer and a PSG layer on the surface of the silicon wafer through diffusion; etching and cleaning: removing the PSG layer on the surface of the silicon wafer; etching and cleaning: forming a pyramid suede on the surface of the silicon wafer; forming an intrinsic amorphous silicon layer and an N-type amorphous silicon layer on one surface of a silicon wafer, and forming an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the other surface of the silicon wafer; depositing a transparent conductive film layer on the front surface and the back surface of the silicon wafer; and forming a metal grid line electrode on the front side and the back side of the silicon wafer. According to the invention, phosphorus diffusion and high-temperature oxidation treatment are carried out on the silicon wafer before texturing and cleaning, so that the defects of internal lattices of the silicon wafer are greatly improved, and impurities such as carbon, sulfur, metal and the like in the silicon wafer are reduced, thereby prolonging the bulk minority carrier lifetime of the silicon wafer, improving the interface passivation of the silicon wafer after amorphous silicon deposition, and further improving the conversion efficiency of a battery.

Description

Preparation method of silicon-based heterojunction solar cell
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a silicon-based heterojunction solar cell.
Background
The solar cell is a semiconductor device which can convert solar energy into electric energy, and photo-generated current is generated in the solar cell under the illumination condition, and the electric energy is output through an electrode. In recent years, solar cell production technology is continuously improved, production cost is continuously reduced, conversion efficiency is continuously improved, and photovoltaic power generation is increasingly widely applied and becomes an important energy source for power supply.
Silicon-based heterojunction cell is one of the current development directions of high-efficiency solar cells. As shown in fig. 1, a substrate of a silicon-based heterojunction cell generally adopts an N-type monocrystalline silicon wafer, a pyramid suede is formed on the surface of the silicon wafer through texturing and cleaning, then an intrinsic amorphous silicon layer and an N-type amorphous silicon layer are formed on one surface of the silicon wafer through a PECVD technique, an intrinsic amorphous silicon layer and a P-type amorphous silicon layer are formed on the other surface of the silicon wafer, then a transparent conductive film layer is sequentially deposited on the front surface and the back surface of the silicon wafer through a PVD technique, and finally a metal gate line electrode is formed through a screen printing or electroplating technique, wherein the whole preparation process is carried out at the temperature of less than 250 ℃.
However, the conventional single crystal or polycrystalline solar cell requires a diffusion and sintering high-temperature treatment process, and the preparation temperature is generally higher than 800 ℃, and a PSG layer is formed at the same time. The high-temperature treatment and the PSG layer are beneficial to improving the lattice defect of the silicon wafer, and can absorb carbon, sulfur, metal and other impurity elements in the silicon wafer body, so that the minority carrier lifetime of the silicon wafer body is greatly improved.
Disclosure of Invention
Aiming at the problems, the invention provides a preparation method of a silicon-based heterojunction solar cell, which combines the advantages of the conventional crystalline silicon cell production process and greatly improves the defects in a silicon wafer, so that the minority carrier lifetime of the passivated surface of the silicon wafer is prolonged, and the cell efficiency is improved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a method of fabricating a silicon-based heterojunction solar cell, the method comprising the steps of:
providing an N-type monocrystalline silicon wafer;
chemical polishing: treating a mechanical damage layer of the silicon wafer, and removing oil stains, metal particles and other impurities on the surface of the silicon wafer;
diffusion: forming a phosphorus diffusion layer and a PSG layer on the surface of the silicon wafer through diffusion;
etching and cleaning: removing the PSG layer on the surface of the silicon wafer;
etching and cleaning: removing a phosphorus diffusion layer, organic matters, metal impurities and the like on the surface of the silicon wafer, and forming a pyramid suede on the surface of the silicon wafer;
depositing an amorphous silicon layer: forming an intrinsic amorphous silicon layer and an N-type amorphous silicon layer on one surface of a silicon wafer, and forming an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the other surface of the silicon wafer;
depositing a transparent conductive film layer: depositing a transparent conductive film layer on the front surface and the back surface of the silicon wafer;
forming a metal grid line electrode: and forming a metal grid line electrode on the front side and the back side of the silicon wafer.
Further, the chemical polishing adopts alkali liquor polishing, the proportion of KOH to DI water is 1 (5-15), the temperature is 60-90 ℃, and the polishing time is 60-180S.
Further, the diffusion adopts a diffusion oxidation furnace to lead through POCL3The liquid diffusion source is used for thermal diffusion, the diffusion oxidation temperature is 600-900 ℃, and the diffusion oxidation time is 60-120M.
Further, the etching cleaning adopts acid liquor to etch and remove the PSG layer on the surface, and the acid liquor can adopt HF solution or HF and HNO3The corrosion temperature of the mixed solution is normal temperature, and the corrosion time is 2-10M.
Further, the texture etching cleaning is to perform RCA pre-cleaning, alkali texture etching, RCA cleaning and acid cleaning on the etched and cleaned monocrystalline silicon wafer, remove organic matters, metal impurities, phosphorus diffusion layers and the like on the surface of the silicon wafer, and form a pyramid texture surface, wherein the size of a pyramid is 2-12 um.
Furthermore, the amorphous silicon layer is deposited by adopting one of PECVD or Hot wire CVD, wherein the thickness of the intrinsic amorphous silicon thin film is 4-10nm, the thickness of the N-type amorphous silicon thin film is 4-10nm, and the thickness of the P-type amorphous silicon thin film is 4-10 nm.
Furthermore, the deposited transparent conductive film layer is at least one of an indium tin oxide film, an aluminum-doped zinc oxide film, a boron-doped zinc oxide film and a tungsten-doped indium oxide film, and the thickness of the transparent conductive film layer is 50-150 nm.
Further, the deposited transparent conductive thin film layer is formed by PVD or RPD technique.
Furthermore, the metal grid line electrode is formed by adopting a screen printing low-temperature silver paste or copper electroplating mode.
From the above description of the structure of the present invention, compared with the prior art, the present invention has the following advantages:
according to the invention, phosphorus diffusion and high-temperature oxidation treatment are carried out on the silicon wafer before texturing and cleaning, the advantages of a conventional crystalline silicon battery are combined, the defects of internal crystal lattices of the silicon wafer are greatly improved, and impurities such as carbon, sulfur, metal and the like in the silicon wafer are reduced, so that the bulk minority carrier lifetime of the silicon wafer is prolonged, the interface passivation of the silicon wafer after amorphous silicon deposition is improved, and the conversion efficiency of the battery is further improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a conventional silicon-based heterojunction solar cell fabrication method;
fig. 2 is a flow chart of a method for manufacturing a silicon-based heterojunction solar cell according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Examples
Referring to fig. 2, a method for fabricating a silicon-based heterojunction solar cell, the method comprising the steps of:
s1, providing an N-type monocrystalline silicon wafer;
s2, chemical polishing: polishing with alkali liquor at 80 deg.C for 60S, wherein the ratio of KOH to DI water is 1: 6. A polishing step for removing a mechanical damage layer of the silicon wafer and removing impurities such as oil stains, metal particles and the like on the surface of the silicon wafer;
s3, diffusion: POCL is introduced by adopting a diffusion oxidation furnace3Liquid state diffusion source thermal diffusion, the diffusion oxidation temperature is 800 ℃, the diffusion oxidation time is 60M, nitrogen and oxygen are introduced during diffusion, the introduction time is 500S, and oxygen is introduced during oxidationIntroducing gas for 600S, and forming a phosphorus diffusion layer and a PSG layer on the surface of the silicon wafer after diffusion;
s4, corrosion cleaning: removing the PSG layer on the surface of the silicon wafer by using 5% HF for 120S;
s5, texturing and cleaning: carrying out RCA pre-cleaning, alkali texturing, RCA cleaning and acid cleaning on the monocrystalline silicon wafer treated by the step S4, removing organic matters, metal impurities, phosphorus diffusion layers and the like on the surface of the silicon wafer, and forming a pyramid textured surface, wherein the size of a pyramid is 2-12 um;
s6, depositing an amorphous silicon layer: forming an intrinsic amorphous silicon layer and an N-type amorphous silicon layer on one surface of a silicon wafer and an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the other surface of the silicon wafer by a chemical vapor deposition PECVD (plasma enhanced chemical vapor deposition) technology, wherein the thickness of the intrinsic amorphous silicon thin film layer is 4-10nm, the thickness of the N-type amorphous silicon thin film layer is 4-10nm, and the thickness of the P-type amorphous silicon thin film layer is 4-10 nm;
s7, depositing a transparent conductive film layer: depositing an indium tin oxide transparent conductive film layer on the front surface and the back surface of the silicon wafer by a Physical Vapor Deposition (PVD) technology, wherein the thickness of the transparent conductive film layer is 80 nm;
s8, forming a metal grid line electrode: and forming metal grid line electrodes on the front side and the back side of the silicon wafer by a silver paste screen printing technology.
According to the manufacturing method, for example, in the conventional N-type single crystal heterojunction solar cell manufacturing method shown in FIG. 1, the minority carrier lifetime of the silicon wafer manufactured by the manufacturing method is prolonged by more than 20% after the amorphous silicon layer is deposited by PECVD, so that the cell conversion efficiency is improved.
According to the invention, phosphorus diffusion and high-temperature oxidation treatment are carried out on the silicon wafer before texturing and cleaning, the advantages of a conventional crystalline silicon battery are combined, the defects of internal crystal lattices of the silicon wafer are greatly improved, and impurities such as carbon, sulfur, metal and the like in the silicon wafer are reduced, so that the bulk minority carrier lifetime of the silicon wafer is prolonged, the interface passivation of the silicon wafer after amorphous silicon deposition is improved, and the conversion efficiency of the battery is further improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (9)

1. A preparation method of a silicon-based heterojunction solar cell is characterized by comprising the following steps: the method comprises the following steps:
providing an N-type monocrystalline silicon wafer;
chemical polishing: treating a mechanical damage layer of the silicon wafer, and removing oil stains, metal particles and other impurities on the surface of the silicon wafer;
diffusion: forming a phosphorus diffusion layer and a PSG layer on the surface of the silicon wafer through diffusion;
etching and cleaning: removing the PSG layer on the surface of the silicon wafer;
etching and cleaning: removing a phosphorus diffusion layer, organic matters, metal impurities and the like on the surface of the silicon wafer, and forming a pyramid suede on the surface of the silicon wafer;
depositing an amorphous silicon layer: forming an intrinsic amorphous silicon layer and an N-type amorphous silicon layer on one surface of a silicon wafer, and forming an intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the other surface of the silicon wafer;
depositing a transparent conductive film layer: depositing a transparent conductive film layer on the front surface and the back surface of the silicon wafer;
forming a metal grid line electrode: and forming a metal grid line electrode on the front side and the back side of the silicon wafer.
2. The method of claim 1, wherein the method comprises: the chemical polishing adopts alkali liquor polishing, the proportion of KOH to DI water is 1 (5-15), the temperature is 60-90 ℃, and the polishing time is 60-180S.
3. The method of claim 1, wherein the method comprises: the diffusion adopts a diffusion oxidation furnace-communicated POCL3The liquid diffusion source is used for thermal diffusion, the diffusion oxidation temperature is 600-900 ℃, and the diffusion oxidation time is 60-120M.
4. The method of claim 1, wherein the method comprises: the etching cleaning being carried out by etching the surface with an acidThe PSG layer may be HF solution or HF and HNO3The corrosion temperature of the mixed solution is normal temperature, and the corrosion time is 2-10M.
5. The method of claim 1, wherein the method comprises: the texture etching cleaning is to perform RCA pre-cleaning, alkali texture etching, RCA cleaning and acid cleaning processes on the etched and cleaned monocrystalline silicon wafer, remove organic matters, metal impurities, phosphorus diffusion layers and the like on the surface of the silicon wafer, and form a pyramid texture surface, wherein the size of a pyramid is 2-12 microns.
6. The method of claim 1, wherein the method comprises: the amorphous silicon layer is deposited by adopting one of PECVD or Hot wire CVD, wherein the thickness of the intrinsic amorphous silicon thin film layer is 4-10nm, the thickness of the N-type amorphous silicon thin film layer is 4-10nm, and the thickness of the P-type amorphous silicon thin film layer is 4-10 nm.
7. The method of claim 1, wherein the method comprises: the deposited transparent conductive film layer is at least one of indium tin oxide film, aluminum-doped zinc oxide film, boron-doped zinc oxide and tungsten-doped indium oxide, and the thickness of the transparent conductive film layer is 50-150 nm.
8. The method of claim 1, wherein the method comprises: the deposited transparent conductive thin film layer is formed by PVD or RPD techniques.
9. The method of claim 1, wherein the method comprises: the metal grid line electrode is formed by adopting a screen printing low-temperature silver paste or copper electroplating mode.
CN202011133338.6A 2020-10-21 2020-10-21 Preparation method of silicon-based heterojunction solar cell Withdrawn CN114388640A (en)

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Application publication date: 20220422