CN114374586B

CN114374586B - Data transmission method, transmitter and receiver

Info

Publication number: CN114374586B
Application number: CN202011097304.6A
Authority: CN
Inventors: 刘全红; 张翃敔; 陈天水; 吴英慧
Original assignee: Hebi Tianhai Electronic Information System Co Ltd
Current assignee: Hebi Tianhai Electronic Information System Co Ltd
Priority date: 2020-10-14
Filing date: 2020-10-14
Publication date: 2024-02-27
Anticipated expiration: 2040-10-14
Also published as: CN114374586A

Abstract

The application discloses a data transmission method, a transmitter and a receiver, wherein the method comprises the following steps: acquiring data to be transmitted; determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency and is used for mapping the corresponding bit value; generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals. By the method, inter-symbol interference can be avoided, and reliability of data transmission is improved.

Description

Data transmission method, transmitter and receiver

Technical Field

The present application belongs to the field of communications technologies, and in particular, to a data transmission method, a transmitter, and a receiver.

Background

Wireless digital communication is a communication scheme that is very popular for current applications. In wireless digital communication, information to be transmitted is digitally modulated to obtain symbols, which are then modulated onto a wireless channel for transmission. However, for wireless transmission, for example, short wave wireless transmission, multipath effects may exist, which may cause intersymbol interference (Inter Symbol Interference, ISI), i.e., interference of the same signal due to mutual overlapping of multipath propagation at the receiving end. For complex geographic environments, such as streets with dense high buildings, the phenomenon that normal communication cannot be performed is often caused due to the multipath effect.

Disclosure of Invention

The technical problem that this application mainly solves is to provide a data transmission method, transmitter and receiver, can avoid the intersymbol interference, improves data transmission's reliability.

In order to solve the technical problems, one technical scheme adopted by the application is as follows: there is provided a data transmission method including: acquiring data to be transmitted; determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency and is used for mapping the corresponding bit value; generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals.

In order to solve the technical problems, another technical scheme adopted by the application is as follows: there is provided a data transmission method including: receiving a plurality of frequency signals; determining the frequency of each frequency signal, and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; based on the mapping relation between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences to obtain the transmitted data.

In order to solve the technical problem, another technical scheme adopted by the application is as follows: there is provided a transmitter comprising: a frequency signal generating circuit for determining a corresponding frequency sequence for each bit value in the data to be transmitted; generating a corresponding at least one frequency signal for the frequency sequence; wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping corresponding bit values; and the transmitting circuit is used for sequentially transmitting the frequency signals.

In order to solve the technical problem, a further technical scheme adopted by the application is as follows: there is provided a receiver comprising: a receiving circuit for receiving a plurality of frequency signals; bit value generating circuit for determining frequency of each frequency signal and dividing the frequencies corresponding to the frequency signals into at least one group of frequency sequences; based on the mapping relation between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences to obtain the transmitted data.

The beneficial effects of this application are: different from the situation in the prior art, the method and the device for transmitting the data are characterized in that the data to be transmitted are obtained, the corresponding frequency sequence is determined for each bit value in the data to be transmitted, at least one corresponding frequency signal is generated for the frequency sequence, the frequency signals are sequentially transmitted, the corresponding bit values are transmitted by transmitting different frequency sequences, the transmission of information is realized due to the bit values, and in addition, the frequency sequence is utilized to replace symbols in digital communication in the transmission process, so that inter-symbol interference can be avoided, and the reliability of data transmission is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

Fig. 1 is a schematic flow chart of a first embodiment of a data transmission method of the present application;

fig. 2 is a schematic flow chart of a second embodiment of the data transmission method of the present application;

FIG. 3 is a flow chart of a third embodiment of a data transmission method of the present application;

fig. 4 is a schematic diagram of the structure of the synchronization time slot of the present application;

fig. 5 is a schematic diagram of a data slot structure of the present application;

fig. 6 is a flowchart of a fourth embodiment of a data transmission method of the present application;

fig. 7 is a schematic flow chart of a fifth embodiment of a data transmission method of the present application;

FIG. 8 is a schematic flow chart of step S53 in FIG. 7 of the present application;

FIG. 9 is a schematic diagram of the structure of three search windows of the present application;

FIG. 10 is a schematic diagram of the memory storage in the receiver of the present application;

fig. 11 is a schematic structural view of a first embodiment of the transmitter of the present application;

fig. 12 is a schematic structural view of a second embodiment of the transmitter of the present application;

fig. 13 is a schematic structural view of a first embodiment of the receiver of the present application;

fig. 14 is a schematic structural view of a second embodiment of the receiver of the present application;

fig. 15 is a schematic structural view of an embodiment of a device with a memory function of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not limiting. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The traditional short wave communication generally has a maximum communication distance of 30-50 km on the ground, and the communication distance is difficult to increase even if the transmission power is increased. However, the requirements on communication distance in the private network field, especially in the military field, are higher and higher, and at present, military communication has no good solution within the range of 50-100 km. The modulation mode used in the existing ultrashort wave long-distance digital communication is generally constant envelope modulation, and multipath effect is not considered in waveform design in order to achieve the cost and the spectral efficiency, so that the expansion of communication distance is restricted to a certain extent. If the communication distance is increased, multipath effect is increased, and thus intersymbol interference is increased.

However, the existing short-wave communication has a relatively wide application in the military field, but has problems, for example, the existing waveform design has very low jump speed, generally only tens of jumps per second in China, and is easy to be detected and interfered by enemy; second, short-wave channel delay spread is typically over 1ms, requiring a very complex channel equalization design, which increases cost and spectral efficiency.

The data transmission method can be applied to ultra-short wave communication, short wave communication or wireless digital communication of other waveforms.

Referring to fig. 1, fig. 1 is a flowchart of a first embodiment of a data transmission method of the present application.

The execution body of the embodiment may be a transmitter, and the transmitter is a transmitting end of a data transmission system. The main task of the transmitter (a transmitter circuit) is to accomplish the modulation of the high frequency carrier wave by the useful low frequency signal into an electromagnetic wave with a certain bandwidth at a certain center frequency, suitable for being transmitted through the antenna. The transmitter is widely applied to various civil and military equipment such as televisions, broadcasting, communication, alarming, radar, remote control, telemetry, electronic countermeasure and the like.

In this embodiment, the data transmission method includes:

Step S11: and acquiring data to be transmitted.

Wherein the data to be transmitted is formed by combining one or more bit values in a certain order. The transmitter may generate corresponding data to be transmitted according to the content to be transmitted. Specifically, after the content to be transmitted is subjected to source coding, one or more bit values can be obtained to be transmitted data which are formed by combining one or more bit values according to a certain sequence. Wherein the order of combination of the one or more bit values is determined by the content to be transmitted corresponding to the data to be transmitted. The content to be transmitted is not limited to sound, text, and images.

The bit values comprise the digits 0 and 1, and correspondingly, the data to be transmitted may be composed of one or more digits 0 or 1 in a certain order. For example, the data to be transmitted corresponding to the letter "R" of the content to be transmitted is 01010010, and the data to be transmitted includes 8 bit values.

Step S12: a corresponding frequency sequence is determined for each bit value in the data to be transmitted.

Wherein the frequency sequence comprises at least one frequency, the frequency sequence being used for mapping the corresponding bit values. The frequencies in the sequence of frequencies corresponding to different bit values are different and/or the ordering of the frequencies is different.

Specifically, the frequencies in the frequency sequences corresponding to the different bit values are different, or the ordering of the frequencies in the frequency sequences corresponding to the different bit values is different, or the frequencies in the frequency sequences corresponding to the different bit values are different and the ordering is different. Wherein the different frequencies in the frequency sequence may be different in size and/or different in number of frequencies in the frequency sequence. The different frequencies in the frequency sequence corresponding to the different bit values may be different in at least one frequency in the frequency sequence corresponding to the different bit values. For example, f1, f2, f3, f4, f5, f6, f7, f8 are eight different frequencies, respectively, the frequency sequence corresponding to the bit value 0 is { f1, f2, f3, f4}, the frequency sequence corresponding to the bit value 1 is { f5, f6, f7, f8}, wherein the frequencies in the frequency sequences corresponding to the bit values 0 and 1 are different in size; for another example, the frequency sequence corresponding to the bit value 0 is { f1, f2, f3, f4}, the frequency sequence corresponding to the bit value 1 is { f4, f3, f2, f1}, wherein the ordering of the frequencies in the frequency sequences corresponding to the bit values 0 and 1 is different; for another example, the frequency sequence corresponding to the bit value 0 is { f1, f2, f3, f4}, where f1< f2< f3< f4, i.e., the frequency in the frequency sequence increases sequentially, the frequency sequence corresponding to the bit value 1 is { f8, f7, f3}, where f8> f7> f3, i.e., the frequency in the frequency sequence decreases sequentially, where the ordering of the frequencies in the frequency sequences corresponding to the bit values 0 and 1 is different and the size and number of the frequencies are different.

Step S13: generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals.

The frequencies in the frequency sequence are digital signals, and the transmitter can convert the digital signals in the frequency sequence into corresponding frequency signals and sequentially transmit the frequency signals. Alternatively, the transmitter may convert digital signals in the frequency sequence to corresponding frequency signals via a local oscillator circuit.

In this embodiment, by acquiring data to be transmitted, determining a corresponding frequency sequence for each bit value in the data to be transmitted, generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals, the transmission of the corresponding bit values is achieved by transmitting different frequency sequences, so that the transmission of information is achieved by the bit values, and symbols in digital communication are replaced by the frequency sequences in the transmission process, so that inter-symbol interference can be avoided, and the reliability of data transmission is improved.

Referring to fig. 2, fig. 2 is a flowchart of a second embodiment of the data transmission method of the present application. The execution body of the embodiment may be a transmitter, and the transmitter is a transmitting end of a data transmission system. In this embodiment, the data transmission method includes:

Step S21: and acquiring data to be transmitted.

For the explanation of this step, reference may be made to the explanation of the corresponding position in the first embodiment of the data transmission method, which is not repeated here.

In this embodiment, steps S22 and S23 are a specific implementation manner of step S12 in the above embodiment.

Step S22: and determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value.

In this embodiment, the mapping relationship between the frequency sequence and the bit value may be the sum of the reference value, the bit value, and the repetition number of the step to perform pseudo-random variable conversion. Alternatively, the reference value tod_comm may be the frequency signal hop count TOD accumulated in the current system time, or a number of high bit values HTOD corresponding to the frequency signal hop count accumulated in the current system time. Specifically, the frequency signal hop count TOD accumulated in the current system time may be obtained by subtracting the reference time from the current system time to obtain an accumulated time value of the current system time from the reference time, and converting the accumulated time value into the number of frequency signal hop periods. The hop period is the number of hops per unit time. For example, the current system time T2 is 2020 month 4 No. 26:00, the reference time T1 is 2020 month 4 No. 25:23:59, and if the skip period T is 1000 hops/second, the reference value is:

TOD_COMM=TOD= (T2-T1) ×T=1s1000=1000, converted to binary

TOD＝1111101000，

Or the reference value TOD _ COMM takes the first 4 upper bits of 1111101000,

TOD_COMM＝HTOD＝1111。

specifically, step S22 may be to perform pseudo-random variable conversion on the sum of the reference value, the bit value, and the number of repetitions of the step to obtain a frequency index; and repeatedly executing the step until a first preset number of frequency indexes are obtained, and clearing the repeated times of the step. Wherein the first preset number of frequency indexes form a frequency index sequence. Optionally, the first preset number may be selected according to an actual situation, for example, may be selected according to a number of frequencies that may be currently available for communication, where the currently available frequencies may be frequencies with a communication quality greater than a preset threshold. In some embodiments, the first preset number may be equal to or less than the number of frequencies currently available for communication. In other embodiments, the first preset number may also be greater than the number of frequencies currently available for communication, where each of the frequencies may be selected only once, and when the first preset number is greater than the number of frequencies currently available for communication, frequencies other than the frequency available for communication, i.e., frequencies with a communication quality less than or equal to the preset threshold, may be included in the frequency sequence, but communication may still be enabled through the frequency, where the communication quality may not reach the preset threshold; another case is that each of the frequencies at which communication is possible may be selected repeatedly a plurality of times.

The specific calculation formula of the frequency index is as follows: frequency index = pseudo-random variable generation function (reference value + bit value + current number of runs of function), where the parameters of the function are reference value, bit value and current number of runs of function. The bit value may be 0 or 1, and the Pseudo-random variable generating function is not limited to PRG (Pseudo Random Generator) functions, pseudo-random binary sequence (PRBS) functions, RS-encoded (Reed-solomon codes) functions, such as Rsenc functions. Next, this embodiment will be described taking a PRG function as an example. The frequency index generation formula corresponding to the PRG function is:

n＝PRG(TOD_COMM+I+e)，

where TOD_COMM is a reference value, I is a bit value, e is the current number of operations of the function, and e is an integer value ranging from zero to a first preset number, for example, 0, 1,2, …, N.

For example, the first predetermined number is 3, the reference value tod_comm=1111101000, the bit value i=0,

when the function is run for the first time, e=1, then n ₁ ＝PRG(1111101000+0+1)＝1；

When the function runs a second time, e=2, then n ₂ ＝PRG(1111101000+0+2)＝2；

When the function runs a third time, e=3, then n ₃ PRG (1111101000+0+3) =3; 3 frequency indexes corresponding to the bit value 0 can be obtained, namely, the frequency index sequence is {1,2,3}, and then the running times of the function are cleared to prepare for calculating the frequency index corresponding to the next bit value.

Step S23: at least one frequency respectively associated with at least one frequency index is selected from a preset frequency set to compose a frequency sequence.

Wherein the set of preset frequencies includes a second preset number of frequencies. Typically, the second preset number is an integer power of 2. For example, the second preset number is L, then L may be 1,2, 4, 8, 16, etc. Generally, the second preset number is greater than or equal to the first preset number. In other embodiments, the second preset number is less than the first preset number. Optionally, the set of preset frequencies includes at least part of the communicable frequencies.

For example, the frequency index sequence is {1,2,3}, the preset frequency set is { f1, f2, f3, f4, f5, f6, f7, f8}, the frequency f1 associated with the frequency index 1, the frequency f2 associated with the frequency index 2, the frequency f3 associated with the frequency index 3 are selected from the preset frequency set, and the frequency sequence { f1, f2, f3}.

Step S24: and generating at least one corresponding frequency signal for the frequency sequence by utilizing the local oscillation circuit, and sequentially transmitting the frequency signals.

The local oscillator circuit in this embodiment may be a digital local oscillator circuit, or may be other local oscillator circuits, for example, a crystal oscillator circuit, etc.

In one embodiment, the digital local oscillator circuit may include a digitally controlled oscillator (numerically controlled oscillator, NCO) by which the frequency sequence may be generated into a corresponding at least one frequency signal and the frequency signals may be transmitted sequentially.

Referring to fig. 3 to 5, fig. 3 is a flowchart illustrating a third embodiment of a data transmission method according to the present application, fig. 4 is a schematic diagram illustrating a structure of a synchronization slot according to the present application, and fig. 5 is a schematic diagram illustrating a structure of a data slot according to the present application. The execution body of the embodiment may be a transmitter, and the transmitter is a transmitting end of a data transmission system. As shown in fig. 5, in the present embodiment, the data transmission method includes:

step S31: and acquiring data to be transmitted.

For the explanation of this step, reference may be made to the explanation of the corresponding position of the first embodiment of the data transmission method, which is not repeated here.

In this embodiment, the data to be transmitted includes a synchronization slot and/or a data slot. In particular, the data to be transmitted may comprise only synchronization slots, or only data slots, or both synchronization slots and data slots. The synchronization slots may be transmitted according to a synchronization transmission period. In some embodiments, the synchronization transmission period is a preset number of data slots at intervals, that is, one synchronization slot is transmitted after each preset number of data slots is transmitted, for example, when the preset number is 1, the synchronization slot is transmitted at intervals from the data slots, that is, 1 synchronization slot is transmitted before each data slot is transmitted; when the preset number is 2, then 2 data slots can be transmitted consecutively and then 1 synchronization slot can be transmitted, and so on. In other embodiments, the synchronization transmission period is in units of time, i.e., the synchronization slots are transmitted once at intervals, e.g., the synchronization transmission period may be transmitting one synchronization slot every second.

As shown in fig. 4, the synchronization slot may include an initial synchronization segment, a synchronization segment, and an information field in sequence. The synchronization slots are transmitted before the transmission of the data slots for achieving an initial access synchronization, synchronization of the slots, synchronization of transmission parameters and/or synchronization of low bit values of the first reference value, except for a number of high bit values. Specifically, the initial synchronization segment of the synchronization slot includes a frequency sequence repeated by a preset number of groups for achieving initial access synchronization, for example, the preset number may be 7. The synchronization segment of the synchronization slot comprises a set of frequency sequences for achieving synchronization of the slots. Wherein the initial synchronization segment is different from the frequency sequence in the synchronization segment. The information field of the synchronization slot is used for synchronizing the transmission parameter and/or the first reference value divided by a number of high bit values. The high bit values of the receiving end and the transmitting end can be guaranteed according to hardware or avoided in use, so that the high bit values can be generally not transmitted. For example, the year, month, and day of the receiving end and the transmitting end are generally the same. The information domain comprises a plurality of groups of frequency sequences, and the number of the frequency sequences is determined by the number of bit values in the data to be transmitted corresponding to the information domain. The transmission parameters are, for example, modulation scheme, coding scheme (e.g., coding rate, convolutional code), etc.

As shown in fig. 5, the data slot may include a data sync segment and a data segment in sequence. The data sync segment includes a predetermined number of repeated sets of frequency sequences, for example, the predetermined number may be 7. The frequency sequence in the data sync segment may be the same as or different from the initial sync segment, the frequency sequence in the sync segment. In this embodiment, by transmitting the synchronization segment before transmitting the data segment, the influence caused by clock drift or space delay can be avoided, and the access synchronization of the data is realized. For example, when the transmitting end and the receiving end are far apart, the propagation of the signal and the electric wave itself takes time, and when the aircraft is used in the aircraft, the distance of the aircraft changes at a moment in the flight. The data segment is used for transmitting data to be transmitted, which corresponds to the content to be transmitted by the user. Optionally, the transmitter may generate corresponding initial data to be transmitted according to the content to be transmitted, and perform channel coding on the initial data to be transmitted to obtain the data to be transmitted. In the channel coding process, the coding class can be selected according to the requirement of the data transmission system, and the coding class is not limited to convolutional codes and TURBO codes. In this embodiment, the channel coding is performed on the initial data to be transmitted, that is, redundancy is added to useful information in the initial data to be transmitted, for example, the initial data to be transmitted is 100 bit values, and the data to be transmitted obtained after the channel coding is 200 bit values, so that the reliability of data transmission can be improved, and the anti-interference capability can be increased.

The initial sync segment includes a plurality of sync preset bit values. The sync segment includes a sync preset bit value. The data sync segment includes a plurality of data preset bit values. The synchronization preset bit value and the data preset bit value are different bit values, for example, when the synchronization preset bit value is 1, the data preset bit value is 0; when the synchronization preset bit value is 0, the data preset bit value is 1, so that the frequency index sequence corresponding to the data synchronization section is different from the frequency index sequence corresponding to the initial synchronization section and the synchronization section, and therefore the frequency sequence in the data synchronization section is different from the frequency sequence in the initial synchronization section and the synchronization section, and further the receiving end can judge the initial synchronization section, the synchronization section and the data synchronization section according to the received frequency sequence.

Optionally, the data to be transmitted may also be grouped before step S32, each group comprising several bit values of the data to be transmitted. In this embodiment, each group includes the same number of bit values. In other embodiments, each group may include a different number of bit values. The basis for the packet may be the number of bit values per transmission. The counting mode of the data transmission system is not limited to binary, quaternary, decimal or hexadecimal. For example, when the current data to be transmitted is 200-bit value and the current system is binary in counting mode, only 1-bit value can be sent at a time, 200-bit values can be divided into 200 groups, and each group comprises 1-bit values; when the counting mode of the current system is quaternary, only 2-bit values can be sent at a time, 200-bit values can be divided into 100 groups, and each group comprises 2-bit values.

In this embodiment, steps S32 and S33 are a specific implementation manner of step S12 in the above embodiment.

Step S32: and determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value.

The description of this step may refer to the description of the corresponding positions in the above embodiments, which is not repeated here.

In the present embodiment, the reference value tod_comm is the frequency signal hop count accumulated in the current system time, i.e. the first reference value TOD, when generating the frequency sequence index corresponding to the data segment. When generating the initial synchronization segment, the synchronization segment, and the frequency sequence index corresponding to the information domain and the data synchronization segment in the synchronization time slot, the reference value tod_comm is a plurality of high bit values of TOD, that is, the second reference value HTOD.

When the data to be transmitted includes a data segment of the data slot, and the bit value is the bit value of the data segment, step S32 includes: performing pseudo-random variable conversion on the sum of the first reference value, the bit value and the repetition number of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and clearing the repeated times of the step. The mapping relation between the frequency sequence and the bit value in the data segment is to convert the pseudo-random variable by the sum of the first reference value, the bit value and the repetition number of the step. The first reference value is the frequency signal hop count accumulated by the current system time.

The present embodiment is exemplified by taking the PRG function as the pseudo random variable generating function.

The frequency index generation formula corresponding to the data segment of the data time slot is as follows:

n＝PRG(TOD+I+e)，

wherein TOD is a first reference value, I is a bit value in a data segment, e is the current running number of the function, and the value range of e is an integer value between zero and a preset number, such as 0, 1, 2, … and N.

When the data to be transmitted includes a data synchronization segment of the data slot, and/or the data to be transmitted further includes a synchronization slot, where the synchronization slot includes an initial synchronization segment and an information field, and the bit value is a bit value in the data synchronization segment, the initial synchronization segment, or the information field, step S32 includes: performing pseudo-random variable conversion on the second reference value, the bit value and the sum of the repetition times of the step to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and clearing the repeated times of the step. The mapping relation among the data synchronization section, the initial synchronization section and the frequency sequence and the bit value in the information domain is to convert the second reference value, the bit value and the sum of the repetition times of the step into pseudo-random variable. The second reference value is a value formed by a plurality of high-order bit values in the first reference value. In this embodiment, the number of low-order bit values in the first reference value may be determined by the size of the signal transmission delay, that is, the number of high-order bit values in the first reference value may be determined by the second reference value. Specifically, the second reference value:

HTOD＝TOD[MSB:E]，

Wherein MSB (Most Significant Bit) is the most significant bit; e is the number of bits taking the high bit value, E is equal to the transmission delay divided by the duration (i.e. the hop period) of each frequency emission in the frequency sequence, the obtained value is rounded up, the hop count corresponding to the transmission delay is obtained, then the hop count corresponding to the transmission delay is taken as the logarithm of 2, and the specific calculation formula is as follows:

E＝log ₂ [ceil(delay/Th)]，

where ceil is an upward rounding function, delay is a time Delay, th is a duration of each frequency transmission in the frequency sequence, and the duration of each frequency transmission in the frequency sequence may be the same and fixed.

Specifically, the frequency index generation formula corresponding to the data synchronization segment, the initial synchronization segment or the information domain is as follows:

n＝PRG(TODH+I+e)，

wherein, TODH is the second reference value, I is the bit value in the data synchronization segment, the initial synchronization segment or the information domain, e is the current running number of the function, and the value range of e is the integer value between zero and the preset number, such as 0, 1, 2, … and N. It should be noted that the preset bit values corresponding to the initial synchronization segment and the data synchronization segment are different, the initial synchronization segment is a synchronization preset bit value, and the data synchronization segment is a data preset bit value.

When the data to be transmitted further includes a synchronization slot, the synchronization slot includes a synchronization segment, and the bit value is the bit value of the synchronization segment, step S32 includes: performing pseudo-random variable conversion on the sum of the second reference value, the synchronous preset bit value, the preset parameter and the repetition number of the step to obtain a third frequency index; and repeatedly executing the step until a preset number of third frequency indexes are obtained, and clearing the repeated times of the step. The mapping relationship between the frequency sequence and the bit value in the synchronization segment is to perform pseudo-random variable conversion on the sum of the second reference value, the synchronization preset bit value, the preset parameter and the repetition number of the step. The preset value may be the total number of frequencies obtained by the initial synchronization segment, that is, the product of the repetition number of the frequency sequence in the initial synchronization segment and the continuous hop count of each bit value information in the initial synchronization segment.

Specifically, the frequency index generation formula corresponding to the synchronization segment in the synchronization time slot is:

n＝PRG(TODH+a+I+e)，

wherein, TODH is the second reference value, a is the preset parameter, I is the bit value in the synchronous section, e is the current running frequency of the function, and the value range of e is the integer value between zero and the preset number, such as 0, 1, 2, … and N.

Step S33: at least one frequency respectively associated with at least one frequency index is selected from a preset frequency set to compose a frequency sequence.

The description of this step may refer to the description of the corresponding positions of the above embodiments, which is not repeated here.

Step S34: and generating at least one corresponding frequency signal for the frequency sequence by utilizing the digital local oscillation circuit, and sequentially transmitting the frequency signals.

In one embodiment, as shown in fig. 4, the synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field. The initial synchronization segment comprises 7 groups of repeated frequency sequences S0, wherein each group of frequency sequences S0 corresponds to one synchronization preset bit value 0, and then the initial synchronization segment corresponds to 7 synchronization preset bit values 0. The synchronization segment comprises 1 group of frequency sequences SYNC, wherein the frequency sequences SYNC correspond to a synchronization preset bit value of 0. The information field includes several sets of frequency sequence SIGNALs. The frequency sequence SIGNAL is determined by the transmission parameters conveyed by the information field and/or the bit values of the first reference value, except for a number of high bit values. As shown in fig. 5, the data slot includes a data sync segment and a data segment. The data synchronization segment comprises 7 groups of repeated frequency sequences S1, wherein each group of frequency sequences S1 corresponds to one data preset bit value 1, and the initial synchronization segment corresponds to 7 data preset bit values 1. The DATA segment includes a plurality of sets of frequency sequences DATA, and the frequency sequences DATA are determined by DATA transmitted by the DATA segment.

Referring to fig. 6, fig. 6 is a flowchart of a fourth embodiment of the data transmission method of the present application. The execution body of the embodiment may be a receiver, which is a receiving end of the data transmission system.

The main function of the receiver is to select the frequency components needed by the receiver from a plurality of electromagnetic waves existing in the air, inhibit or filter the unwanted signals or noise and interference signals, and then amplify and demodulate the signals to obtain the original useful information.

In this embodiment, the data transmission method includes:

step S41: a plurality of frequency signals is received.

Wherein the frequency signal may be an electromagnetic wave signal. The receiver may receive a plurality of frequency signals sequentially through one receiving circuit, or the receiver may receive a plurality of frequency signals in parallel using a plurality of receiving circuits.

Step S42: the frequency of each frequency signal is determined, and a plurality of frequencies corresponding to the plurality of frequency signals are divided into at least one set of frequency sequences.

Alternatively, the receiver may determine the frequency of each of the plurality of frequencies, respectively, and store the determined frequencies at corresponding positions of the frequency sequences, so that the receiver may divide the plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences according to a preset number.

Step S43: based on the mapping relation between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences to obtain the transmitted data.

The receiver can acquire a mapping relation between the frequency sequences and the bit values, and generate corresponding bit values for each group of frequency sequences according to the mapping relation between the frequency sequences and the bit values so as to obtain transmitted data.

Alternatively, the mapping relationship between the frequency sequence and the bit value may be pre-stored in the receiver or the server, the receiver may obtain the mapping relationship between the frequency sequence and the bit value locally, or may be connected to the server, and obtain the mapping relationship between the frequency sequence and the bit value from the server, or the receiver may obtain the mapping relationship between the frequency sequence and the bit value from a plurality of received frequency signals.

In this embodiment, the plurality of frequencies corresponding to the plurality of received frequency signals are divided into at least one group of frequency sequences, and based on the mapping relationship between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences, so as to obtain the transmitted data, and the corresponding bit values can be mapped through the frequency sequences, so that the data transmission is realized, no symbol in digital communication is provided, the inter-symbol interference can be avoided, and the reliability of the data transmission is improved.

Referring to fig. 7 to 10, fig. 7 is a flowchart of a fifth embodiment of the data transmission method of the present application, fig. 8 is a flowchart of step S53 of fig. 7 of the present application, fig. 9 is a schematic diagram of the structure of three search windows of the present application, and fig. 10 is a schematic diagram of the memory of the receiver of the present application. The execution body of the embodiment may be a receiver, which is a receiving end of the data transmission system. In this embodiment, the data transmission method includes:

step S51: a plurality of frequency signals is received.

The description of this step may be that of the corresponding position in the above embodiment, which is not repeated here.

In this embodiment, the plurality of frequency signals may be frequency signals in a data slot and/or frequency signals in a synchronization slot. The synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field. The initial synchronization segment includes a plurality of synchronization preset bit values for initial access synchronization. The sync segment includes a sync preset bit value for slot synchronization. The information field comprises a number of bit values associated with the transmission parameter and/or the first reference value divided by the number of high bit values for enabling synchronization of the transmission parameter and/or the first reference value divided by the number of high bit values. The data slot includes a data sync segment and a data segment. The data synchronization section includes a plurality of data preset bit values for data access synchronization. The data segment comprises a plurality of bit values in data to be transmitted, which correspond to the content to be transmitted, and is used for transmitting the data. Generally, a receiver receives a synchronization slot first to achieve synchronization of initial synchronization, slot synchronization, transmission parameters and/or a first reference value divided by a plurality of high bit values, and then receives a data slot to achieve access synchronization of data and transmission of data. In this embodiment, the description of the data slots and the synchronization slots may refer to the description of the corresponding positions in the above embodiment, which is not repeated here.

Steps S52-S53 are a specific implementation of step S42 in the above embodiment.

Step S52: the frequency of each frequency signal is determined.

Specifically, each frequency signal is input in parallel to a preset number of frequency detection circuits to determine the frequency of the frequency signal. Wherein each frequency detection circuit is configured to detect a frequency.

The frequency detection circuit may include a second mixer, a digital down-converter, a correlator, and a memory. The second mixer is used for mixing the frequency signal with a first reference frequency signal generated by the digital local oscillation circuit to obtain a mixed signal. The mixed signal obtained after the mixing of the second mixer filters out the carrier signal in the frequency signal. The digital down converter is used for down-converting the mixed signal to obtain a down-converted signal. The correlator is used for performing correlation operation on the down-conversion signal to obtain a correlation result between the frequency signal and the reference frequency signal. The correlation operation is, for example, a convolution operation. The memory is used for determining the storage position of the correlation result of the frequency signals according to the receiving order of the frequency signals, and storing the correlation result according to the storage position, so that the correlation result sequences obtained by combining the correlation results stored by different memories according to the storage positions are consistent with the receiving order of the corresponding frequency signals. The memory may store the correlation results in parallel with a delay of a preset number of hops, where the preset number is equal to a preset number in a frequency sequence of a preset number of frequencies transmitted by the transmitting end, so that the receiving end can perform multi-hop joint detection with a previously stored frequency when receiving a last frequency in the frequency sequence transmitted by the transmitting end.

In a specific embodiment, as shown in fig. 10, the frequency sequence sent by the sending end includes 7 frequencies { f7, f6, f5, f4, f3, f2, f1}, and the receiving end sequentially receives the frequencies f7, f6, f5, f4, f3, f2, f1. And similarly, when the receiving end receives the frequencies f6, f5, f4, f3 and f2, the corresponding correlation results are stored for 7 hops, so that when the receiving end receives the last frequency f1 in the frequency sequence sent by the sending end, the frequency f1 and the previously stored frequencies f7, f6, f5, f4, f3 and f2 can be checked together, namely multi-hop joint detection. The memory can store L paths in parallel, wherein L is the number of frequencies in a preset frequency set.

Optionally, the transmitter further includes passing the plurality of frequency signals through a band-pass filter, a first mixer, a low-pass filter and an analog-to-digital conversion circuit in sequence after receiving the plurality of frequency signals, and then inputting each frequency signal into a preset number of frequency detection circuits in parallel. The band-pass filter is used for passing frequency signals of a specific frequency band and shielding frequency signals of other frequency bands. The first mixer is used for mixing the received frequency signal with a local oscillation signal with the same frequency. The first mixer is used for removing carriers in the frequency signal. The low pass filter may remove high frequency portions of the frequency signal, leaving useful low frequency portions of the frequency signal. Analog-to-digital conversion circuitry may convert analog signals to digital signals.

Step S53: the plurality of frequencies corresponding to the plurality of frequency signals are divided into at least one set of frequency sequences.

In one case, for example, when the received plurality of frequency signals are frequency signals in a synchronization section, an information field, or a data section, after determining the frequency of each frequency signal, the plurality of frequencies may be directly divided into at least one set of frequency sequences. In another case, for example, when the received plurality of frequency signals are the plurality of frequency signals in the initial synchronization segment or the data synchronization segment, after determining the frequency of each frequency signal, it is necessary to determine the current frequency sequence corresponding to the preset bit value by determining a plurality of different sets of first reference frequency sequences corresponding to the preset bit value for synchronization, and dividing the plurality of frequencies into different sets of frequency sequences according to the first reference frequency sequences. Step S531: and determining a plurality of groups of different first reference frequency sequences corresponding to the preset bit values for synchronization based on the mapping relation between the frequency sequences and the bit values.

Specifically, at least one adjacent reference value, which is different from the current second reference value within a preset variation range, is obtained, different mapping relations are obtained by using the current second reference value and each adjacent reference value, and different first reference frequency sequences corresponding to the preset bit values are respectively determined according to the different mapping relations.

The second reference value is a plurality of high bit values corresponding to the frequency signal hops accumulated by the current system time of the receiver. When the time difference between the frequency signal transmitting end and the receiving end is within the allowable range, the difference between the second reference values at the two ends is only three possibilities of-1, 0 and +1, and as the second reference values can be selected according to the time delay of the system, the values of the second reference values can be controlled, so that the difference between the second reference values at the two ends is only three possibilities of-1, 0 and +1, and different mapping relations can be obtained by using the current second reference value and at least one adjacent reference value which is different from the current second reference value within the preset variation range, and different first reference frequency sequences corresponding to the preset bit values can be respectively determined according to the different mapping relations.

For example, the current second reference value of the transmitting end is 99, the frequency sequence corresponding to the preset bit value generated by the transmitting end according to the current second reference value is { f1, f2, f3}, the current second reference value of the receiving end is 100, the frequency sequence corresponding to the preset bit value generated by the receiving end according to the current second reference value is { f2, f3, f1}, and the frequency sequence { f2, f3, f1} is used as the first reference frequency sequence. If the transmitting end transmits only one group of frequency sequences { f1, f2, f3}, the receiving end cannot successfully identify the frequency signal transmitted by the transmitting end according to the current first reference frequency sequence { f2, f3, f1}, if the transmitting end transmits multiple groups of repeated frequency sequences { f1, f2, f3}, the receiving end can identify the frequency signal transmitted by the transmitting end according to the current first reference frequency sequence { f2, f3, f1}, but cannot identify the frequency sequence actually transmitted by the transmitting end as { f1, f2, f3}, so the receiving end still takes the second reference value 100 corresponding to the current first reference frequency sequence as the current second reference value of the transmitting end, and obviously the current second reference value of the transmitting end is 99, and the receiving end does not realize the synchronization of the second reference value. In this embodiment, in order to achieve synchronization of the second reference values of the receiving end and the transmitting end, the receiving end and the transmitting end may select the second reference values according to the system delay, so that the difference between the second reference values of the two ends of the receiving end and the transmitting end is only-1, 0, +1, the current second reference value of the receiving end is 100, and the adjacent reference values 99 and 101 thereof are correspondingly selected, so that different mapping relations are obtained by using the current second reference value 100 of the receiving end and the adjacent reference values 99 and 101, and different first reference frequency sequences corresponding to the preset bit values are respectively determined according to the different mapping relations. The first reference frequency sequence corresponding to the second reference value 100 is { f2, f3, f1}, the first reference frequency sequence corresponding to the second reference value 99 is { f1, f2, f3}, and the first reference frequency sequence corresponding to the second reference value 101 is { f3, f1, f2}. Alternatively, the receiving end may take an adjacent reference value, for example 99, which is different from the current second reference value by a predetermined range.

In some embodiments, the plurality of frequency signals are a plurality of frequency signals in a synchronization time slot, the synchronization time slot includes a synchronization preset bit value in an initial synchronization segment, and then a plurality of groups of different first reference frequency sequences corresponding to the synchronization preset bit value are determined based on a third mapping relationship between the frequency sequences and the bit value of the initial synchronization segment. The third mapping relation between the frequency sequence and the bit value of the initial synchronization section is to perform pseudo-random variable conversion on the second reference value or the adjacent reference value, the synchronization preset bit value and the sum of the repetition times of the step to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and clearing the repeated times of the step. Reference may be made specifically to the description of the corresponding positions in the above embodiments, and details are not repeated here.

For example, if the current second reference value of the receiving end is 100 and the adjacent reference values are 99 and 101, the generating formula n=prg (todh+i+e) according to the frequency index may be obtained: when the synchronous preset bit value I=1 and the TODH is the current second reference value 100 of the receiving end, the obtained frequency index sequence is {2,3,1}, and the corresponding frequency sequence is { f2, f3, f1}; when the synchronous preset bit value I=1 and the TODH is the adjacent reference value 99, the obtained frequency index sequence is {2,1,3}, and the corresponding frequency sequence is { f2, f1, f3}; when the synchronization preset bit value i=1 and the todh is the adjacent reference value 101, the obtained frequency index sequence is {3,2,1}, and the corresponding frequency sequence is { f3, f2, f1}.

In other embodiments, the plurality of frequency signals are a plurality of frequency signals within a data slot, the data slot includes a data preset bit value in a data synchronization segment, and a plurality of sets of different second reference frequency sequences corresponding to the data preset bit value are determined based on a first mapping relationship between the frequency sequences and the bit value of the data synchronization segment. The first mapping relation between the frequency sequence and the bit value of the data synchronization section is to perform pseudo-random variable conversion on the second reference value or the adjacent reference value, the preset bit value of the data and the sum of the repetition times of the step to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and clearing the repeated times of the step. Reference may be made specifically to the description of the corresponding positions in the above embodiments, and details are not repeated here. It should be noted that, the second reference value is updated by the receiving end after receiving the synchronization time slot, and the second reference values in the receiving end and the transmitting end may still be inconsistent when the receiving end receives the data time slot due to the influence of clock drift or space delay and other factors, so that the embodiment can realize the access synchronization of the data by adding the data synchronization section before the data section.

For example, if the second reference value updated by the receiving end after receiving the synchronization timeslot is 99 and the adjacent reference values are 98 and 100, the generating formula n=prg (todh+i+e) according to the frequency index may be obtained: when the preset bit value of the data is i=0 and the todh is the current second reference value 98 of the receiving end, the obtained frequency index sequence is {5,4,6}, and the corresponding second reference frequency sequence is { f5, f4, f6}; when the synchronous preset bit value I=0 and the TODH is the adjacent reference value 99, the obtained frequency index sequence is {4,5,6}, and the corresponding second reference frequency sequence is { f4, f5, f6}; when the synchronization preset bit value i=0 and the todh is the adjacent reference value 100, the obtained frequency index sequence is {6,5,4}, and the corresponding second reference frequency sequence is { f6, f5, f4}.

Step S532: and respectively comparing each group of first reference frequency sequences with a plurality of frequencies, counting the times of continuously appearing corresponding first reference frequency sequences in the plurality of frequencies, and taking the first frequency reference sequence with the largest times as the current frequency sequence corresponding to the preset bit value.

In one embodiment, as shown in fig. 9, the plurality of frequencies received by the receiver are f1, f2, f3; f1, f2, f3; f1, f2, f3; f1, f2, f3; f1, f2, f3; f1, f2, f3; f1, f2, f3, the plurality of frequencies being a 7-set repeating sequence of frequencies S1{ f1, f2, f3} in the data sync segment. The receiver searches using three search windows, respectively. The first reference frequency sequence corresponding to the second reference value 100 is { f2, f3, f1}, i.e. a first search window WIN0; the first reference frequency sequence corresponding to the second reference value 99 is { f1, f2, f3}, i.e. the second search window WIN-1; the first reference frequency sequence corresponding to the second reference value 101 is { f3, f1, f2}, that is, the third search window win+1, and the three sets of first reference frequency sequences are compared with a plurality of frequencies respectively, wherein 6 times corresponding to { f2, f3, f1} continuously occur in the plurality of frequencies, 7 times corresponding to { f1, f2, f3} and 6 times corresponding to { f3, f1, f2 }. And taking the first frequency reference sequence { f1, f2, f3} with the largest frequency as the current frequency sequence corresponding to the preset bit value.

In the above embodiment, the plurality of frequencies are compared with the first reference frequency sequence, that is, the frequencies are compared with the frequencies, and in other embodiments, the plurality of frequencies may be converted into the corresponding frequency indexes and then compared with the frequency indexes corresponding to the first reference frequency sequence.

Step S533: the frequencies remaining after the current frequency sequence continuously appears among the plurality of frequencies are divided into at least one set of frequency sequences.

After dividing a plurality of frequencies corresponding to a plurality of frequency signals in an initial synchronization section in a synchronization time slot into at least one group of frequency sequences, continuing the frequencies remaining after the current frequency sequence, namely the frequencies in the synchronization section, into at least one group of frequency sequences. Specifically, a group of second reference frequency sequences corresponding to the synchronous preset bit values are determined based on a fourth mapping relation between the frequency sequences and the bit values of the synchronous segment; the method comprises the steps of obtaining the residual frequencies after the current frequency sequence continuously appears in the plurality of frequencies, and dividing the frequencies positioned behind a first reference frequency sequence in the residual frequencies into at least one group of frequency sequences. The fourth mapping relation between the frequency sequence and the bit value of the synchronous section is to perform pseudo-random variable conversion on the sum of the second reference value, the synchronous preset bit value, the preset parameter and the repetition number of the step to obtain a third frequency index; and repeatedly executing the step until a preset number of third frequency indexes are obtained, and clearing the repeated times of the step. Reference may be made specifically to the description of the corresponding positions in the above embodiments, and details are not repeated here.

Optionally, before step S533, the method further includes selecting, from the current second reference value and each adjacent reference value, a reference value corresponding to the current frequency sequence as the latest second reference value, so as to achieve synchronization of the second reference values of the receiving end and the transmitting end. Specifically, the reference value corresponding to the current frequency sequence may be selected from the initial synchronization segment as the latest second reference value for calculating the relevant second reference value in the synchronization segment, the information field and the data synchronization segment, and the reference value corresponding to the current frequency sequence may be selected from the data synchronization segment as the latest second reference value for calculating the relevant second reference value in the data segment.

Step S54: based on the mapping relation between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences to obtain the transmitted data.

When the plurality of frequency signals are a plurality of frequency signals in the synchronous time slot, corresponding bit values are generated for each group of frequency sequences based on a fifth mapping relation between the frequency sequences and the bit values of the information domain, so that information of the information domain in the synchronous time slot is obtained. The fifth mapping relation is to perform pseudo-random variable conversion according to the frequency index corresponding to the frequency in the received frequency sequence, the second reference value and the sum of the repetition times of the step, so as to obtain a corresponding bit value. For example, the received frequency index { f1, f2, f3} is {1,2,3}, the updated second reference value is 99, and the sum of the repetition times of the step is converted into a pseudo-random variable, so as to obtain the bit value 1 corresponding to the frequency index { f1, f2, f3 }.

Optionally, after obtaining the information of the information field in the synchronization time slot, further includes: acquiring a low-order bit value in a first reference value from an information domain; and updating the current second reference value and the low bit value to obtain the latest first reference value so as to realize the synchronization of the first reference values of the receiving end and the transmitting end.

When the plurality of frequency signals are a plurality of frequency signals in the data time slot, corresponding bit values are generated for each group of frequency sequences based on a second mapping relation between the frequency sequences and the bit values of the data segments, so that information of the data segments in the data time slot is obtained. The second mapping relation is to perform pseudo-random variable conversion according to the frequency index corresponding to the frequency in the received frequency sequence, the first reference value and the sum of the repetition times of the step, so as to obtain a corresponding bit value. In this embodiment, the operation of generating the corresponding bit value according to each set of frequency sequences and the operation of generating each set of frequency sequences according to the bit values in the above embodiment are inverse operations, and specific reference may be made to the description of the corresponding positions in the above embodiment, which is not repeated here.

In this embodiment, the second mapping relationship is related to the current first reference value, and the first mapping relationship, the third mapping relationship, the fourth mapping relationship, and the fifth mapping relationship are related to the current second reference value. The second reference value is a value formed by a plurality of high-order bit values in the first reference value.

Referring to fig. 11, fig. 11 is a schematic structural diagram of a first embodiment of a transmitter of the present application.

The transmitter includes a frequency signal generating circuit 11 and a transmitting circuit 12. The frequency signal generating circuit 11 is configured to determine a corresponding frequency sequence for each bit value in the data to be transmitted, and generate at least one corresponding frequency signal for the frequency sequence. The frequency sequence comprises at least one frequency, the frequency sequence being used to map corresponding bit values. The transmitting circuit 12 is used for sequentially transmitting the frequency signals.

In this embodiment, the description of the frequency signal generating circuit 11 and the transmitting circuit 12 can be referred to the description of the corresponding positions in the above embodiment, and the description is omitted here.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a second embodiment of the transmitter of the present application.

The transmitter includes a frequency signal generating circuit 21 and a transmitting circuit 22, unlike the above-described embodiment, the transmitter further includes a digital-to-analog conversion circuit 23, an up-converter 24, a band-pass filter bank 25, a mixer 26, and a low-pass filter 27. The digital-to-analog conversion circuit 23, the up-converter 24, the band-pass filter bank 25, the mixer 26, and the low-pass filter 27 are sequentially connected between the frequency signal generating circuit 21 and the transmitting circuit.

The frequency signal generating circuit 21 is configured to determine a corresponding frequency sequence for each bit value in the data to be transmitted, and generate at least one corresponding frequency signal for the frequency sequence. The sequence of frequencies includes at least one frequency. The frequency sequence is used to map the corresponding bit values. Wherein the frequencies in the frequency sequence corresponding to the different bit values are different and/or the ordering of the frequencies is different.

The frequency signal generating circuit 21 further includes a pseudo random sequence generator 211 and a digital local oscillation circuit 212. The pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion based on the bit value, so as to obtain at least one frequency index in the frequency sequence corresponding to the bit value.

When the data to be transmitted includes a data segment of the data slot and the bit value is the bit value of the data segment, the pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion on the first reference value, the bit value, and the sum of the repetition times of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and clearing the repeated times of the step.

When the data to be transmitted includes a data synchronization segment of the data slot, and/or the data to be transmitted further includes a synchronization slot, where the synchronization slot includes an initial synchronization segment and an information field, and the bit value is a bit value in the data synchronization segment, the initial synchronization segment or the information field, the pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion on the second reference value, the bit value, and the sum of the repetition times of the step to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and clearing the repeated times of the step.

When the data to be transmitted further includes a synchronization time slot, the synchronization time slot includes a synchronization segment, and the bit value is the bit value of the synchronization segment, the pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion on the second reference value, the synchronization preset bit value, the preset parameter, and the sum of the repetition times of the step to obtain a third frequency index; and repeatedly executing the step until a preset number of third frequency indexes are obtained, and clearing the repeated times of the step.

The second reference value is a value formed by a plurality of high-order bit values in the first reference value. The information field comprises a transmission parameter and/or a low order bit value of the first reference value, other than the number of high order bit values. The data synchronization section comprises a plurality of data preset bit values, the initial synchronization section comprises a plurality of synchronization preset bit values, and the synchronization section comprises a synchronization preset bit value, wherein the synchronization preset bit value and the data preset bit value are different bit values.

The digital local oscillation circuit 212 is configured to select at least one frequency respectively associated with at least one frequency index from a preset frequency set to form a frequency sequence, and generate at least one corresponding frequency signal for the frequency sequence.

The digital-to-analog conversion circuit 23 is used to convert digital signals into analog signals. Up-converter 24 is used to convert an input signal having a frequency into an output signal having a higher frequency. The band-pass filter is used for passing frequency signals of a specific frequency band and shielding frequency signals of other frequency bands. The mixer 26 is configured to mix each frequency signal output by the band-pass filter bank 25 with a local oscillation signal, where the frequency of the local oscillation signal mixed with each frequency signal is the same. The low pass filter 27 may remove high frequency portions of the frequency signal, leaving useful low frequency portions of the frequency signal. The transmitting circuit 22 is used for sequentially transmitting the frequency signals.

For a specific explanation of some circuit elements in this embodiment, such as the frequency signal generating circuit and the transmitting circuit, please refer to the explanation of the corresponding steps in the method embodiment of the transmitter, and the detailed description is omitted here.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a first embodiment of a receiver according to the present application.

The receiver comprises a receiving circuit 31 and a bit value generating circuit 32. The receiving circuit 31 is configured to receive a plurality of frequency signals. The bit value generating circuit 32 is configured to determine a frequency of each frequency signal and divide a plurality of frequencies corresponding to the plurality of frequency signals into at least one set of frequency sequences; based on the mapping relation between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences to obtain the transmitted data.

In this embodiment, the descriptions of the receiving circuit and the bit value generating circuit may be referred to the descriptions of the corresponding positions in the above embodiments, and will not be repeated here.

Referring to fig. 14, fig. 14 is a schematic structural diagram of a second embodiment of the receiver of the present application.

The receiver includes a receiving circuit 41 and a bit value generating circuit 42, and unlike the first embodiment of the receiver, the receiver in this embodiment further includes a band pass filter 43, a first mixer 44, a low pass filter 45, an analog-to-digital conversion circuit 46, and a digital local oscillation circuit 47.

The band-pass filter 43, the first mixer 44, the low-pass filter 45, and the analog-to-digital conversion circuit 46 are connected in order between the receiving circuit 41 and the bit value generating circuit 42. The band-pass filter 43 is used to pass frequency signals of a specific frequency band while masking frequency signals of other frequency bands. The first mixer 44 is configured to mix the received frequency signal with a local oscillator signal of the same frequency. The first mixer 44 is used to remove the carrier wave from the frequency signal. The low pass filter 45 may remove high frequency portions of the frequency signal, leaving useful low frequency portions of the frequency signal. Analog-to-digital conversion circuit 46 may convert the analog signal to a digital signal, wherein the sampling frequency of analog-to-digital conversion circuit 46 is greater than twice the maximum offset frequency.

The bit value generation circuit 42 includes a preset number of frequency detection circuits 421 and a logic processing and decoding circuit 422. Wherein each frequency detection circuit 421 is configured to detect a frequency. The frequency detection circuit 421 includes a second mixer 4211, a digital down converter 4212, a correlator 4213, and a memory 4214. The second mixer 4211 is configured to mix the frequency signal with the first reference frequency signal generated by the digital local oscillation circuit 47 to obtain a mixed signal. The digital down converter 4212 is used for down-converting the mixed signal to obtain a down-converted signal. The correlator 4213 is configured to perform a correlation operation on the down-converted signal to obtain a correlation result between the frequency signal and the reference frequency signal. The memory 4214 is configured to determine a storage location of the correlation results of the frequency signals according to the receiving order of the frequency signals, and store the correlation results according to the storage location, so that a correlation result sequence obtained by combining the correlation results stored in the different memories 4214 according to the storage locations thereof is consistent with the receiving order of the corresponding frequency signals. The logic processing and decoding circuit 422 is configured to divide a plurality of frequencies corresponding to the plurality of frequency signals into at least one set of frequency sequences; based on the mapping relation between the frequency sequences and the bit values, corresponding bit values are generated for each group of frequency sequences to obtain the transmitted data.

Wherein the receiver inputs each frequency signal in parallel to a preset number (e.g., L) of frequency detection circuits 421 to determine the frequency of the frequency signal.

The logic processing and decoding circuit 422 is configured to determine a plurality of different sets of first reference frequency sequences corresponding to preset bit values for synchronization based on a mapping relationship between the frequency sequences and the bit values; comparing each group of first reference frequency sequences with a plurality of frequencies respectively to count the times of continuously appearing corresponding first reference frequency sequences in the plurality of frequencies; and taking the first frequency reference sequence with the largest frequency as a current frequency sequence corresponding to the reference bit value, and dividing the frequency remained after the current frequency sequence continuously appears in the plurality of frequencies into at least one group of frequency sequences.

When the plurality of frequency signals are a plurality of frequency signals in a data slot, wherein the data slot includes a data synchronization segment and a data segment, the data synchronization segment includes a plurality of data preset bit values for data access synchronization, the logic processing and decoding circuit 422 is configured to determine a plurality of different sets of first reference frequency sequences corresponding to the data preset bit values based on a first mapping relationship between the frequency sequences and the bit values of the data synchronization segment. The logic processing and decoding circuit 422 is further configured to generate a corresponding bit value for each set of frequency sequences based on a second mapping relationship between the frequency sequences and the bit values of the data segments, so as to obtain information of the data segments in the data slots.

When the plurality of frequency signals are a plurality of frequency signals in a synchronization time slot, wherein the synchronization time slot includes an initial synchronization segment, a synchronization segment and an information field, the initial synchronization segment includes a plurality of synchronization preset bit values for initial access synchronization, and the synchronization segment includes one synchronization preset bit value for time slot synchronization, the logic processing and decoding circuit 422 is configured to determine a plurality of different sets of first reference frequency sequences corresponding to the synchronization preset bit values based on a third mapping relationship between the frequency sequences and the bit values of the initial synchronization segment. The logic processing and decoding circuit 422 is further configured to determine a set of second reference frequency sequences corresponding to the synchronization preset bit values based on a fourth mapping relationship between the frequency sequences and the bit values of the synchronization segment; the method comprises the steps of obtaining the residual frequencies after the current frequency sequence continuously appears in the plurality of frequencies, and dividing the frequencies positioned behind a first reference frequency sequence in the residual frequencies into at least one group of frequency sequences. The logic processing and decoding circuit 422 is further configured to generate a corresponding bit value for each set of frequency sequences based on a fifth mapping relationship between the frequency sequences and the bit values of the information domain, so as to obtain information of the information domain in the synchronous timeslot. After the information of the information field is obtained, the logic processing and decoding circuit 422 is further configured to obtain the low-order bit value in the first reference value from the information field, and update the latest first reference value by using the current second reference value and the low-order bit value.

Wherein the second mapping relationship is related to the current first reference value, and the first mapping relationship, the third mapping relationship, the fourth mapping relationship and the fifth mapping relationship are related to the current second reference value; the second reference value is a value formed by a plurality of high-order bit values in the first reference value. The logic processing and decoding circuit 422 is configured to obtain at least one adjacent reference value differing from the current second reference value by a predetermined variation range, obtain different mapping relationships by using the current second reference value and each adjacent reference value, and determine different first reference frequency sequences corresponding to the reference bit values according to the different mapping relationships. And the logic processing and decoding circuit 422 is further configured to select, from the current second reference value and each neighboring reference value, the reference value corresponding to the current frequency sequence as the latest second reference value.

For a specific explanation of some circuit elements in this embodiment, such as the receiving circuit and the bit value generating circuit, please refer to the above explanation of the corresponding steps in the method embodiment of the receiver, and the detailed description is omitted here.

In one example application, a very high frequency communication system (VHF COMM) product of a certain model is described as an example: the working frequency band of the product is as follows: 30 MHz-88 MHz; jump speed: fh=32000 Hop/s; frequency step: 25KHz; number of frequencies: n=256; frequency sequence length: l=16; baseband sampling rate fs= (88M-30M)/2 x osr=116 Msps (osr=4). Since the time t=l/fh=16/32000 s=500 us=5×10 required for transmitting the frequency sequence ^-4 s, so that the time t can be multiplied by the speed of light C to obtain the frequency sequence at t×c=5×10 ^-4 s*3×10 ⁵ km/s=150 km. The multipath signals within 150km can be filtered out, which is beneficial to expanding the communication distance and has relatively stronger adaptability in complex terrain environments.

The application also provides an embodiment of the data transmission device. Specifically, the data transmission device comprises an acquisition module, a determination module and a sending module. The acquisition module is used for acquiring data to be transmitted; the determining module is used for determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency and is used for mapping the corresponding bit value; the transmitting module is used for generating at least one corresponding frequency signal for the frequency sequence and sequentially transmitting the frequency signals.

In some embodiments, the frequencies in the sequence of frequencies corresponding to different bit values are different and/or the ordering of the frequencies is different.

In some embodiments, the determining module is specifically configured to: determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value; selecting at least one frequency respectively associated with at least one frequency index from a preset frequency set to form a frequency sequence; and/or, when generating the corresponding at least one frequency signal for the frequency sequence, the transmitting module is specifically configured to: and generating at least one corresponding frequency signal for the frequency sequence by utilizing the digital local oscillation circuit.

In some embodiments, when the data to be transmitted includes a data segment of a data slot; when the bit value is the bit value of the data segment, the determining module is specifically configured to: performing pseudo-random variable conversion on the sum of the first reference value, the bit value and the repetition number of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and clearing the repeated times of the step.

In some embodiments, when the data to be transmitted includes a data synchronization segment of a data slot, and/or the data to be transmitted further includes a synchronization slot, the synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field; when the bit value is a bit value in the data synchronization segment, the initial synchronization segment or the information domain, the determining module is specifically configured to: performing pseudo-random variable conversion on the second reference value, the bit value and the sum of the repetition times of the step to obtain a second frequency index; repeatedly executing the step until a preset number of second frequency indexes are obtained, and resetting the repeated times of the step; if the bit value is the bit value of the synchronous segment, performing pseudo-random variable conversion on the second reference value, the synchronous preset bit value, the preset parameter and the sum of the repetition times of the step to obtain a third frequency index; and repeatedly executing the step until a preset number of third frequency indexes are obtained, and clearing the repeated times of the step.

In some embodiments, the first reference value is a frequency signal hop count accumulated for a current system time; the second reference value is a value formed by a plurality of high-order bit values in the first reference value; the information field comprises transmission parameters and/or low bit values except a plurality of high bit values in the first reference value; the data synchronization section comprises a plurality of data preset bit values, the initial synchronization section comprises a plurality of synchronization preset bit values, and the synchronization section comprises a synchronization preset bit value, wherein the synchronization preset bit value and the data preset bit value are different bit values.

The application also provides another embodiment of the data transmission device. The data transmission device comprises a receiving module, a determining module and a generating module. The receiving module is used for receiving a plurality of frequency signals. The determining module is used for determining the frequency of each frequency signal and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; the generating module is used for generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values so as to obtain transmitted data.

In some embodiments, the determining module is specifically configured to: determining a plurality of groups of different first reference frequency sequences corresponding to preset bit values for synchronization based on a mapping relation between the frequency sequences and the bit values; comparing each group of first reference frequency sequences with a plurality of frequencies respectively to count the times of continuously appearing corresponding first reference frequency sequences in the plurality of frequencies; and taking the first frequency reference sequence with the largest frequency as a current frequency sequence corresponding to a preset bit value, and dividing the frequency remained after the current frequency sequence continuously appears in a plurality of frequencies into at least one group of frequency sequences.

In some embodiments, if the plurality of frequency signals are a plurality of frequency signals in a data slot, wherein the data slot includes a data synchronization segment and a data segment, the data synchronization segment includes a plurality of data preset bit values for data access synchronization, the determining module is specifically configured to: determining a plurality of groups of different first reference frequency sequences corresponding to the preset bit values of the data based on a first mapping relation between the frequency sequences and the bit values of the data synchronization section; generating corresponding bit values for each group of frequency sequences based on a second mapping relation between the frequency sequences and the bit values of the data segments to obtain information of the data segments in the data time slots; when the plurality of frequency signals are a plurality of frequency signals in a synchronous time slot, wherein the synchronous time slot comprises an initial synchronous section, a synchronous section and an information field, the initial synchronous section comprises a plurality of synchronous preset bit values for initial access synchronization, and the synchronous section comprises a synchronous preset bit value for time slot synchronization, the determining module is specifically configured to: determining a plurality of groups of different first reference frequency sequences corresponding to the synchronous preset bit values based on a third mapping relation between the frequency sequences and the bit values of the initial synchronous segment; determining a group of second reference frequency sequences corresponding to the synchronous preset bit values based on a fourth mapping relation between the frequency sequences and the bit values of the synchronous segments; obtaining the residual frequency after the current frequency sequence continuously appears in the plurality of frequencies, and dividing the frequency positioned behind the first reference frequency sequence in the residual frequency into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on a fifth mapping relation between the frequency sequences and the bit values of the information domain so as to obtain information of the information domain in the synchronous time slot.

In some embodiments, the second mapping is associated with a current first reference value, and the first, third, fourth, and fifth mappings are associated with a current second reference value; the second reference value is a value formed by a plurality of high-order bit values in the first reference value; the determining module is specifically configured to: acquiring at least one adjacent reference value which is different from the current second reference value within a preset variation range, respectively utilizing the current second reference value and each adjacent reference value to obtain different mapping relations, and respectively determining different first reference frequency sequences corresponding to the preset bit values according to the different mapping relations; the determining module is specifically configured to: before dividing the frequency remained after the current frequency sequence continuously appears in the plurality of frequencies into at least one group of frequency sequences, selecting the reference value corresponding to the current frequency sequence from the current second reference value and each adjacent reference value as the latest second reference value; and after generating corresponding bit values for each group of frequency sequences based on a fifth mapping relationship between the frequency sequences and the bit values of the information domain to obtain information of the information domain in the synchronous time slot, the determining module is specifically configured to: acquiring a low-order bit value in a first reference value from an information domain; and updating the current second reference value and the low bit value to obtain the latest first reference value.

In some embodiments, the determining module is specifically configured to: each frequency signal is input in parallel to a preset number of frequency detection circuits to determine the frequency of the frequency signal, wherein each frequency detection circuit is used for detecting one frequency.

Referring to fig. 15, fig. 15 is a schematic structural diagram of an embodiment of a device with a memory function in the present application. The data transmission device 500 stores instructions 501, which instructions 501 when executed implement the method of any of the embodiments described above.

The apparatus 500 with a storage function may be specifically a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disc, which may store program instructions, or may be a server storing the program instructions, where the server may send the stored program instructions to other devices for running, or may also self-run the stored program instructions.

The following further details the beneficial effects of the above scheme as follows:

(1) The bit values in the data to be transmitted are mapped onto the frequency sequence, so that symbols in digital communication in the traditional sense are omitted, inter-symbol interference is avoided, meanwhile, as no symbols are omitted, and no processing link of matched filtering exists, all filters can be realized by using cascaded integral comb (Cascade Integrator Comb, CIC) filters and only adders are needed, the complexity and the power consumption of the realization are reduced without using multipliers, and the requirement on the processing capacity of a chip is also reduced;

(2) The high-speed frequency hopping of the continuous carrier phase is adopted, and the hopping period Th is far smaller than the multipath delay spread of the signal, so that the frequency is not repeated in one bit value transmission period, and the influence of multipath signals can be eliminated through a radio frequency tuning filter, an intermediate frequency filter and a digital baseband filter due to the rapid hopping of the signal frequency, so that complex channel equalization processing is avoided, the frequency spectrum utilization rate is improved, and the cost and the power consumption of products are reduced;

(3) In the frequency hopping process, the frequency of a local oscillator signal is kept unchanged, the phase is continuous, the signal in each hop has no modulation in the traditional sense, the instantaneous bandwidth is close to 0, each channel can be allocated with a narrower bandwidth compared with the prior application, the channel capacity is improved, in order to improve the hop count in the prior art, the dual phase-locked loops work alternately, and as the local oscillator frequency is kept unchanged in the scheme, the requirement on the phase-locked loops is reduced, and only one phase-locked loop is needed, so that the hardware cost and the power consumption are reduced;

(4) The bit value in the data to be transmitted is mapped to the frequency sequence, so that the contradiction between high jump speed and frequency spectrum efficiency can be well solved, the adaptation capability and communication distance of the product in a complex terrain environment can be improved by modifying the existing product by using the waveform, and the communication distance can be effectively improved under the condition of increasing power in a new product;

(5) The number of hops is controlled by controlling the number, the reaction time is extremely short, so that higher hop speed, such as 32000 hops/second, can be achieved, and the hop speed is far higher than that of the existing product (such as 1000 hops/second in China generally), so that the existing communication jammer cannot track and interfere the implementation of the communication jammer, and the method has great significance in the field of military communication.

The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims

1. A data transmission method, comprising:

acquiring data to be transmitted;

determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value;

generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals;

the determining a corresponding frequency sequence for each bit value in the data to be transmitted includes:

Determining at least one frequency index in a frequency sequence corresponding to a bit value according to a mapping relation between the frequency sequence and the bit value;

selecting at least one frequency respectively associated with the at least one frequency index from a preset frequency set to form the frequency sequence;

the mapping relation between the frequency sequence and the bit value is a sum of a reference value, a bit value and the repetition number of the step to perform pseudo-random variable conversion, wherein the frequency index=a pseudo-random variable generation function (reference value+bit value+current running number of the function), and the reference value is the frequency signal hop count accumulated in the current system time or a plurality of high bit values corresponding to the frequency signal hop count accumulated in the current system time.

2. Method according to claim 1, characterized in that the frequencies in the sequence of frequencies corresponding to different bit values are different and/or the ordering of the frequencies is different.

3. A method according to claim 1 or 2, characterized in that,

the generating of the corresponding at least one frequency signal for the frequency sequence includes:

and generating at least one corresponding frequency signal for the frequency sequence by utilizing a digital local oscillation circuit.

4. The method of claim 1, wherein the data to be transmitted comprises a data segment of a data slot; the determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value comprises the following steps:

if the bit value is the bit value of the data segment, performing pseudo-random variable conversion on the first reference value, the bit value and the sum of the repetition times of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and resetting the repeated times of the step.

5. The method of claim 4, wherein the data to be transmitted comprises a data synchronization segment of a data slot, and/or the data to be transmitted further comprises a synchronization slot comprising an initial synchronization segment, a synchronization segment, and an information field;

the determining at least one first frequency index corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value comprises the following steps:

if the bit value is the bit value in the data synchronization section, the initial synchronization section or the information domain, performing pseudo-random variable conversion on the second reference value, the bit value and the sum of the repetition times of the step to obtain a second frequency index; repeatedly executing the step until the preset number of second frequency indexes are obtained, and resetting the repeated times of the step;

If the bit value is the bit value of the synchronous segment, performing pseudo-random variable conversion on the second reference value, the synchronous preset bit value, the preset parameter and the sum of the repetition times of the step to obtain a third frequency index; and repeatedly executing the step until the preset number of third frequency indexes are obtained, and clearing the repeated times of the step.

6. The method of claim 5, wherein the first reference value is a frequency signal hop count accumulated for a current system time;

the second reference value is a value formed by a plurality of high-order bit values in the first reference value;

the information field comprises a transmission parameter and/or a low bit value except the plurality of high bit values in the first reference value;

the data synchronization section comprises a plurality of data preset bit values, the initial synchronization section comprises a plurality of synchronization preset bit values, and the synchronization section comprises one synchronization preset bit value, wherein the synchronization preset bit value and the data preset bit value are different bit values.

7. A data transmission method, comprising:

receiving a plurality of frequency signals;

Determining the frequency of each frequency signal, and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences;

generating corresponding bit values for each group of the frequency sequences based on the mapping relation between the frequency sequences and the bit values so as to obtain transmitted data;

the dividing the frequencies corresponding to the frequency signals into at least one group of frequency sequences comprises:

determining a plurality of groups of different first reference frequency sequences corresponding to preset bit values for synchronization based on the mapping relation between the frequency sequences and the bit values;

comparing each group of the first reference frequency sequences with the plurality of frequencies respectively to count the times of continuously appearing corresponding first reference frequency sequences in the plurality of frequencies;

and taking the first frequency reference sequence with the largest frequency as the current frequency sequence corresponding to the preset bit value, and dividing the frequency remained after the current frequency sequence continuously appears in the plurality of frequencies into at least one group of frequency sequences.

8. The method of claim 7, wherein if the plurality of frequency signals are a plurality of frequency signals within a data slot, wherein the data slot comprises a data synchronization segment and a data segment, the data synchronization segment comprising a plurality of data preset bit values for data access synchronization; the determining, based on the mapping relationship between the frequency sequence and the bit value, a plurality of different groups of first reference frequency sequences corresponding to preset bit values for synchronization includes:

Determining a plurality of groups of different first reference frequency sequences corresponding to the preset bit values of the data based on a first mapping relation between the frequency sequences and the bit values of the data synchronization section;

generating a corresponding bit value for each group of the frequency sequences based on the mapping relationship between the frequency sequences and the bit values to obtain transmitted data, including:

generating corresponding bit values for each group of the frequency sequences based on a second mapping relation between the frequency sequences and the bit values of the data segments to obtain information of the data segments in the data time slots;

if the plurality of frequency signals are a plurality of frequency signals in a synchronous time slot, wherein the synchronous time slot comprises an initial synchronous section, a synchronous section and an information field, the initial synchronous section comprises a plurality of synchronous preset bit values for initial access synchronization, and the synchronous section comprises a synchronous preset bit value for time slot synchronization; the determining, based on the mapping relationship between the frequency sequence and the bit value, a plurality of different groups of first reference frequency sequences corresponding to preset bit values for synchronization includes:

determining a plurality of groups of different first reference frequency sequences corresponding to synchronous preset bit values based on a third mapping relation between the frequency sequences and the bit values of the initial synchronous segment;

The dividing the frequencies remaining after the current frequency sequence continuously appears in the plurality of frequencies into at least one group of frequency sequences includes:

determining a group of second reference frequency sequences corresponding to the synchronization preset bit values based on a fourth mapping relation between the frequency sequences and the bit values of the synchronization section;

obtaining the residual frequency after the current frequency sequence continuously appears in the plurality of frequencies, and dividing the frequency positioned behind the first reference frequency sequence in the residual frequency into at least one group of frequency sequences;

and generating corresponding bit values for each group of the frequency sequences based on a fifth mapping relation between the frequency sequences and the bit values of the information domain so as to obtain the information of the information domain in the synchronous time slot.

9. The method of claim 8, wherein the second mapping is associated with a current first reference value, and wherein the first, third, fourth, and fifth mappings are associated with a current second reference value; the second reference value is a value formed by a plurality of high-order bit values in the first reference value;

According to the mapping relationship between the frequency sequence and the bit value, determining a plurality of groups of different first reference frequency sequences corresponding to preset bit values for synchronization includes:

acquiring at least one adjacent reference value which is different from the current second reference value within a preset variation range, respectively utilizing the current second reference value and each adjacent reference value to obtain different mapping relations, and respectively determining different first reference frequency sequences corresponding to the preset bit values according to the different mapping relations;

before said dividing the frequencies remaining after the current frequency sequence occurs consecutively among the plurality of frequencies into at least one set of frequency sequences, the method further comprises:

selecting a reference value corresponding to the current frequency sequence from the current second reference value and each adjacent reference value as the latest second reference value;

after generating a corresponding bit value for each group of the frequency sequences based on the fifth mapping relationship between the frequency sequences and the bit values of the information domain to obtain the information of the information domain in the synchronous time slot, the method further comprises:

Acquiring a low-order bit value in the first reference value from the information domain;

and updating to obtain the latest first reference value by using the current second reference value and the low bit value.

10. The method of claim 7, wherein said determining the frequency of each of said frequency signals comprises:

and inputting each frequency signal into a preset number of frequency detection circuits in parallel to determine the frequency of the frequency signal, wherein each frequency detection circuit is used for detecting one frequency.

11. A transmitter, comprising:

a frequency signal generating circuit for determining a corresponding frequency sequence for each bit value in the data to be transmitted; generating a corresponding at least one frequency signal for the frequency sequence; wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value;

a transmitting circuit for sequentially transmitting the frequency signals;

the frequency signal generating circuit is used for determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value; selecting at least one frequency respectively associated with the at least one frequency index from a preset frequency set to form the frequency sequence; the mapping relation between the frequency sequence and the bit value is a sum of a reference value, a bit value and the repetition number of the step to perform pseudo-random variable conversion, wherein the frequency index=a pseudo-random variable generation function (reference value+bit value+current running number of the function), and the reference value is the frequency signal hop count accumulated in the current system time or a plurality of high bit values corresponding to the frequency signal hop count accumulated in the current system time.

12. The transmitter of claim 11, further comprising a digital-to-analog conversion circuit, an up-converter, a band-pass filter bank, a mixer, and a low-pass filter connected in series between the frequency signal generation circuit and the transmission circuit, wherein the mixer is configured to mix each frequency signal output by the band-pass filter bank with a local oscillator signal, wherein the local oscillator signal mixed with each frequency signal has the same frequency; and/or the number of the groups of groups,

the frequency signal generation circuit includes:

a pseudo-random sequence generator for performing pseudo-random variable conversion based on the bit value to obtain at least one frequency index in a frequency sequence corresponding to the bit value;

and the digital local oscillation circuit is used for selecting at least one frequency respectively associated with the at least one frequency index from a preset frequency set to form the frequency sequence, and generating at least one corresponding frequency signal for the frequency sequence.

13. A receiver, comprising:

a receiving circuit for receiving a plurality of frequency signals;

bit value generating circuitry for determining a frequency of each of the frequency signals and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one set of frequency sequences; generating corresponding bit values for each group of the frequency sequences based on the mapping relation between the frequency sequences and the bit values so as to obtain transmitted data;

The bit value generation circuit is used for determining a plurality of groups of different first reference frequency sequences corresponding to preset bit values used for synchronization based on the mapping relation between the frequency sequences and the bit values; comparing each group of the first reference frequency sequences with the plurality of frequencies respectively to count the times of continuously appearing corresponding first reference frequency sequences in the plurality of frequencies; and taking the first frequency reference sequence with the largest frequency as the current frequency sequence corresponding to the preset bit value, and dividing the frequency remained after the current frequency sequence continuously appears in the plurality of frequencies into at least one group of frequency sequences.

14. The receiver of claim 13, further comprising a band pass filter, a first mixer, a low pass filter, and an analog to digital conversion circuit connected in sequence between the receiving circuit and the bit value generating circuit, wherein the first mixer is configured to mix the received frequency signal with a local oscillator signal of the same frequency; and/or the number of the groups of groups,

the bit value generation circuit includes:

a preset number of frequency detection circuits, wherein each frequency detection circuit is used for detecting one frequency;

Logic processing and decoding circuitry for dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one set of frequency sequences; and generating corresponding bit values for each group of the frequency sequences based on the mapping relation between the frequency sequences and the bit values so as to obtain transmitted data.

15. The receiver of claim 14, wherein the receiver further comprises a digital local oscillator circuit; the frequency detection circuit includes:

the second mixer is used for mixing the frequency signal with a first reference frequency signal generated by the digital local oscillation circuit to obtain a mixed signal;

the digital down converter is used for down-converting the mixed signal to obtain a down-converted signal;

the correlator is used for carrying out correlation operation on the down-conversion signal to obtain a correlation result between the frequency signal and the reference frequency signal;

and the memory is used for determining the storage position of the correlation result of the frequency signals according to the receiving order of the frequency signals and storing the correlation result according to the storage position so that the correlation result sequences obtained by combining the correlation results stored by different memories according to the storage positions of the correlation result sequences are consistent with the receiving order of the corresponding frequency signals.