CN114374586A

CN114374586A - Data transmission method, transmitter and receiver

Info

Publication number: CN114374586A
Application number: CN202011097304.6A
Authority: CN
Inventors: 刘全红; 张翃敔; 陈天水; 吴英慧
Original assignee: Hebi Tianhai Electronic Information System Co Ltd
Current assignee: Hebi Tianhai Electronic Information System Co Ltd
Priority date: 2020-10-14
Filing date: 2020-10-14
Publication date: 2022-04-19
Anticipated expiration: 2040-10-14
Also published as: CN114374586B

Abstract

The application discloses a data transmission method, a transmitter and a receiver, wherein the method comprises the following steps: acquiring data to be transmitted; determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value; and generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals. By means of the method, inter-symbol interference can be avoided, and reliability of data transmission is improved.

Description

Data transmission method, transmitter and receiver

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data transmission method, a transmitter, and a receiver.

Background

Wireless digital communication is a communication method that is currently very popular. In wireless digital communication, information to be transmitted is digitally modulated to obtain symbols, and the symbols are further modulated onto a wireless channel for transmission. However, in a wireless transmission process, for example, a short-wave wireless transmission process, there may be multipath effect, which may further cause Inter Symbol Interference (ISI), that is, Interference of the same signal due to the overlapping of multipath propagation at the receiving end. For complex geographic environments, such as dense streets in high buildings, the phenomenon of abnormal communication is often caused due to the multipath effect.

Disclosure of Invention

The technical problem mainly solved by the application is to provide a data transmission method, a transmitter and a receiver, which can avoid intersymbol interference and improve the reliability of data transmission.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a data transmission method, including: acquiring data to be transmitted; determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value; and generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals.

In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a data transmission method, including: receiving a plurality of frequency signals; determining the frequency of each frequency signal, and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

In order to solve the above technical problem, the present application adopts another technical solution: there is provided a transmitter comprising: the frequency signal generating circuit is used for determining a corresponding frequency sequence for each bit value in the data to be transmitted; generating at least one corresponding frequency signal for the sequence of frequencies; wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping corresponding bit values; and the transmitting circuit is used for sequentially transmitting the frequency signals.

In order to solve the above technical problem, the present application adopts another technical solution that: there is provided a receiver comprising: a receiving circuit for receiving a plurality of frequency signals; the bit value generating circuit is used for determining the frequency of each frequency signal and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

The beneficial effect of this application is: different from the prior art, the method and the device have the advantages that the data to be transmitted are obtained, the corresponding frequency sequence is determined for each bit value in the data to be transmitted, the corresponding at least one frequency signal is generated for the frequency sequence, the frequency signals are sequentially sent, the corresponding bit value is transmitted by sending different frequency sequences, the transmission of information is achieved due to the bit value, the frequency sequence is used for replacing symbols in digital communication in the transmission process, the inter-symbol interference can be avoided, and the reliability of data transmission is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

fig. 1 is a schematic flow chart of a first embodiment of the data transmission method of the present application;

FIG. 2 is a schematic flow chart diagram illustrating a second embodiment of the data transmission method of the present application;

FIG. 3 is a schematic flow chart of a third embodiment of the data transmission method of the present application;

FIG. 4 is a schematic diagram of the structure of the synchronous timeslot of the present application;

FIG. 5 is a schematic diagram of the structure of a data slot of the present application;

FIG. 6 is a schematic flow chart of a fourth embodiment of the data transmission method of the present application;

fig. 7 is a schematic flow chart of a fifth embodiment of the data transmission method of the present application;

FIG. 8 is a schematic flow chart of step S53 in FIG. 7 of the present application;

FIG. 9 is a schematic diagram of the structure of three search windows according to the present application;

FIG. 10 is a schematic diagram of a memory in a receiver according to the present application;

fig. 11 is a schematic structural diagram of a first embodiment of the transmitter of the present application;

fig. 12 is a schematic structural diagram of a second embodiment of the transmitter of the present application;

FIG. 13 is a schematic block diagram of a first embodiment of a receiver of the present application;

FIG. 14 is a schematic block diagram of a second embodiment of a receiver of the present application;

FIG. 15 is a schematic structural diagram of an embodiment of the apparatus with storage function according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The maximum communication distance of the traditional short-wave communication on the ground is generally 30-50 kilometers, and the communication distance is difficult to increase even if the transmission power is increased. The requirement of the private network field, especially the military field, on the communication distance is higher and higher, and no good solution is provided for the military communication within the range of 50-100 kilometers at present. The modulation mode used by the existing ultrashort wave remote digital communication is generally constant envelope modulation, and the multipath effect is not considered in the waveform design in order to take the cost and the frequency spectrum efficiency into consideration, so that the expansion of the communication distance is restricted to a certain extent. If the communication distance is increased, the multipath effect is increased, and the inter-symbol interference is increased.

The existing short-wave communication is widely applied in the military field, but has some problems, for example, firstly, the existing waveform design has very low jump speed, generally only dozens of jumps per second in China, and is easily interfered by enemy detection; second, the delay spread of the short-wave channel is generally over 1ms, and a very complex channel equalization design is required, which increases the cost and the spectrum utilization efficiency.

The data transmission method can be applied to ultra-short wave communication, short wave communication or other waveform wireless digital communication.

Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a data transmission method according to a first embodiment of the present application.

The execution subject of this embodiment may be a transmitter, and the transmitter is a transmitting end of the data transmission system. The transmitter (a transmitter circuit) has the main task of modulating a useful low-frequency signal into a high-frequency carrier, which becomes an electromagnetic wave having a certain bandwidth at a certain center frequency and suitable for being transmitted through an antenna. Transmitters are widely used in television, radio, communications, alarms, radar, remote control, telemetry, electronic countermeasure and other civilian and military equipment.

In this embodiment, the data transmission method includes:

step S11: and acquiring data to be transmitted.

The data to be transmitted is formed by combining one or more bit values according to a certain sequence. The transmitter may generate corresponding data to be transmitted according to the content to be transmitted. Specifically, after the content to be transmitted is subjected to source coding, data to be transmitted, which is formed by combining one or more bit values according to a certain sequence, can be obtained. Wherein the combination order of the one or more bit values is determined by the content to be transmitted corresponding to the data to be transmitted. The contents to be transmitted are not limited to sound, text and images.

The bit values include digits 0 and 1, and correspondingly, the data to be transmitted may be composed of one or more digits 0 or 1 in a certain sequence. For example, the content letter "R" to be transmitted corresponds to 01010010, and the data to be transmitted includes 8 bit values.

Step S12: a corresponding frequency sequence is determined for each bit value in the data to be transmitted.

Wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping corresponding bit values. The frequencies in the frequency sequence corresponding to different bit values are different and/or the ordering of the frequencies is different.

Specifically, the frequencies in the frequency sequences corresponding to different bit values are different, or the ordering of the frequencies in the frequency sequences corresponding to different bit values is different, or the frequencies in the frequency sequences corresponding to different bit values are different and the ordering is different. Wherein, the difference of the frequencies in the frequency sequence may be the difference of the sizes of the frequencies in the frequency sequence and/or the difference of the numbers of the frequencies. The different sizes of the frequencies in the frequency sequences corresponding to the different bit values may be different sizes of at least one frequency in the frequency sequences corresponding to the different bit values. For example, f1, f2, f3, f4, f5, f6, f7 and f8 are eight different frequencies, the frequency sequence corresponding to the bit value 0 is { f1, f2, f3 and f4}, the frequency sequence corresponding to the bit value 1 is { f5, f6, f7 and f8}, and the frequencies in the frequency sequences corresponding to the bit values 0 and 1 are different in size; for another example, the frequency sequence corresponding to the bit value 0 is { f1, f2, f3, f4}, the frequency sequence corresponding to the bit value 1 is { f4, f3, f2, f1}, and the frequency sequences corresponding to the bit values 0 and 1 are different in frequency rank; for another example, the frequency sequence corresponding to the bit value 0 is { f1, f2, f3, f4}, where f1< f2< f3< f4, i.e., the frequencies in the frequency sequence increase sequentially, and the frequency sequence corresponding to the bit value 1 is { f8, f7, f3}, where f8> f7> f3, i.e., the frequencies in the frequency sequence decrease sequentially, where the frequencies in the frequency sequences corresponding to the bit values 0 and 1 are sorted differently and the sizes and numbers of the frequencies are different.

Step S13: and generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals.

The frequency in the frequency sequence is a digital signal, and the transmitter can convert the digital signal in the frequency sequence into a corresponding frequency signal and sequentially transmit the frequency signal. Alternatively, the transmitter may convert the digital signals in the frequency sequence into corresponding frequency signals through the local oscillation circuit.

In the embodiment, by obtaining data to be transmitted, determining a corresponding frequency sequence for each bit value in the data to be transmitted, generating at least one corresponding frequency signal for the frequency sequence, and sequentially sending the frequency signals, the transmission of the corresponding bit value is realized by sending different frequency sequences, the transmission of information is realized if the bit value is the bit value, and the frequency sequence is used for replacing a symbol in digital communication in the transmission process, so that inter-symbol interference can be avoided, and the reliability of data transmission is improved.

Referring to fig. 2, fig. 2 is a flowchart illustrating a data transmission method according to a second embodiment of the present application. The execution subject of this embodiment may be a transmitter, and the transmitter is a transmitting end of the data transmission system. In this embodiment, the data transmission method includes:

step S21: and acquiring data to be transmitted.

For the explanation of this step, reference may be made to the explanation of the corresponding location in the first embodiment of the data transmission method, which is not described herein again.

In the present embodiment, steps S22 and S23 are a specific implementation manner of step S12 in the above embodiment.

Step S22: and determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value.

In this embodiment, the mapping relationship between the frequency sequence and the bit value may be pseudo-random variable conversion performed on the sum of the reference value, the bit value, and the repetition number of this step. Alternatively, the reference value TOD _ COMM may be the accumulated frequency signal hop count TOD of the current system time, or a number of high-order bit values HTOD corresponding to the accumulated frequency signal hop count of the current system time. Specifically, the accumulated frequency signal hop count TOD of the current system time may be obtained by subtracting the reference time from the current system time to obtain an accumulated time value of the current system time from the reference time, and then converting the accumulated time value into the number of frequency signal hop periods. The hop period is the number of hops per unit time. For example, the current system time T2 is 26 # 00: 00/4/2020, the reference time T1 is 23: 59/4/25/2020, and if the skip period T is 1000 hops/sec, the reference value is:

TOD _ COMM ═ TOD ═ (T2-T1) ═ T ═ 1s ═ 1000, and the conversion is made into binary

TOD＝1111101000，

Or the reference value TOD _ COMM takes the first 4 high bits of 1111101000,

TOD_COMM＝HTOD＝1111。

specifically, in step S22, the reference value, the bit value, and the sum of the repetition times of this step may be subjected to pseudo-random variable conversion to obtain a frequency index; and repeatedly executing the step until a first preset number of frequency indexes are obtained, and resetting the repeated times of the step. The first preset number of frequency indexes form a frequency index sequence. Optionally, the first preset number may be selected according to an actual situation, for example, the first preset number may be selected according to a number of currently communicable frequencies, where the currently communicable frequency may be a frequency with a communication quality greater than a preset threshold. In some embodiments, the first preset number may be equal to or less than the number of frequencies at which communication is currently possible. In other embodiments, the first preset number may be greater than the number of currently communicable frequencies, in which case, each of the communicable frequencies may be selected only once, and when the first preset number is greater than the number of currently communicable frequencies, a frequency other than the communicable frequencies, that is, a frequency having a communication quality less than or equal to a preset threshold value may be included in the frequency sequence, but communication is still possible through the frequency, only the communication quality may not reach the preset threshold value; alternatively, each of the communicable frequencies may be selected repeatedly a plurality of times.

The specific calculation formula of the frequency index is as follows: the frequency index is a function of generating a pseudo-random variable (reference value + bit value + current number of times of operation of the function), where the parameters of the function are the reference value, the bit value and the current number of times of operation of the function. The bit value may be 0 or 1, and the Pseudo-Random variable generation function is not limited to a prg (Pseudo Random generator) function, a Pseudo-Random Binary Sequence (PRBS) function, an RS code (Reed-solomon codes) function, such as an Rsenc function. Next, the present embodiment will be described taking a PRG function as an example. The frequency index generation formula corresponding to the PRG function is as follows:

n＝PRG(TOD_COMM+I+e)，

wherein, TOD _ COMM is a reference value, I is a bit value, e is a current operation time of the function, and a value range of e is an integer value between zero and a first preset number, such as 0, 1,2, …, N.

For example, the first predetermined number is 3, the reference value TOD _ COMM is 1111101000, the bit value I is 0,

when the function is run for the first time, e is 1, then n₁＝PRG(1111101000+0+1)＝1；

When the function is run for the second time, e is 2, then n₂＝PRG(1111101000+0+2)＝2；

When the function runs for the third time, e is 3, then n₃PRG (1111101000+0+3) ═ 3; 3 frequency indexes corresponding to the bit value 0 can be obtained, namely the frequency index sequence is {1,2,3}, and then the running times of the function are cleared to prepare for calculating the frequency index corresponding to the next bit value.

Step S23: at least one frequency respectively associated with at least one frequency index is selected from a preset frequency set to constitute a frequency sequence.

Wherein the preset frequency set includes a second preset number of frequencies. Typically, the second predetermined number is an integer power of 2. For example, if the second predetermined number is L, L may be 1,2, 4, 8, 16, etc. Generally, the second predetermined number is greater than or equal to the first predetermined number. In other embodiments, the second predetermined number is less than the first predetermined number. Optionally, the preset frequency set includes at least part of the communicable frequencies.

For example, the frequency index sequence is {1,2,3}, the preset frequency set is { f1, f2, f3, f4, f5, f6, f7, f8}, and the frequency f1 associated with the frequency index 1, the frequency f2 associated with the frequency index 2, the frequency f3 associated with the frequency index 3 are selected from the preset frequency set to form the frequency sequence { f1, f2, f3 }.

Step S24: and generating at least one corresponding frequency signal for the frequency sequence by using the local oscillation circuit, and sequentially transmitting the frequency signals.

The local oscillator circuit in this embodiment may be a digital local oscillator circuit, or may be other local oscillator circuits, such as a crystal oscillator circuit.

In a specific embodiment, the digital local oscillator circuit may include a Numerically Controlled Oscillator (NCO), and the NCO may generate at least one corresponding frequency signal from the frequency sequence and sequentially transmit the frequency signals.

Referring to fig. 3 to 5, fig. 3 is a flowchart illustrating a data transmission method according to a third embodiment of the present application, fig. 4 is a schematic diagram illustrating a structure of a synchronization slot according to the present application, and fig. 5 is a schematic diagram illustrating a structure of a data slot according to the present application. The execution subject of this embodiment may be a transmitter, and the transmitter is a transmitting end of the data transmission system. As shown in fig. 5, in this embodiment, the data transmission method includes:

step S31: and acquiring data to be transmitted.

For the explanation of this step, reference may be made to the explanation of the corresponding position in the first embodiment of the data transmission method, and details are not described here.

In this embodiment, the data to be transmitted includes a synchronization slot and/or a data slot. Specifically, the data to be transmitted may include only the synchronization slots, or only the data slots, or both the synchronization slots and the data slots. The synchronization slots may be transmitted according to a synchronization transmission period. In some embodiments, the synchronization transmission period is a preset number of data slots at intervals, that is, one synchronization slot is transmitted after each preset number of data slots is transmitted, for example, when the preset number is 1, the synchronization slot and the data slot are transmitted at intervals, that is, 1 synchronization slot is transmitted before each data slot is transmitted; when the preset number is 2, 2 data slots can be continuously transmitted and then 1 synchronization slot can be transmitted, and so on. In other embodiments, the synchronization transmission period is transmitted in units of time, i.e., one synchronization slot is transmitted at intervals, for example, the synchronization transmission period may be one synchronization slot transmitted every second.

As shown in fig. 4, the synchronization slot may sequentially include an initial synchronization segment, a synchronization segment, and an information field. The synchronization time slot is transmitted before the data time slot is transmitted, and is used for realizing initial access synchronization, time slot synchronization, and synchronization of transmission parameters and/or low-order bit values except a plurality of high-order bit values in the first reference value. Specifically, the initial synchronization segment of the synchronization slot includes a predetermined number of groups of repeated frequency sequences for achieving initial access synchronization, for example, the predetermined number may be 7. The synchronization segment of the synchronization slot comprises a set of frequency sequences for achieving synchronization of the slot. Wherein the initial synchronization segment is different from the frequency sequence in the synchronization segment. The information field of the synchronization slot is used for realizing the synchronization of the transmission parameter and/or the first reference value divided by a plurality of high-order bit values. The high-order bit values of the receiving end and the transmitting end can be guaranteed according to hardware or avoided in use, so that the high-order bit values can not be transmitted generally. For example, the year, month and day of the receiving end and the transmitting end are generally the same. The information domain comprises a plurality of groups of frequency sequences, and the number of the frequency sequences is determined by the number of bit values in the data to be transmitted corresponding to the information domain. The transmission parameter is, for example, a modulation scheme, a coding scheme (e.g., a coding rate, a convolutional code), and the like.

As shown in fig. 5, the data slot may sequentially include a data sync segment and a data segment. The data sync segment includes a predetermined number of groups of repeated frequency sequences, for example the predetermined number may be 7. The frequency sequence in the data sync segment may be the same as or different from the frequency sequence in the initial sync segment, the sync segment. In this embodiment, the synchronization segment is transmitted before the data segment, so that the influence caused by clock drift or spatial delay can be avoided, and the access synchronization of data is realized. For example, in the case that the transmitting end and the receiving end are far away from each other, the propagation itself of the signal and the radio wave requires time, and in the case of application to an aircraft, the instantaneous distance of the aircraft during flight also changes. The data segment is used for transmitting data to be transmitted corresponding to the content to be transmitted of the user. Optionally, the transmitter may generate corresponding initial data to be transmitted according to the content to be transmitted, and perform channel coding on the initial data to be transmitted to obtain the data to be transmitted. In the channel coding process, the coding class can be selected according to the requirement of the data transmission system, and the coding class is not limited to convolutional codes and TURBO codes. In this embodiment, the data to be transmitted initially is subjected to channel coding, that is, redundancy is added to useful information in the data to be transmitted initially, for example, the data to be transmitted initially is a 100-bit value, and the data to be transmitted obtained after the channel coding is a 200-bit value, so that reliability of data transmission can be improved, and anti-interference capability can be increased.

The initial sync segment includes a plurality of sync preset bit values. The sync segment includes a sync preset bit value. The data sync segment includes a plurality of data preset bit values. The synchronous preset bit value and the data preset bit value are different bit values, for example, when the synchronous preset bit value is 1, the data preset bit value is 0; when the synchronization preset bit value is 0, the data preset bit value is 1, so that the frequency index sequence corresponding to the data synchronization segment is different from the frequency index sequences corresponding to the initial synchronization segment and the synchronization segment, the frequency sequence in the data synchronization segment is different from the frequency sequences in the initial synchronization segment and the synchronization segment, and the receiving end can judge the initial synchronization segment, the synchronization segment and the data synchronization segment according to the received frequency sequence.

Optionally, before step S32, the data to be transmitted may also be grouped, each group including data to be transmitted of several bit values. In this embodiment, each group includes the same number of bit values. In other embodiments, each group may include a different number of bit values. The basis for the grouping may be the number of bit values per transmission. The data transmission system is not limited to being counted in binary, quaternary, decimal or hexadecimal form. For example, when the current data to be transmitted is a 200-bit value and the counting mode of the current system is binary, only a 1-bit value can be sent each time, the 200-bit values can be divided into 200 groups, and each group includes a 1-bit value; when the counting mode of the current system is quaternary, only 2-bit values can be transmitted each time, and 200-bit values can be divided into 100 groups, each group including 2-bit values.

In the present embodiment, steps S32 and S33 are a specific implementation manner of step S12 in the above embodiment.

Step S32: and determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value.

For the explanation of this step, reference may be made to the explanation of the corresponding position in the above embodiments, and details are not described here.

In contrast, in the present embodiment, when generating the frequency sequence index corresponding to the data segment, the reference value TOD _ COMM takes the frequency signal hop count accumulated by the current system time, i.e. the first reference value TOD. When the frequency sequence index corresponding to the initial sync segment, the sync segment, and the information field and the data sync segment in the sync slot is generated, the reference value TOD _ COMM is a plurality of high-order bit values of TOD, i.e., the second reference value HTOD.

When the data to be transmitted includes a data segment of the data slot, and the bit value is a bit value of the data segment, step S32 includes: carrying out pseudo-random variable conversion on the first reference value, the bit value and the sum of the repetition times of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and resetting the repeated times of the step. And the mapping relation between the frequency sequence and the bit value in the data segment is that the sum of the first reference value, the bit value and the repetition times of the step is subjected to pseudo-random variable conversion. The first reference value is the frequency signal hop count accumulated by the current system time.

This embodiment exemplifies the pseudo random variable generation function as the PRG function.

The frequency index generation formula corresponding to the data segment of the data time slot is as follows:

n＝PRG(TOD+I+e)，

wherein TOD is a first reference value, I is a bit value in the data segment, e is a current operation time of the function, and a value range of e is an integer value between zero and a preset number, such as 0, 1,2, …, N.

When the data to be transmitted includes the data synchronization segment of the data slot, and/or the data to be transmitted further includes the synchronization slot, the synchronization slot includes the initial synchronization segment and the information field, and the bit value is a bit value in the data synchronization segment, the initial synchronization segment, or the information field, step S32 includes: carrying out pseudo-random variable conversion on the second reference value, the bit value and the sum of the repetition times of the step to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and resetting the repeated times of the step. And the mapping relation among the frequency sequences and the bit values in the data synchronization segment, the initial synchronization segment and the information domain is that the sum of the second reference value, the bit value and the repetition times of the step is subjected to pseudo-random variable conversion. The second reference value is a value composed of a plurality of high-order bit values in the first reference value. In this embodiment, the number of discarding the low-order bit value in the first reference value may be determined by the size of the signal transmission delay, that is, the number of the high-order bit value in the first reference value is determined by the second reference value. Specifically, the second reference value:

HTOD＝TOD[MSB:E]，

wherein MSB (most Significant bit) is the most Significant bit; e is the number of bits of the high-order bit value, E is equal to the transmission delay divided by the duration (i.e., the hop period) of each frequency transmission in the frequency sequence, and the obtained value is rounded up to obtain the hop count corresponding to the transmission delay, and then the hop count corresponding to the transmission delay is logarithmized by 2, and the specific calculation formula is as follows:

E＝log₂[ceil(delay/Th)]，

wherein ceil is an rounding-up function, Delay is a time Delay, Th is a duration of each frequency transmission in the frequency sequence, and the duration of each frequency transmission in the frequency sequence may be the same and fixed.

Specifically, the frequency index generation formula corresponding to the data synchronization segment, the initial synchronization segment, or the information field is as follows:

n＝PRG(TODH+I+e)，

wherein, TODH is a second reference value, I is a bit value in the data synchronization segment, the initial synchronization segment, or the information domain, e is a current operation time of the function, and a value range of e is an integer value between zero and a preset number, such as 0, 1,2, …, N. It should be noted that the preset bit values corresponding to the initial synchronization segment and the data synchronization segment are different, the initial synchronization segment is a synchronous preset bit value, and the data synchronization segment is a data preset bit value.

When the data to be transmitted further includes a sync slot, the sync slot includes a sync segment, and the bit value is a bit value of the sync segment, step S32 includes: carrying out pseudo-random variable conversion on the second reference value, the synchronous preset bit value, the preset parameter and the sum of the repetition times of the step to obtain a third frequency index; and repeating the step until a preset number of third frequency indexes are obtained, and resetting the repetition times of the step. And the mapping relation between the frequency sequence and the bit value in the synchronization segment is that the second reference value, the synchronization preset bit value, the preset parameter and the sum of the repetition times of the step are subjected to pseudo-random variable conversion. The preset value may be a total number of frequencies obtained by the initial synchronization segment, that is, a product of the repetition number of the frequency sequence in the initial synchronization segment and the hop count of each bit value information in the initial synchronization segment.

Specifically, the frequency index generation formula corresponding to the synchronization segment in the synchronization slot is as follows:

n＝PRG(TODH+a+I+e)，

wherein, TODH is a second reference value, a is a preset parameter, I is a bit value in the synchronization segment, e is a current running time of the function, and a value range of e is an integer value between zero and a preset number, such as 0, 1,2, …, N.

Step S33: at least one frequency respectively associated with at least one frequency index is selected from a preset frequency set to constitute a frequency sequence.

For the explanation of this step, reference may be made to the explanation of the corresponding position in the above embodiment, which is not described herein again.

Step S34: and generating at least one corresponding frequency signal for the frequency sequence by using the digital local oscillator circuit, and sequentially transmitting the frequency signals.

In one embodiment, as shown in fig. 4, a synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field. The initial sync segment includes 7 repeated sets of frequency sequences S0, wherein each set of frequency sequences S0 corresponds to a sync default bit value of 0, and the initial sync segment corresponds to 7 sync default bit values of 0. The synchronization segment includes 1 set of frequency sequences SYNC, wherein the frequency sequences SYNC correspond to a synchronization preset bit value 0. The information field comprises several sets of frequency sequences SIGNAL. The frequency sequence SIGNAL is determined by the transmission parameter conveyed by the information field and/or the bit value of the first reference value except for a number of high bit values. As shown in fig. 5, the data slot includes a data sync segment and a data segment. The data sync segment includes 7 repeated sets of frequency sequences S1, wherein each set of frequency sequences S1 corresponds to a data preset bit value of 1, and the initial sync segment corresponds to 7 data preset bit values of 1. The DATA segment includes a plurality of sets of frequency sequences DATA, which are determined by the DATA transmitted by the DATA segment.

Referring to fig. 6, fig. 6 is a schematic flowchart illustrating a data transmission method according to a fourth embodiment of the present application. The main body of the implementation of this embodiment may be a receiver, which is a receiving end of a data transmission system.

The receiver has the main functions of selecting self-needed frequency components from a plurality of electromagnetic waves existing in the air, suppressing or filtering out unwanted signals or noise and interference signals, and then obtaining original useful information through amplification and demodulation.

In this embodiment, the data transmission method includes:

step S41: a plurality of frequency signals is received.

The frequency signal may be an electromagnetic wave signal. The receiver may receive the plurality of frequency signals sequentially through one receiving circuit, or the receiver may receive the plurality of frequency signals in parallel using a plurality of receiving circuits.

Step S42: the frequency of each frequency signal is determined, and a plurality of frequencies corresponding to the plurality of frequency signals are divided into at least one group of frequency sequences.

Alternatively, the receiver may determine a frequency of each of the plurality of frequencies, and store the determined frequency at a corresponding position of the frequency sequence, so that the receiver may divide the plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences according to a preset number.

Step S43: and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

The receiver can obtain the mapping relation between the frequency sequence and the bit value, and generate the corresponding bit value for each group of frequency sequence according to the mapping relation between the frequency sequence and the bit value, so as to obtain the transmitted data.

Alternatively, the mapping relationship between the frequency sequence and the bit value may be pre-stored in the receiver or the server, the receiver may obtain the mapping relationship between the frequency sequence and the bit value from a local area, or may be connected to the server, and obtain the mapping relationship between the frequency sequence and the bit value from the server, or the receiver may obtain the mapping relationship between the frequency sequence and the bit value from a plurality of received frequency signals.

In this embodiment, a plurality of frequencies corresponding to a plurality of received frequency signals are divided into at least one group of frequency sequences, and corresponding bit values are generated for each group of frequency sequences based on a mapping relationship between the frequency sequences and the bit values to obtain transmitted data, so that the corresponding bit values can be mapped through the frequency sequences, data transmission is realized, symbols in digital communication are omitted, intersymbol interference can be avoided, and reliability of data transmission is improved.

Referring to fig. 7 to 10, fig. 7 is a schematic flowchart of a fifth embodiment of the data transmission method of the present application, fig. 8 is a schematic flowchart of step S53 in fig. 7 of the present application, fig. 9 is a schematic structural diagram of three search windows of the present application, and fig. 10 is a schematic storage diagram of a memory in a receiver of the present application. The execution subject of this embodiment may be a receiver, which is a receiving end of the data transmission system. In this embodiment, the data transmission method includes:

step S51: a plurality of frequency signals is received.

The description of this step may be the description of the corresponding position in the above embodiments, and is not repeated herein.

In this embodiment, the plurality of frequency signals may be frequency signals in a data slot and/or frequency signals in a synchronization slot. The synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field. The initial synchronization segment includes a plurality of synchronization preset bit values for initial access synchronization. The sync segment includes a sync preset bit value for slot synchronization. The information field comprises a plurality of bit values related to the transmission parameter and/or the first reference value divided by a plurality of high bit values, and is used for realizing synchronization of the transmission parameter and/or the first reference value divided by the plurality of high bit values. The data slot includes a data sync segment and a data segment. The data synchronization segment includes a plurality of data preset bit values for data access synchronization. The data segment comprises a plurality of bit values in the data to be transmitted corresponding to the content to be transmitted and is used for transmitting the data. Generally, a receiver receives a synchronization time slot first to achieve initial synchronization, time slot synchronization, synchronization of a transmission parameter and/or a value obtained by dividing a plurality of high-order bit values in a first reference value, and then receives a data time slot to achieve access synchronization of data and data transmission. In this embodiment, for the explanation of the data time slot and the synchronization time slot, reference may be made to the explanation of the corresponding position in the above embodiments, and details are not described here.

Steps S52-S53 are a specific implementation of step S42 in the above embodiment.

Step S52: the frequency of each frequency signal is determined.

Specifically, each frequency signal is input in parallel to a preset number of frequency detection circuits to determine the frequency of the frequency signal. Wherein each frequency detection circuit is configured to detect a frequency.

The frequency detection circuit may include a second mixer, a digital down-converter, a correlator, and a memory. The second frequency mixer is used for mixing the frequency signal with a first reference frequency signal generated by the digital local oscillator circuit to obtain a mixed frequency signal. And the carrier signal in the frequency signal is filtered out from the mixed frequency signal obtained by mixing through the second mixer. The digital down converter is used for carrying out down conversion on the mixing signal to obtain a down conversion signal. The correlator is used for carrying out correlation operation on the down-conversion signals to obtain a correlation result between the frequency signals and the reference frequency signals. The correlation operation is, for example, a convolution operation. The memory is used for determining the storage position of the correlation result of the frequency signal according to the receiving sequence of the frequency signal and storing the correlation result according to the storage position, so that the correlation result sequence obtained by combining the correlation results stored by different memories according to the storage positions is consistent with the receiving sequence of the corresponding frequency signal. The memory may store the correlation result in parallel for a predetermined number of hops, where the predetermined number is equal to a predetermined number in a frequency sequence of a predetermined number of frequencies transmitted by the transmitting end, so that the receiving end can perform multi-hop joint detection with a previously stored frequency when receiving a last frequency in the frequency sequence transmitted by the transmitting end.

In a specific embodiment, as shown in fig. 10, a frequency sequence transmitted by a transmitting end includes 7 frequencies { f7, f6, f5, f4, f3, f2, and f1}, and a receiving end receives frequencies f7, f6, f5, f4, f3, f2, and f1 in sequence. Similarly, after the receiving end receives the frequencies f6, f5, f4, f3, and f2, the corresponding correlation results are stored for 7 hops, so that when the receiving end receives the last frequency f1 in the frequency sequence sent by the sending end, the receiving end may check the frequency f1 together with the previously stored frequencies 6 f7, f6, f5, f4, f3, and f2, that is, perform multi-hop joint detection. The memory can store L paths of parallel memory, wherein L is the number of frequencies in a preset frequency set.

Optionally, the transmitter further includes, after receiving the plurality of frequency signals, sequentially passing the plurality of frequency signals through the band-pass filter, the first mixer, the low-pass filter, and the analog-to-digital conversion circuit, and then inputting each frequency signal in parallel to the preset number of frequency detection circuits. The band-pass filter is used for passing frequency signals of a specific frequency band and shielding frequency signals of other frequency bands. The first frequency mixer is used for mixing the received frequency signal with a local oscillator signal of the same frequency. The first mixer is used for removing the carrier wave in the frequency signal. The low pass filter may remove high frequency portions of the frequency signal and leave useful low frequency portions of the frequency signal. The analog-to-digital conversion circuit may convert the analog signal to a digital signal.

Step S53: and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences.

In one case, such as when the received plurality of frequency signals are frequency signals in a synchronization segment, an information field, or a data segment, the plurality of frequencies may be divided into at least one set of frequency sequences directly after determining the frequency of each frequency signal. Alternatively, when the received multiple frequency signals are multiple frequency signals in an initial synchronization segment or a data synchronization segment, after the frequency of each frequency signal is determined, the multiple frequencies need to be divided into different groups of frequency sequences according to a first reference frequency sequence by determining multiple different groups of first reference frequency sequences corresponding to preset bit values for synchronization, so as to determine a current frequency sequence corresponding to the preset bit values. Step S531: and determining a plurality of different groups of first reference frequency sequences corresponding to the preset bit values for synchronization based on the mapping relation between the frequency sequences and the bit values.

Specifically, at least one adjacent reference value, the difference between which and the current second reference value is within a preset variation range, is obtained, different mapping relationships are obtained by respectively using the current second reference value and each adjacent reference value, and different first reference frequency sequences corresponding to preset bit values are respectively determined according to the different mapping relationships.

The current second reference value is a plurality of high-order bit values corresponding to frequency signal hops accumulated by the current system time of the receiver. When the time difference between the sending end and the receiving end of the frequency signal is within the allowed range, the difference values of the second reference values at the two ends are only three possibilities of-1, 0 and +1, and the second reference values can be selected according to the time delay of the system, so that the difference values of the second reference values at the two ends are only three possibilities of-1, 0 and +1 by controlling the values of the second reference values, so that different mapping relationships can be obtained by using the current second reference value and at least one adjacent reference value which has a difference with the current second reference value within a preset variation range, and different first reference frequency sequences corresponding to preset bit values are respectively determined according to the different mapping relationships.

For example, the current second reference value at the transmitting end is 99, the frequency sequence corresponding to the preset bit value generated by the transmitting end according to the current second reference value is { f1, f2, f3}, the current second reference value at the receiving end is 100, the frequency sequence corresponding to the preset bit value generated by the receiving end according to the current second reference value is { f2, f3, f1}, and the frequency sequence { f2, f3, f1} is used as the first reference frequency sequence. If the transmitting end only transmits one group of frequency sequences { f1, f2, f3}, the receiving end cannot successfully identify the frequency signal transmitted by the transmitting end according to the current first reference frequency sequence { f2, f3, f1}, and if the transmitting end transmits multiple groups of repeated frequency sequences { f1, f2, f3}, the receiving end can identify the frequency signal transmitted by the transmitting end according to the current first reference frequency sequence { f2, f3, f1}, but cannot identify the frequency sequence actually transmitted by the transmitting end as { f1, f2, f3}, so that the receiving end still takes the second reference value 100 corresponding to the current first reference frequency sequence as the current second reference value of the transmitting end, obviously that the current second reference value of the transmitting end is 99, and the receiving end does not realize the synchronization of the second reference value. In this embodiment, to implement synchronization of the second reference values of the receiving end and the transmitting end, the receiving end and the transmitting end may select the second reference value according to the system delay, so that the difference between the second reference values at the two ends of the receiving end and the transmitting end is only-1, 0, and +1, the current second reference value of the receiving end is 100, and the adjacent reference values 99 and 101 are correspondingly taken, so that different mapping relationships are obtained by using the current second reference value 100 of the receiving end and the adjacent reference values 99 and 101, and different first reference frequency sequences corresponding to the preset bit values are respectively determined according to the different mapping relationships. The first reference frequency series corresponding to the second reference value 100 is { f2, f3, f1}, the first reference frequency series corresponding to the second reference value 99 is { f1, f2, f3}, and the first reference frequency series corresponding to the second reference value 101 is { f3, f1, f2 }. Alternatively, the receiving end may also take an adjacent reference value, for example 99, which is different from the current second reference value within a preset variation range.

In some embodiments, the plurality of frequency signals are a plurality of frequency signals within a synchronization slot, the synchronization slot includes a synchronization preset bit value in the initial synchronization segment, and several different sets of first reference frequency sequences corresponding to the synchronization preset bit value are determined based on a third mapping relationship between the frequency sequences and the bit value of the initial synchronization segment. The third mapping relation between the frequency sequence and the bit value of the initial synchronization segment is that the second reference value or the sum of the adjacent reference values, the synchronous preset bit value and the repetition times of the step are subjected to pseudo-random variable conversion to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and resetting the repeated times of the step. Reference may be made to the description of the corresponding positions in the above embodiments, which is not repeated herein.

For example, if the current second reference value of the receiving end is 100, and the adjacent reference values are 99 and 101, then the frequency index generation formula n ═ PRG (TODH + I + e) can be obtained: when the synchronization preset bit value I is 1 and TODH is the current second reference value 100 of the receiving end, the obtained frequency index sequence is {2,3,1}, and the corresponding frequency sequence is { f2, f3, f1 }; when the synchronization preset bit value I is 1 and TODH is the adjacent reference value 99, the obtained frequency index sequence is {2,1,3}, and the corresponding frequency sequence is { f2, f1, f3 }; when the synchronization preset bit I is 1 and TODH is the adjacent reference value 101, the obtained frequency index sequence is {3,2,1}, and the corresponding frequency sequence is { f3, f2, f1 }.

In other embodiments, the plurality of frequency signals are a plurality of frequency signals in a data slot, the data slot includes a data preset bit value in the data synchronization segment, and a plurality of different sets of second reference frequency sequences corresponding to the data preset bit value are determined based on a first mapping relationship between the frequency sequence and the bit value of the data synchronization segment. The first mapping relation between the frequency sequence and the bit value of the data synchronization segment is that the second reference value or the sum of the adjacent reference values, the data preset bit value and the repetition times of the step are subjected to pseudo-random variable conversion to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and resetting the repeated times of the step. Reference may be made to the description of the corresponding positions in the above embodiments, which is not repeated herein. It should be noted that the second reference value is a second reference value updated by the receiving end after receiving the synchronization time slot, and due to the influence of factors such as clock drift or spatial delay, when the receiving end receives the data time slot, the second reference values in the receiving end and the transmitting end may still be inconsistent, so the present embodiment can implement access synchronization of data by adding the data synchronization segment before the data segment.

For example, if the second reference value updated by the receiving end after receiving the synchronization slot is 99, and the adjacent reference values are 98 and 100, the receiving end may generate a formula n ═ PRG (TODH + I + e) according to the frequency index: when the preset data bit value I is 0 and TODH is the current second reference value 98 of the receiving end, the obtained frequency index sequence is {5,4,6}, and the corresponding second reference frequency sequence is { f5, f4, f6 }; when the synchronization preset bit value I is 0 and TODH is an adjacent reference value 99, the obtained frequency index sequence is {4,5,6}, and the corresponding second reference frequency sequence is { f4, f5, f6 }; when the synchronization preset bit value I is 0 and TODH is the adjacent reference value 100, the obtained frequency index sequence is {6,5,4}, and the corresponding second reference frequency sequence is { f6, f5, f4 }.

Step S532: and respectively comparing each group of first reference frequency sequences with a plurality of frequencies to count the times of continuous occurrence of the corresponding first reference frequency sequences in the plurality of frequencies, and taking the first frequency reference sequence with the largest time as the current frequency sequence corresponding to the preset bit value.

In one embodiment, as shown in fig. 9, the plurality of frequencies received by the receiver are f1, f2, f 3; f1, f2, f 3; f1, f2, f 3; f1, f2, f 3; f1, f2, f 3; f1, f2, f 3; f1, f2, f3, the frequencies are 7 groups of repeated frequency sequences S1{ f1, f2, f3} in the data sync segment. The receiver searches using three search windows, respectively. The first reference frequency series corresponding to the second reference value 100 is { f2, f3, f1}, i.e. the first search window WIN 0; the second reference value 99 corresponds to the first reference frequency sequence { f1, f2, f3}, i.e. the second search window WIN-1; the second reference value 101 corresponds to the first reference frequency sequence { f3, f1, f2}, i.e. the third search window WIN +1, and compares the three groups of the first reference frequency sequences with a plurality of frequencies, wherein the plurality of frequencies occur 6 times in succession corresponding to { f2, f3, f1}, 7 times corresponding to { f1, f2, f3}, and 6 times corresponding to { f3, f1, f2 }. And taking the first frequency reference sequence { f1, f2, f3} with the largest frequency as the current frequency sequence corresponding to the preset bit value.

In the above embodiment, the plurality of frequencies are aligned with the first reference frequency sequence, that is, the frequencies are aligned with the frequencies, and in other embodiments, the plurality of frequencies may be converted into corresponding frequency indexes and then aligned with the frequency indexes corresponding to the first reference frequency sequence.

Step S533: frequencies remaining after a current frequency sequence occurs consecutively among the plurality of frequencies are divided into at least one group of frequency sequences.

After dividing a plurality of frequencies corresponding to a plurality of frequency signals in an initial synchronization segment in a synchronization slot into at least one group of frequency sequences, the remaining frequencies after the current frequency sequence, i.e. the frequencies in the synchronization segment, are continued to be divided into at least one group of frequency sequences. Specifically, a group of second reference frequency sequences corresponding to the synchronous preset bit values are determined based on a fourth mapping relation between the frequency sequences and the bit values of the synchronous segments; acquiring the remaining frequencies after the current frequency sequence appears continuously in the plurality of frequencies, and dividing the frequencies after the first reference frequency sequence in the remaining frequencies into at least one group of frequency sequences. The fourth mapping relation between the frequency sequence and the bit value of the synchronization segment is that the second reference value, the synchronization preset bit value, the preset parameter and the sum of the repetition times of the step are subjected to pseudo-random variable conversion to obtain a third frequency index; and repeating the step until a preset number of third frequency indexes are obtained, and resetting the repetition times of the step. Reference may be made to the description of the corresponding positions in the above embodiments, which is not repeated herein.

Optionally, before step S533, the method further includes selecting a reference value corresponding to the current frequency sequence from the current second reference value and each adjacent reference value as a latest second reference value, so as to implement synchronization of the second reference values of the receiving end and the transmitting end. Specifically, the reference value corresponding to the current frequency sequence may be selected from the initial sync segment as the latest second reference value for the calculation of the second reference value in the sync segment, the information field, and the data sync segment, and the reference value corresponding to the current frequency sequence may be selected from the data sync segment as the latest second reference value for the calculation of the second reference value in the data segment.

Step S54: and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

And when the plurality of frequency signals are a plurality of frequency signals in the synchronization time slot, generating corresponding bit values for each group of frequency sequences based on a fifth mapping relation between the frequency sequences and the bit values of the information domain to obtain the information of the information domain in the synchronization time slot. And the fifth mapping relation is that pseudo-random variable conversion is carried out according to the frequency index corresponding to the frequency in the received frequency sequence, the second reference value and the sum of the repetition times of the step to obtain a corresponding bit value. For example, the frequency index corresponding to the received frequency index { f1, f2, f3} is {1,2,3}, the updated second reference value is 99, and the sum of the repetition times of this step is subjected to pseudo-random variable conversion to obtain a bit value of 1 corresponding to the frequency index { f1, f2, f3 }.

Optionally, after obtaining the information of the information field in the synchronization slot, the method further includes: acquiring a low bit value in the first reference value from the information domain; and updating to obtain the latest first reference value by utilizing the current second reference value and the low-order bit value so as to realize the synchronization of the first reference values of the receiving end and the transmitting end.

And when the plurality of frequency signals are a plurality of frequency signals in the data time slot, generating corresponding bit values for each group of frequency sequences based on a second mapping relation between the frequency sequences and the bit values of the data segments so as to obtain the information of the data segments in the data time slot. And the second mapping relation is that pseudo-random variable conversion is carried out according to the frequency index corresponding to the frequency in the received frequency sequence, the first reference value and the sum of the repetition times of the step to obtain a corresponding bit value. In this embodiment, the operation of generating the corresponding bit value according to each group of frequency sequences and the operation of generating each group of frequency sequences according to the bit value in the above embodiment are inverse operations, which may specifically refer to the explanation of the corresponding position in the above embodiment, and will not be described here again.

In this embodiment, the second mapping relationship is related to the current first reference value, and the first mapping relationship, the third mapping relationship, the fourth mapping relationship, and the fifth mapping relationship are related to the current second reference value. The second reference value is a value composed of a plurality of high-order bit values in the first reference value.

Referring to fig. 11, fig. 11 is a schematic structural diagram of a transmitter according to a first embodiment of the present application.

The transmitter includes a frequency signal generation circuit 11 and a transmission circuit 12. The frequency signal generating circuit 11 is configured to determine a corresponding frequency sequence for each bit value in the data to be transmitted, and generate at least one corresponding frequency signal for the frequency sequence. The frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping corresponding bit values. The transmission circuit 12 is used to sequentially transmit the frequency signals.

In this embodiment, for the explanation of the frequency signal generating circuit 11 and the transmitting circuit 12, reference may be made to the explanation of corresponding positions in the above embodiments, and details are not described here.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a transmitter according to a second embodiment of the present application.

The transmitter includes a frequency signal generating circuit 21 and a transmitting circuit 22, and unlike the above-described embodiment, the transmitter further includes a digital-to-analog converting circuit 23, an up-converter 24, a band-pass filter bank 25, a mixer 26, and a low-pass filter 27 in this embodiment. Among them, a digital-to-analog conversion circuit 23, an up-converter 24, a band-pass filter bank 25, a mixer 26, and a low-pass filter 27 are connected in order between the frequency signal generation circuit 21 and the transmission circuit.

The frequency signal generating circuit 21 is configured to determine a corresponding frequency sequence for each bit value in the data to be transmitted, and generate at least one corresponding frequency signal for the frequency sequence. The sequence of frequencies includes at least one frequency. The frequency sequence is used to map the corresponding bit values. And the frequencies in the frequency sequences corresponding to the different bit values are different and/or the ordering of the frequencies is different.

The frequency signal generation circuit 21 further includes a pseudo random sequence generator 211 and a digital local oscillation circuit 212. The pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion based on bit values to obtain at least one frequency index in a frequency sequence corresponding to the bit values.

When the data to be transmitted includes a data segment of a data time slot and the bit value is the bit value of the data segment, the pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion on the sum of the first reference value, the bit value, and the repetition number of this step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and resetting the repeated times of the step.

When the data to be transmitted includes a data synchronization segment of a data time slot, and/or the data to be transmitted also includes a synchronization time slot, the synchronization time slot includes an initial synchronization segment and an information domain, and a bit value is a bit value in the data synchronization segment, the initial synchronization segment, or the information domain, the pseudorandom sequence generator 211 is configured to perform pseudorandom variable conversion on a second reference value, the bit value, and the sum of the repetition times of this step to obtain a second frequency index; and repeatedly executing the step until a preset number of second frequency indexes are obtained, and resetting the repeated times of the step.

When the data to be transmitted further includes a synchronization slot, the synchronization slot includes a synchronization segment, and the bit value is a bit value of the synchronization segment, the pseudo-random sequence generator 211 is configured to perform pseudo-random variable conversion on the sum of the second reference value, the synchronization preset bit value, the preset parameter, and the repetition number of this step, so as to obtain a third frequency index; and repeating the step until a preset number of third frequency indexes are obtained, and resetting the repetition times of the step.

The second reference value is a value formed by a plurality of high-order bit values in the first reference value. The information field comprises the transmission parameter and/or a lower bit value of the first reference value except for a plurality of higher bit values. The data synchronization segment comprises a plurality of data preset bit values, the initial synchronization segment comprises a plurality of synchronous preset bit values, the synchronization segment comprises a synchronous preset bit value, and the synchronous preset bit value and the data preset bit value are different bit values.

The digital local oscillator circuit 212 is configured to select at least one frequency from a preset frequency set, where the at least one frequency is respectively associated with at least one frequency index, to form a frequency sequence, and to generate at least one corresponding frequency signal for the frequency sequence.

The digital-to-analog conversion circuit 23 is used to convert the digital signal into an analog signal. The up-converter 24 is used to convert an input signal having a certain frequency into an output signal having a higher frequency. The band-pass filter is used for passing frequency signals of a specific frequency band and shielding frequency signals of other frequency bands. The mixer 26 is used for mixing each frequency signal output by the band-pass filter bank 25 with a local oscillator signal, wherein the frequency of the local oscillator signal mixed with each frequency signal is the same. The low pass filter 27 may remove high frequency portions of the frequency signal and leave useful low frequency portions of the frequency signal. The transmission circuit 22 is used to sequentially transmit the frequency signals.

For a detailed description of some circuit elements in this embodiment, such as the frequency signal generating circuit and the transmitting circuit, please refer to the description of the corresponding steps in the above method embodiment for the transmitter, which is not repeated herein.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a receiver according to a first embodiment of the present application.

The receiver includes a receiving circuit 31 and a bit value generating circuit 32. The receiving circuit 31 is used for receiving a plurality of frequency signals. The bit value generating circuit 32 is used for determining the frequency of each frequency signal and dividing a plurality of frequencies corresponding to a plurality of frequency signals into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

In this embodiment, for the explanation of the receiving circuit and the bit value generating circuit, reference may be made to the explanation of the corresponding position in the above embodiment, and details are not described here.

Referring to fig. 14, fig. 14 is a schematic structural diagram of a receiver according to a second embodiment of the present application.

The receiver includes a receiving circuit 41 and a bit value generating circuit 42, and unlike the first embodiment of the receiver, the receiver further includes a band pass filter 43, a first mixer 44, a low pass filter 45, an analog-to-digital conversion circuit 46, and a digital local oscillation circuit 47 in this embodiment.

The band-pass filter 43, the first mixer 44, the low-pass filter 45, and the analog-to-digital conversion circuit 46 are connected in this order between the reception circuit 41 and the bit value generation circuit 42. The band pass filter 43 is used to pass frequency signals of a specific frequency band while shielding frequency signals of other frequency bands. The first mixer 44 is used for mixing the received frequency signal with a local oscillator signal of the same frequency. The first mixer 44 is used to remove the carrier wave from the frequency signal. The low pass filter 45 may remove high frequency portions of the frequency signal and leave useful low frequency portions of the frequency signal. The analog-to-digital conversion circuit 46 may convert the analog signal to a digital signal, wherein the analog-to-digital conversion circuit 46 samples at a frequency greater than twice the maximum offset frequency.

The bit value generation circuit 42 includes a preset number of frequency detection circuits 421 and a logic processing and decoding circuit 422. Each frequency detection circuit 421 is used to detect one frequency. Frequency detection circuit 421 includes a second mixer 4211, a digital down-converter 4212, a correlator 4213, and a memory 4214. The second mixer 4211 is configured to mix the frequency signal with the first reference frequency signal generated by the digital local oscillator circuit 47 to obtain a mixed signal. Digital down converter 4212 is configured to down-convert the mixed signal to obtain a down-converted signal. The correlator 4213 is configured to perform correlation operation on the down-converted signal to obtain a correlation result between the frequency signal and the reference frequency signal. The memory 4214 is configured to determine a storage location of a correlation result of a frequency signal according to a reception order of the frequency signal, and store the correlation result according to the storage location, so that a correlation result sequence obtained by combining correlation results stored in different memories 4214 according to the storage locations thereof coincides with a reception order of the corresponding frequency signal. The logic processing and decoding circuit 422 is configured to divide the plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

Wherein the receiver inputs each frequency signal in parallel to a preset number (e.g., L) of frequency detection circuits 421 to determine the frequency of the frequency signal.

The logic processing and decoding circuit 422 is configured to determine, based on a mapping relationship between the frequency sequence and the bit value, a plurality of different sets of first reference frequency sequences corresponding to preset bit values for synchronization; comparing each group of first reference frequency sequences with a plurality of frequencies respectively to count the times of continuous occurrence of the corresponding first reference frequency sequences in the plurality of frequencies; and taking the first frequency reference sequence with the largest frequency as a current frequency sequence corresponding to the reference bit value, and dividing the frequencies remaining after the current frequency sequence continuously appears in the plurality of frequencies into at least one group of frequency sequences.

When the plurality of frequency signals are a plurality of frequency signals in a data slot, where the data slot includes a data synchronization segment and a data segment, and the data synchronization segment includes a plurality of data preset bit values for data access synchronization, the logic processing and decoding circuit 422 is configured to determine a plurality of different sets of first reference frequency sequences corresponding to the data preset bit values based on a first mapping relationship between the frequency sequences and the bit values of the data synchronization segment. The logic processing and decoding circuit 422 is further configured to generate corresponding bit values for each group of the frequency sequences based on a second mapping relationship between the frequency sequences and the bit values of the data segments to obtain information of the data segments in the data slots.

When the plurality of frequency signals are a plurality of frequency signals in a synchronization slot, where the synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field, the initial synchronization segment includes a plurality of synchronization preset bit values for initial access synchronization, and the synchronization segment includes a synchronization preset bit value for slot synchronization, the logic processing and decoding circuit 422 is configured to determine a plurality of different sets of first reference frequency sequences corresponding to the synchronization preset bit values based on a third mapping relationship between the frequency sequences and the bit values of the initial synchronization segment. The logic processing and decoding circuit 422 is further configured to determine a set of second reference frequency sequences corresponding to the synchronized preset bit values based on a fourth mapping relationship between the frequency sequences and the bit values of the synchronized segments; acquiring the remaining frequencies after the current frequency sequence appears continuously in the plurality of frequencies, and dividing the frequencies after the first reference frequency sequence in the remaining frequencies into at least one group of frequency sequences. The logic processing and decoding circuit 422 is further configured to generate corresponding bit values for each group of frequency sequences based on a fifth mapping relationship between the frequency sequences and the bit values of the information field to obtain information of the information field in the synchronization time slot. After the information in the information field is obtained, the logic processing and decoding circuit 422 is further configured to obtain the lower bit value of the first reference value from the information field, and update the current second reference value and the lower bit value to obtain the latest first reference value.

The second mapping relation is related to a current first reference value, and the first mapping relation, the third mapping relation, the fourth mapping relation and the fifth mapping relation are related to a current second reference value; the second reference value is a value composed of a plurality of high-order bit values in the first reference value. The logic processing and decoding circuit 422 is configured to obtain at least one adjacent reference value that differs from the current second reference value within a preset variation range, obtain different mapping relationships by using the current second reference value and each adjacent reference value, and determine different first reference frequency sequences corresponding to the reference bit values according to the different mapping relationships. And the logic processing and decoding circuit 422 is further configured to select a reference value corresponding to the current frequency sequence from the current second reference value and each adjacent reference value as the latest second reference value.

For specific descriptions of some circuit elements in this embodiment, such as the receiving circuit and the bit value generating circuit, please refer to the description of the corresponding steps in the above method embodiment for the receiver, which is not described herein again.

In an application example, a certain type of very high frequency communication system (VHF COMM) product is taken as an example for explanation: the working frequency band of the product is as follows: 30 MHz-88 MHz; jumping speed: FH equals 32000 Hop/s; frequency stepping: 25 KHz; number of frequencies: n-256; length of frequency sequence: l ═ 16; the baseband sampling rate fs is (88M-30M)/2 OSR 116Msps (OSR 4). The time t, L/FH, 16/32000s, 500us, 5 × 10 required for transmitting the frequency sequence^-4s, so that the time t can be multiplied by the speed of light C to obtain the frequency sequence at t × C5 × 10^-4s*3×10⁵And km/s is 150 km. The multipath signals within 150km can be filtered, so that the communication distance can be expanded, and the adaptability in a complex terrain environment is relatively strong.

The application also provides an implementation mode of the data transmission device. Specifically, the data transmission device comprises an acquisition module, a determination module and a sending module. The acquisition module is used for acquiring data to be transmitted; the determining module is used for determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value; the transmitting module is used for generating at least one corresponding frequency signal for the frequency sequence and sequentially transmitting the frequency signals.

In some embodiments, the frequencies in the frequency sequences corresponding to different bit values are different and/or the ordering of the frequencies is different.

In some embodiments, the determining module is specifically configured to: determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relation between the frequency sequence and the bit value; selecting at least one frequency respectively associated with at least one frequency index from a preset frequency set to form a frequency sequence; and/or the sending module, when generating the corresponding at least one frequency signal for the frequency sequence, is specifically configured to: and generating at least one corresponding frequency signal for the frequency sequence by using the digital local oscillator circuit.

In some embodiments, when the data to be transmitted comprises a data segment of a data slot; when the bit value is a bit value of the data segment, the determining module is specifically configured to: carrying out pseudo-random variable conversion on the first reference value, the bit value and the sum of the repetition times of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and resetting the repeated times of the step.

In some embodiments, when the data to be transmitted includes a data synchronization segment of a data slot, and/or the data to be transmitted further includes a synchronization slot, the synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field; when the bit value is a bit value in the data synchronization segment, the initial synchronization segment, or the information domain, the determining module is specifically configured to: carrying out pseudo-random variable conversion on the second reference value, the bit value and the sum of the repetition times of the step to obtain a second frequency index; repeatedly executing the step until a preset number of second frequency indexes are obtained, and resetting the repetition times of the step; if the bit value is the bit value of the synchronous segment, performing pseudo-random variable conversion on the second reference value, the synchronous preset bit value, the preset parameter and the sum of the repetition times of the step to obtain a third frequency index; and repeating the step until a preset number of third frequency indexes are obtained, and resetting the repetition times of the step.

In some embodiments, the first reference value is a frequency signal hop count accumulated for the current system time; the second reference value is a value formed by a plurality of high-order bit values in the first reference value; the information field comprises transmission parameters and/or low bit values except a plurality of high bit values in the first reference value; the data synchronization segment comprises a plurality of data preset bit values, the initial synchronization segment comprises a plurality of synchronous preset bit values, the synchronization segment comprises a synchronous preset bit value, and the synchronous preset bit value and the data preset bit value are different bit values.

The present application also provides another embodiment of a data transmission device. Specifically, the data transmission device comprises a receiving module, a determining module and a generating module. The receiving module is used for receiving a plurality of frequency signals. The determining module is used for determining the frequency of each frequency signal and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; the generating module is used for generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values so as to obtain the transmitted data.

In some embodiments, the determining module is specifically configured to: determining a plurality of different groups of first reference frequency sequences corresponding to preset bit values for synchronization based on a mapping relation between the frequency sequences and the bit values; comparing each group of first reference frequency sequences with a plurality of frequencies respectively to count the times of continuous occurrence of the corresponding first reference frequency sequences in the plurality of frequencies; and taking the first frequency reference sequence with the largest frequency as a current frequency sequence corresponding to a preset bit value, and dividing the residual frequencies after the current frequency sequence continuously appears in a plurality of frequencies into at least one group of frequency sequences.

In some embodiments, if the plurality of frequency signals are a plurality of frequency signals in a data slot, where the data slot includes a data synchronization segment and a data segment, and the data synchronization segment includes a plurality of data preset bit values for data access synchronization, the determining module is specifically configured to: determining a plurality of different groups of first reference frequency sequences corresponding to the preset bit values of the data based on a first mapping relation between the frequency sequences and the bit values of the data synchronization segment; generating corresponding bit values for each group of frequency sequences based on a second mapping relation between the frequency sequences and the bit values of the data segments to obtain information of the data segments in the data time slots; when the plurality of frequency signals are a plurality of frequency signals in a synchronization slot, where the synchronization slot includes an initial synchronization segment, a synchronization segment, and an information field, the initial synchronization segment includes a plurality of synchronization preset bit values for initial access synchronization, and the synchronization segment includes one synchronization preset bit value for slot synchronization, the determining module is specifically configured to: determining a plurality of different groups of first reference frequency sequences corresponding to the synchronous preset bit values based on a third mapping relation between the frequency sequences and the bit values of the initial synchronous segment; determining a group of second reference frequency sequences corresponding to the synchronous preset bit values based on a fourth mapping relation between the frequency sequences and the bit values of the synchronous segments; acquiring the residual frequencies after the current frequency sequence continuously appears in the multiple frequencies, and dividing the frequencies behind the first reference frequency sequence in the residual frequencies into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on a fifth mapping relation between the frequency sequences and the bit values of the information domain to obtain the information of the information domain in the synchronous time slot.

In some embodiments, the second mapping relationship is associated with a current first reference value, and the first mapping relationship, the third mapping relationship, the fourth mapping relationship, and the fifth mapping relationship are associated with a current second reference value; the second reference value is a value formed by a plurality of high-order bit values in the first reference value; the determination module is specifically configured to: acquiring at least one adjacent reference value with the difference with the current second reference value within a preset variation range, respectively obtaining different mapping relations by using the current second reference value and each adjacent reference value, and respectively determining different first reference frequency sequences corresponding to preset bit values according to the different mapping relations; the determination module is specifically configured to: before dividing the remaining frequencies after the current frequency sequence appears continuously in the plurality of frequencies into at least one group of frequency sequences, selecting a reference value corresponding to the current frequency sequence from the current second reference value and each adjacent reference value as a latest second reference value; and after generating corresponding bit values for each group of frequency sequences based on a fifth mapping relationship between the frequency sequences and the bit values of the information fields to obtain information of the information fields in the synchronization time slot, the determining module is specifically configured to: acquiring a low bit value in the first reference value from the information domain; and updating to obtain the latest first reference value by using the current second reference value and the low bit value.

In some embodiments, the determining module is specifically configured to: each frequency signal is input in parallel to a preset number of frequency detection circuits for determining the frequency of the frequency signal, wherein each frequency detection circuit is used for detecting one frequency.

Referring to fig. 15, fig. 15 is a schematic structural diagram of an embodiment of a device with a storage function according to the present application. The data transmission apparatus 500 stores instructions 501, and when executed, the instructions 501 implement the method in any of the embodiments described above.

The apparatus 500 with a storage function may be a medium that can store program instructions, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, or may be a server that stores the program instructions, and the server may send the stored program instructions to other devices for operation, or may self-operate the stored program instructions.

The following goes on to list the beneficial effects produced by the above scheme in detail:

(1) bit values in data to be transmitted are mapped onto a frequency sequence, symbols in digital communication in the traditional sense are not available, so that inter-symbol interference is avoided, meanwhile, due to the fact that no symbols are available, a processing link of matched filtering is not available, all filters can use Cascade Integrator Comb (CIC) filters, the filters can be realized only by an adder, a multiplier is not needed, complexity and power consumption of realization are reduced, and requirements on processing capacity of a chip are also reduced;

(2) the high-speed frequency hopping of continuous carrier phases is adopted, the hopping period Th is far smaller than the multipath time delay expansion of signals, so that the frequency is not repeated in one bit value transmission period, and because the signal frequency rapidly hops, the influence of multipath signals can be eliminated through a radio frequency tuning filter, an intermediate frequency filter and a digital baseband filter, thereby avoiding complex channel equalization processing, improving the frequency spectrum utilization rate and reducing the cost and the power consumption of products;

(3) in the frequency hopping process, the frequency of a local oscillator signal is kept unchanged, the phase is continuous, the signal is not modulated in each hop in the traditional sense, the instantaneous bandwidth is close to 0, each channel can be allocated with a bandwidth which is narrower than the bandwidth applied in the prior art, the channel capacity is favorably improved, and in the prior art, in order to improve the hop count, the dual phase-locked loops are generally operated alternately;

(4) the bit values in the data to be transmitted are mapped onto the frequency sequence, the contradiction between high jump speed and spectral efficiency can be well solved, the adaptability and the communication distance of the product in a complex terrain environment can be improved by transforming the existing product by using the waveform, and the communication distance can be effectively improved under the condition of increasing power in a new product;

(5) the hop count is controlled by the control number, the reaction time is extremely short, so that a higher hop rate, such as 32000 hops/second, can be achieved, and the hop rate is far higher than that of the existing product (for example, generally 1000 hops/second in China), so that the existing communication jammers cannot perform tracking interference on the existing communication jammers, and the method is significant in the field of military communication.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims

1. A method of data transmission, comprising:

acquiring data to be transmitted;

determining a corresponding frequency sequence for each bit value in the data to be transmitted, wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value;

and generating at least one corresponding frequency signal for the frequency sequence, and sequentially transmitting the frequency signals.

2. The method of claim 1, wherein the frequencies in the frequency sequences corresponding to different bit values are different and/or the ordering of the frequencies is different.

3. The method according to claim 1 or 2, wherein the determining a corresponding frequency sequence for each bit value in the data to be transmitted comprises:

determining at least one frequency index in a frequency sequence corresponding to a bit value according to a mapping relation between the frequency sequence and the bit value;

selecting at least one frequency respectively associated with the at least one frequency index from a preset frequency set to compose the frequency sequence; and/or the presence of a gas in the gas,

the generating of the corresponding at least one frequency signal for the frequency sequence comprises:

and generating at least one corresponding frequency signal for the frequency sequence by using a digital local oscillator circuit.

4. The method of claim 3, wherein the data to be transmitted comprises a data segment of a data slot; determining at least one frequency index in the frequency sequence corresponding to the bit value according to the mapping relationship between the frequency sequence and the bit value, including:

if the bit value is the bit value of the data segment, performing pseudo-random variable conversion on the first reference value, the bit value and the sum of the repetition times of the step to obtain a first frequency index; and repeatedly executing the step until a preset number of first frequency indexes are obtained, and resetting the repeated times of the step.

5. The method according to claim 4, wherein the data to be transmitted comprises a data sync segment of a data slot, and/or the data to be transmitted further comprises a sync slot, wherein the sync slot comprises an initial sync segment, a sync segment and an information field;

determining at least one first frequency index corresponding to a bit value according to a mapping relationship between a frequency sequence and the bit value, including:

if the bit value is the bit value in the data synchronization segment, the initial synchronization segment or the information domain, performing pseudo-random variable conversion on a second reference value, the bit value and the sum of the repetition times of the step to obtain a second frequency index; repeatedly executing the step until the second frequency indexes with the preset number are obtained, and resetting the repeated times of the step;

if the bit value is the bit value of the synchronous segment, performing pseudo-random variable conversion on the second reference value, the synchronous preset bit value, the preset parameter and the sum of the repetition times of the step to obtain a third frequency index; and repeatedly executing the step until the preset number of third frequency indexes are obtained, and resetting the repeated times of the step.

6. The method of claim 5, wherein the first reference value is a frequency signal hop count accumulated for a current system time;

the second reference value is a value formed by a plurality of high-order bit values in the first reference value;

the information field comprises transmission parameters and/or low bit values except the high bit values in the first reference value;

the data synchronization segment comprises a plurality of data preset bit values, the initial synchronization segment comprises a plurality of synchronization preset bit values, the synchronization segment comprises one synchronization preset bit value, and the synchronization preset bit value and the data preset bit value are different bit values.

7. A method of data transmission, comprising:

receiving a plurality of frequency signals;

determining the frequency of each frequency signal, and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences;

and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

8. The method of claim 7,

the dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences comprises:

determining a plurality of different groups of first reference frequency sequences corresponding to preset bit values for synchronization based on the mapping relation between the frequency sequences and the bit values;

comparing each group of the first reference frequency sequences with the plurality of frequencies respectively to count the times of continuous occurrence of the corresponding first reference frequency sequences in the plurality of frequencies;

and taking the first frequency reference sequence with the largest frequency as the current frequency sequence corresponding to the preset bit value, and dividing the residual frequencies after the current frequency sequence appears continuously in the multiple frequencies into at least one group of frequency sequences.

9. The method of claim 8, wherein if the plurality of frequency signals are a plurality of frequency signals in a data slot, wherein the data slot comprises a data sync segment and a data segment, the data sync segment comprises a plurality of data preset bit values for data access synchronization; the determining, based on the mapping relationship between the frequency sequence and the bit value, a plurality of different sets of first reference frequency sequences corresponding to preset bit values for synchronization includes:

determining a plurality of different groups of first reference frequency sequences corresponding to preset bit values of data based on a first mapping relation between the frequency sequences and the bit values of the data synchronization segment;

generating a corresponding bit value for each group of the frequency sequence based on the mapping relationship between the frequency sequence and the bit value to obtain the transmitted data, including:

generating corresponding bit values for each group of the frequency sequences based on a second mapping relation between the frequency sequences and the bit values of the data segments to obtain information of the data segments in the data time slots;

if the plurality of frequency signals are a plurality of frequency signals in a synchronization time slot, wherein the synchronization time slot comprises an initial synchronization segment, a synchronization segment and an information field, the initial synchronization segment comprises a plurality of synchronization preset bit values for initial access synchronization, and the synchronization segment comprises a synchronization preset bit value for time slot synchronization; the determining, based on the mapping relationship between the frequency sequence and the bit value, a plurality of different sets of first reference frequency sequences corresponding to preset bit values for synchronization includes:

determining a plurality of different groups of first reference frequency sequences corresponding to synchronous preset bit values based on a third mapping relation between the frequency sequences and the bit values of the initial synchronous segment;

the dividing frequencies remaining after the current frequency sequence occurs consecutively in the plurality of frequencies into at least one group of frequency sequences includes:

determining a group of second reference frequency sequences corresponding to the synchronous preset bit values based on a fourth mapping relation between the frequency sequences and the bit values of the synchronous segments;

acquiring the residual frequencies after the current frequency sequence continuously appears in the multiple frequencies, and dividing the frequencies behind the first reference frequency sequence in the residual frequencies into at least one group of frequency sequences;

and generating corresponding bit values for each group of the frequency sequences based on a fifth mapping relation between the frequency sequences and the bit values of the information domain to obtain the information of the information domain in the synchronous time slot.

10. The method of claim 9, wherein the second mapping relationship is associated with a current first reference value, and the first mapping relationship, the third mapping relationship, the fourth mapping relationship, and the fifth mapping relationship are associated with a current second reference value; the second reference value is a value formed by a plurality of high-order bit values in the first reference value;

determining a plurality of different groups of first reference frequency sequences corresponding to preset bit values for synchronization according to the mapping relationship between the frequency sequences and the bit values, including:

acquiring at least one adjacent reference value with the difference with the current second reference value within a preset variation range, respectively obtaining different mapping relations by using the current second reference value and each adjacent reference value, and respectively determining different first reference frequency sequences corresponding to the preset bit values according to the different mapping relations;

before the dividing frequencies remaining after the current sequence of frequencies occurs consecutively in the plurality of frequencies into at least one set of sequences of frequencies, the method further comprises:

selecting a reference value corresponding to the current frequency sequence from the current second reference value and each adjacent reference value as a latest second reference value;

after the generating, based on the fifth mapping relationship between the frequency sequences and the bit values of the information field, corresponding bit values for each group of the frequency sequences to obtain information of the information field in the synchronization slot, the method further includes:

acquiring a low bit value in the first reference value from the information domain;

and updating to obtain the latest first reference value by using the current second reference value and the low bit value.

11. The method of claim 7, wherein said determining the frequency of each of said frequency signals comprises:

and inputting each frequency signal into a preset number of frequency detection circuits in parallel to determine the frequency of the frequency signal, wherein each frequency detection circuit is used for detecting one frequency.

12. A transmitter, comprising:

the frequency signal generating circuit is used for determining a corresponding frequency sequence for each bit value in the data to be transmitted; generating a corresponding at least one frequency signal for the sequence of frequencies; wherein the frequency sequence comprises at least one frequency, and the frequency sequence is used for mapping the corresponding bit value;

and the transmitting circuit is used for sequentially transmitting the frequency signals.

13. The transmitter of claim 12, further comprising a digital-to-analog conversion circuit, an up-converter, a band-pass filter bank, a mixer and a low-pass filter sequentially connected between the frequency signal generating circuit and the transmitting circuit, wherein the mixer is configured to mix each frequency signal output by the band-pass filter bank with a local oscillator signal, and the local oscillator signal mixed with each frequency signal has the same frequency; and/or the presence of a gas in the gas,

the frequency signal generation circuit includes:

the pseudo-random sequence generator is used for carrying out pseudo-random variable conversion based on the bit value to obtain at least one frequency index in a frequency sequence corresponding to the bit value;

and the digital local oscillator circuit is used for selecting at least one frequency respectively associated with the at least one frequency index from a preset frequency set to form the frequency sequence and generate at least one corresponding frequency signal for the frequency sequence.

14. A receiver, comprising:

a receiving circuit for receiving a plurality of frequency signals;

the bit value generating circuit is used for determining the frequency of each frequency signal and dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

15. The receiver of claim 14, further comprising a band pass filter, a first mixer, a low pass filter, and an analog-to-digital conversion circuit sequentially connected between the receiving circuit and the bit value generating circuit, wherein the first mixer is configured to mix a received frequency signal with a local oscillator signal of the same frequency; and/or the presence of a gas in the gas,

the bit value generation circuit includes:

a preset number of frequency detection circuits, wherein each frequency detection circuit is used for detecting one frequency;

logic processing and decoding circuit for dividing a plurality of frequencies corresponding to the plurality of frequency signals into at least one group of frequency sequences; and generating corresponding bit values for each group of frequency sequences based on the mapping relation between the frequency sequences and the bit values to obtain the transmitted data.

16. The receiver of claim 15, further comprising a digital local oscillator circuit; the frequency detection circuit includes:

the second frequency mixer is used for mixing the frequency signal with a first reference frequency signal generated by the digital local oscillator circuit to obtain a mixed frequency signal;

the digital down converter is used for carrying out down conversion on the mixing signal to obtain a down conversion signal;

the correlator is used for carrying out correlation operation on the down-conversion signal to obtain a correlation result between the frequency signal and the reference frequency signal;

and the memory is used for determining the storage position of the correlation result of the frequency signal according to the receiving sequence of the frequency signal and storing the correlation result according to the storage position, so that a correlation result sequence obtained by combining the correlation results stored by different memories according to the storage positions is consistent with the receiving sequence corresponding to the frequency signal.