CN114337697B - Multipath baseband signal synthesis method and system - Google Patents
Multipath baseband signal synthesis method and system Download PDFInfo
- Publication number
- CN114337697B CN114337697B CN202210008244.9A CN202210008244A CN114337697B CN 114337697 B CN114337697 B CN 114337697B CN 202210008244 A CN202210008244 A CN 202210008244A CN 114337697 B CN114337697 B CN 114337697B
- Authority
- CN
- China
- Prior art keywords
- signal
- stage
- signals
- sampling rate
- baseband
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The application relates to a multi-path baseband signal synthesis method and a system, which are used for solving the problem of high consumption of synthesis resources of the existing multi-path baseband signal. The method comprises the following steps: acquiring multi-path baseband signal data; determining the stage number of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signals and the grouping number of each stage of signals according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the number of paths of baseband signals; from the first stage to the last stage, interpolation filtering is carried out on the signals of the stage according to the interpolation multiple corresponding to each stage, and the signals after the stage interpolation are grouped and synthesized according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage; the signal output by the last stage is the synthesized signal.
Description
Technical Field
The present application relates to the field of signal synthesis technologies, and in particular, to a method and a system for synthesizing a multipath baseband signal.
Background
At present, the field of software radio often relates to a scene that multiple baseband signals are synthesized into one signal for up-conversion and finally transmitted through DA, and the characteristic of FPGA multiple parallel channels can play a great advantage under the scene, so that the synthesis time can be greatly shortened, and the transmission time sequence can be accurately controlled. However, when the number of baseband signals is too large, the conventional method for independently interpolating, filtering, frequency shifting and synthesizing multiple paths of signals is limited by the resources in the FPGA, so that time sequence violations and even wiring failures can be caused by a large amount of resources, more FPGA chips with resources are needed or the number of baseband signals is reduced, and the cost is increased or the number of supported baseband signals is too small.
Take the example of up-conversion of 80 paths of 1M baseband signals to 1 path of 375M sample rate signals: the 80-channel baseband signal is up-converted to 375M sampling rate through 375 times interpolation filtering, then the frequency shift of DDS is randomly distributed in a 187.5M frequency range, so that 80 375 times interpolation filters are needed, the interpolation filters with large multiples consume DSP resources very, and meanwhile, the 1-channel signal synthesized after 80-channel frequency shift consumes wiring resources very much. The result is that the baseband signal which can be supported is very limited under the condition that the FPGA chip is unchanged, and the requirement of 80 paths is far less than.
Disclosure of Invention
In view of the above analysis, the present application aims to provide a method and a system for synthesizing multiple baseband signals, which are used for solving the problem of large consumption of synthesis resources of the existing multiple baseband signals.
In one aspect, an embodiment of the present application provides a method for synthesizing a multipath baseband signal, including the following steps:
acquiring multi-path baseband signal data;
determining the stage number of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signals and the grouping number of each stage of signals according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the number of paths of baseband signals;
from the first stage to the last stage, interpolation filtering is carried out on the signals of the stage according to the interpolation multiple corresponding to each stage, and the signals after the stage interpolation are grouped and synthesized according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage;
the signal output by the last stage is the synthesized signal.
The beneficial effects of the technical scheme are as follows: the multi-path baseband signals are synthesized in a hierarchical grouping mode, the number of paths synthesized at one time is greatly reduced, so that the pressure on time sequence and wiring is reduced, and the signals are interpolated in a hierarchical mode, so that the multiple of an interpolation filter is reduced, and the consumption of resources is greatly reduced.
Based on the further improvement of the method, determining the stage number of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage signal and the packet number of each stage signal according to the ratio of the target sampling rate and the initial sampling rate of the multipath baseband signals and the number of paths of the baseband signals comprises:
determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the factor of the ratio; wherein the product of the interpolation multiples of the sampling rate of each stage of signal is the same as the ratio of the target sampling rate to the initial sampling rate; and determining the grouping number of each stage of signals according to the stage number of the hierarchical synthesis and the path number of the baseband signals.
The beneficial effects of the technical scheme are as follows: the hierarchical level number can be quickly determined by determining the hierarchical synthesized level number, the sampling rate interpolation multiple of each level signal and the grouping number of each level signal according to the ratio of the target sampling rate to the initial sampling rate, and the method is simple and convenient to implement.
Further, according to the number of packets of the signal corresponding to the stage, the signals after the stage interpolation are combined, including:
according to the sampling rate of the interpolated signals, frequency shifting is carried out on the signals in each group;
and synthesizing the signals after the frequency shifting in each packet into one path of signals.
The beneficial effects of the technical scheme are as follows: the signals in each group are subjected to frequency shift synthesis, so that the number of paths of one-time synthesis is reduced, and the occupation of resources is reduced.
Further, frequency shifting the signals in each packet according to the sample rate of the interpolated signals, including:
determining a frequency shift value of each path of signal in each packet according to the sampling rate of the interpolated signal;
and calculating a phase control word according to the frequency shift value of each signal in each packet, controlling the output signal of the IP core according to the phase control word, and multiplying the output signal of the IP core with the signal to obtain a frequency shifted signal.
Further, determining a frequency shift value of each signal in each packet according to the sample rate of the interpolated signal, including:
and for each group, uniformly distributing the frequency shift value of each signal in a frequency band range corresponding to the sampling rate of the interpolated signal according to the sampling rate of the interpolated signal and the number of signal paths in the group.
The beneficial effects of the technical scheme are as follows: the frequency shift value of each signal is determined according to the sampling rate of the interpolated signal, and the frequency shift value of each signal is uniformly distributed in the corresponding frequency band range, so that the frequency shifted signals are not aliased, and the receiving end can be conveniently decomposed. The phase control word is adopted to control the IP core to output corresponding output signals to shift the frequency of the signals, and the method is simple and convenient to implement.
Further, for each signal, calculating a phase control word according to the frequency shift value of the signal, including: the value of the Phase control word Phase _ in is calculated according to the following formula:
according to the formula |fout|2 θ Calculating the numerical value corresponding to the 0 th to theta-1 th bits of the phase_in of the Phase control word;
when Fout is more than or equal to 0, the highest bit phase_in [ theta-1 ] =0 of the Phase control word; when Fout <0, the highest bit phase_in [ theta-1 ] =1 of the Phase control word,
where θ is the bit width of the phase control word, fout is the shift value, and Fs is the system clock frequency.
The beneficial effects of the technical scheme are as follows: the positive and negative of the shift frequency value are represented by the highest bit of the phase control word, so that the signal can be conveniently shifted to the negative frequency, and the shift frequency distribution of the signal in the packet is convenient.
On the other hand, the embodiment of the application provides a multi-path baseband signal synthesis system, which comprises the following modules:
the baseband signal acquisition module is used for acquiring multiple paths of baseband signal data;
the hierarchical grouping determining module is used for determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the number of paths of baseband signals;
the grouping and synthesizing module is used for sequentially carrying out interpolation filtering on the signals of each stage from the first stage to the last stage according to the interpolation multiple corresponding to each stage, and grouping and synthesizing the signals after the stage interpolation according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage;
and the signal transmitting module is used for transmitting the synthesized signal output by the last stage.
Further, the hierarchical grouping determination module is used for determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the factor of the ratio; wherein the product of the interpolation multiples of the sampling rate of each stage of signal is the same as the ratio of the target sampling rate to the initial sampling rate; the hierarchical packet determining module is further configured to determine the packet number of each level of signal according to the number of levels of hierarchical synthesis and the number of paths of the baseband signal.
Further, the packet synthesis module is configured to group and synthesize the signals after the interpolation of the stage according to the number of packets of the signals corresponding to the stage, and includes:
according to the sampling rate of the interpolated signals, frequency shifting is carried out on the signals in each group;
and synthesizing the signals after the frequency shifting in each packet into one path of signals.
Further, the packet synthesis module is configured to shift the frequency of the signal in each packet according to the sampling rate of the interpolated signal, and includes:
determining a frequency shift value of each path of signal in each packet according to the sampling rate of the interpolated signal;
and calculating a phase control word according to the frequency shift value of each signal in each packet, controlling the output signal of the IP core according to the phase control word, and multiplying the output signal of the IP core with the signal to obtain a frequency shifted signal.
In the application, the technical schemes can be mutually combined to realize more preferable combination schemes. Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the application, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a flow chart of a method for synthesizing multipath baseband signals according to an embodiment of the present application;
fig. 2 is a block diagram of a multi-path baseband signal synthesis system according to an embodiment of the present application.
Detailed Description
The following detailed description of preferred embodiments of the application is made in connection with the accompanying drawings, which form a part hereof, and together with the description of the embodiments of the application, are used to explain the principles of the application and are not intended to limit the scope of the application.
At present, the field of software radio often relates to a scene that multiple baseband signals are synthesized into one signal for up-conversion and finally transmitted through DA, and the characteristic of FPGA multiple parallel channels can play a great advantage under the scene, so that the synthesis time can be greatly shortened, and the transmission time sequence can be accurately controlled. However, when the number of baseband signals is too large, the conventional method for independently interpolating, filtering, frequency shifting and synthesizing multiple paths of signals is limited by the resources in the FPGA, so that time sequence violations and even wiring failures can be caused by a large amount of resources, more FPGA chips with resources are needed or the number of baseband signals is reduced, and the cost is increased or the number of supported baseband signals is too small.
Taking the example of up-conversion of the 80-channel 1M sample rate baseband signal to the 1-channel 375M sample rate signal: the 80-channel baseband signal is up-converted to 375M sampling rate through 375 times interpolation filtering, and then is randomly distributed in a 187.5M frequency range through DDS frequency shift, so that 80 375 times interpolation filters are needed, the interpolation filters with large multiples consume DSP resources very, and meanwhile, the 1-channel signal synthesized after 80-channel frequency shift consumes wiring resources very much. The result is that the baseband signal which can be supported is very limited under the condition that the FPGA chip is unchanged, and the requirement of 80 paths is far less than.
In view of this, in one embodiment of the present application, a method for synthesizing a multipath baseband signal is disclosed, as shown in fig. 1. The method comprises the following steps:
s1, acquiring multi-path baseband signal data;
s2, determining the stage number of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signal and the number of paths of baseband signals;
s3, from the first stage to the last stage, sequentially carrying out interpolation filtering on signals of each stage according to interpolation multiples corresponding to each stage, and grouping and synthesizing the signals after the stage interpolation according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage;
s4, the signal output by the last stage is the synthesized signal.
By adopting the hierarchical grouping mode to carry out synthesis processing on the multipath baseband signals, the number of paths synthesized at one time is greatly reduced, thereby reducing the pressure on time sequence and wiring. Meanwhile, signals are interpolated in a hierarchical mode, so that the multiple of an interpolation filter is reduced, and the consumption of resources is greatly reduced.
Specifically, the multi-path baseband data can be sent by an upper computer, the upper computer writes the multi-path baseband signals to be synthesized into the DDR according to the appointed address, and writes the number of the baseband signals and the signal sampling rate into a register of the FPGA. After receiving a start enabling signal sent by the upper computer, the FPGA reads multiple paths of baseband signals in parallel from the DDR according to the sampling rate of the baseband signals and the reading speed corresponding to the sampling rate, so that multiple paths of baseband signals are obtained. For example, the baseband signal to be synthesized is 80 paths, when the sampling rate of the baseband signal is 1M, the 80 paths of baseband signals are read in parallel at a speed of reading 1M data points per second, and when the sampling rate of the baseband signal is 5M, the 80 paths of baseband signals are read in parallel at a speed of reading 5M data points per second.
After obtaining the channel number and sampling rate information of the baseband signals to be synthesized, determining the stage number of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signals and the grouping number of each stage of signals according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the channel number of the baseband signals.
Specifically, determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the factor of the ratio; wherein the product of the interpolation multiples of the sampling rate of each stage of signal is the same as the ratio of the target sampling rate to the initial sampling rate; and determining the grouping number of each stage of signals according to the stage number of the hierarchical synthesis and the path number of the baseband signals.
For example, the baseband signal has a sampling rate of 1M, i.e., an initial sampling rate of 1M, a target sampling rate of 375M, and a ratio of the target sampling rate to the initial sampling rate of 375. The number of stages of the hierarchical composition is determined based on a factor of 375, for example 375=5×5×15, the number of stages is determined to be 3 stages, the interpolation multiple of the first stage is 5, the interpolation multiple of the second stage is 5, and the interpolation multiple of the third stage is 15.
And determining the grouping number of each stage of signals according to the stage number of the hierarchical synthesis and the path number of the baseband signals. For example, the baseband signal is 80 paths, the number of stages of hierarchical synthesis is 3, the number of packets of the first-stage signal may be 16, that is, the 80-path baseband signal is synthesized into 16 paths of signals, the number of packets of the second-stage signal may be 4, that is, the synthesized 16 paths of signals are further synthesized into 4 paths of signals, the number of packets of the third-stage signal is 1, that is, the 4 paths of signals of the previous stage are synthesized into 1 path.
After determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signals and the grouping number of each stage of signals, sequentially carrying out interpolation filtering on the signals of each stage from the first stage to the last stage according to the interpolation multiple corresponding to each stage, and grouping and synthesizing the signals after the stage interpolation according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage.
For example, the interpolation multiple of the first stage is 5, then 5 times interpolation is performed on the 80 paths of 1M baseband signals, for example, 5 times interpolation filter is used for interpolation filtering, and 80 5 times interpolation filters are needed.
After interpolation is carried out on the signals, the signals after interpolation of the stage are grouped and synthesized according to the grouping number of the signals corresponding to the stage. For example, if the number of packets of the first-stage signal is 16, the continuous 5-path signal may be used as one packet, and the signals in each packet may be synthesized, that is, synthesized into one-path signal in the frequency domain.
Specifically, according to the number of packets of the signal corresponding to the stage, the signals after the stage interpolation are grouped and combined, including:
according to the sampling rate of the interpolated signals, frequency shifting is carried out on the signals in each group;
and synthesizing the signals after the frequency shifting in each packet into one path of signals.
Specifically, according to the sample rate of the interpolated signal, frequency shifting the signal in each packet includes:
determining a frequency shift value of each path of signal in each packet according to the sampling rate of the interpolated signal;
and calculating a phase control word according to the frequency shift value of each signal in each packet, controlling the output signal of the IP core according to the phase control word, and multiplying the output signal of the IP core with the signal to obtain a frequency shifted signal.
In order to ensure that aliasing does not occur in the frequency-shifted signal, determining a frequency-shifted value of each signal in each packet according to the sampling rate of the interpolated signal includes:
and for each group, uniformly distributing the frequency shift value of each path of signal in a frequency band range corresponding to the sampling rate of the interpolated signal according to the sampling rate of the interpolated signal and the number of signal paths in the group.
For example, after the 80 paths of 1M baseband signals are interpolated according to the interpolation multiple 5 of the first stage, the sampling rate of the signals is 5M, and the range of the signal frequency which can be distributed is-2.5M to +2.5m according to the nyquist sampling law. For example, the number of packets of the first-stage signal is 16, each packet has 5 signals, and for each packet, the frequency shift values of the 5 signals are uniformly distributed between-2.5M and +2.5M, for example, the frequency shift values of the 5 signals in each packet can be-2M, -1M, 0M, 1M and 2M respectively.
After the frequency shift value is obtained, a digital frequency oscillator based on an IP core can be used for frequency shift of the interpolated signal.
The digital oscillator controls the frequency of the output signal by a phase control word. For each signal, the value of the Phase control word phase_in is calculated according to the following formula:
according to the formula |fout|2 θ Calculating the numerical value corresponding to the 0 th to theta-1 th bits of the phase_in of the Phase control word;
when Fout is more than or equal to 0, the highest bit phase_in [ theta-1 ] =0 of the Phase control word; when Fout <0, the highest bit phase_in [ theta-1 ] =1 of the Phase control word,
where θ is the bit width of the phase control word, e.g., 32 bits, fout is the shift value, and Fs is the system clock frequency.
According to the formula |fout|2 θ The value calculated by/Fs is a decimal number, and the value converted into hexadecimal is stored in bits 0 to theta-1 corresponding to the phase control word. If the shift value is positive, the highest bit of the phase control word is 0, i.e., the θ -1 bit is 0, and if the shift value is negative, the highest bit of the phase control word is 0, i.e., the θ -1 bit is 1.
The IP core outputs a corresponding signal according to the phase control word, and multiplies the output signal of the IP core with the signal to be frequency shifted to obtain a signal after frequency shifting.
And synthesizing the signals after the frequency shifting in each packet into one path of signals, thereby obtaining 16 paths of synthesized signals. The obtained 16-channel synthesized signal is used as an input signal of the next stage, and the same processing is continued. For example, if the interpolation multiple of the sampling rate of the second-stage signal is 5 and the number of packets is 4, the 16 paths of 5M signals are subjected to 5-time sampling rate interpolation to obtain 16 paths of signals with 25M sampling rates, and at this time, the frequency distributable range of the signals is-12.5M to +12.5M, and the number of signal paths in each packet is 4, so that the frequency shift values of the 4 paths of signals in each packet can be-10M, -5M, 0M and 5M respectively, and the signals in each packet are frequency-shifted and synthesized into one path of signals.
The second stage synthesis is carried out to obtain 4 paths of signals, the obtained 4 paths of synthesized signals are used as input signals of a third stage, the interpolation multiple of the sampling rate of the signals of the third stage is 15, the number of groups is 1, then 15 times of interpolation is carried out on the signals of the sampling rate of 4 paths of 25M to obtain signals of the sampling rate of 4 paths of 375M, the frequency distributable range of the signals is-187.5M to +187.5M, the number of the signals in the groups is 4, the frequency shift values of the 4 paths of signals in the groups can be 25M, 50M, 75M and 100M respectively, and the signals in the groups are frequency-shifted and synthesized to form a path of signal to obtain the final synthesized signal.
In practice, the final frequency of each signal should be positive, so the sum of the minimum shift values of each stage of the composite signal should be greater than zero. For example, the minimum value of the shift frequency value of the first-stage synthesized signal is-2, the minimum shift frequency value of the second-stage synthesized signal is-10, and the minimum shift frequency value of the third-stage synthesized signal is 25, which is the sum of 13.
For the signal with the sampling rate of 80 paths of 1M in the example, only 80+16 interpolation filters of 5 times and 4 interpolation filters of 15 times are needed in a grouping synthesis mode, so that the use of resources is greatly reduced. Meanwhile, the number of synthesized paths is changed from 80 paths to 5 paths at most, so that each baseband signal can be moved to different frequencies while the number of synthesized paths is reduced, and the time sequence and wiring pressure are reduced.
The frequency points of the synthesized 80 paths of signals are shown in the table 1, and the frequency points of each path of signals are different, so that aliasing can not occur, and the quality of the synthesized signals is ensured. The synthesized signal can be temporarily stored in a designated DDR address, and after the synthesized signal is received, the synthesized signal is sent to a digital-to-analog conversion chip, such as an AD9176 chip, to perform digital-to-analog conversion, and finally is transmitted out through a radio frequency port.
TABLE 1 Signal frequency Point Table
| Road number | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| Frequency point | 13M | 14M | 15M | 16M | 17M | 18M | 19M | 20M | 21M | 22M |
| Road number | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
| Frequency point | 23M | 24M | 25M | 26M | 27M | 28M | 29M | 30M | 31M | 32M |
| Road number | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 |
| Frequency point | 38M | 39M | 40M | 41M | 42M | 43M | 44M | 45M | 46M | 47M |
| Road number | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
| Frequency point | 48M | 49M | 50M | 51M | 52M | 53M | 54M | 55M | 56M | 57M |
| Road number | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 |
| Frequency point | 63M | 64M | 65M | 66M | 67M | 68M | 69M | 70M | 71M | 72M |
| Road number | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 |
| Frequency point | 73M | 74M | 75M | 76M | 77M | 78M | 79M | 80M | 81M | 82M |
| Road number | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 |
| Frequency point | 88M | 89M | 90M | 91M | 92M | 93M | 94M | 95M | 96M | 97M |
| Road number | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 |
| Frequency point | 98M | 99M | 100M | 101M | 102M | 103M | 104M | 105M | 106M | 107M |
In one embodiment of the present application, a multi-path baseband signal synthesis system is disclosed, as shown in fig. 2, the system includes the following modules:
the baseband signal acquisition module is used for acquiring multiple paths of baseband signal data;
the hierarchical grouping determining module is used for determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the number of paths of baseband signals;
the grouping and synthesizing module is used for sequentially carrying out interpolation filtering on the signals of each stage from the first stage to the last stage according to the interpolation multiple corresponding to each stage, and grouping and synthesizing the signals after the stage interpolation according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage;
and the signal transmitting module is used for transmitting the synthesized signal output by the last stage.
Preferably, the hierarchical grouping determining module is configured to determine, according to the factor of the ratio, the number of stages of hierarchical synthesis, an interpolation multiple of the sampling rate of each stage of signal, and the number of groups of each stage of signal; wherein the product of the interpolation multiples of the sampling rate of each stage of signal is the same as the ratio of the target sampling rate to the initial sampling rate; the hierarchical packet determining module is further configured to determine the packet number of each level of signal according to the number of levels of hierarchical synthesis and the number of paths of the baseband signal.
Preferably, the packet synthesis module is configured to group and synthesize the signals after the interpolation of the stage according to the number of packets of the signals corresponding to the stage, and includes:
according to the sampling rate of the interpolated signals, frequency shifting is carried out on the signals in each group;
and synthesizing the signals after the frequency shifting in each packet into one path of signals.
Preferably, the packet synthesis module is configured to shift the frequency of the signal in each packet according to the sampling rate of the interpolated signal, and includes:
determining a frequency shift value of each path of signal in each packet according to the sampling rate of the interpolated signal;
and calculating a phase control word according to the frequency shift value of each signal in each packet, controlling the output signal of the IP core according to the phase control word, and multiplying the output signal of the IP core with the signal to obtain a frequency shifted signal.
Preferably, the packet synthesis module is configured to determine a frequency shift value of each signal in each packet according to a sampling rate of the interpolated signal, and includes:
and for each group, uniformly distributing the frequency shift value of each signal in a frequency band range corresponding to the sampling rate of the interpolated signal according to the sampling rate of the interpolated signal and the number of signal paths in the group.
Preferably, the packet synthesis module is configured to calculate, for each signal, a phase control word according to a frequency shift value of the signal, and includes: the value of the Phase control word Phase _ in is calculated according to the following formula:
according to the formula |fout|2 θ Calculating the numerical value corresponding to the 0 th to theta-1 th bits of the phase_in of the Phase control word;
when Fout is more than or equal to 0, the highest bit phase_in [ theta-1 ] =0 of the Phase control word; when Fout <0, the highest bit phase_in [ theta-1 ] =1 of the Phase control word,
where θ is the bit width of the phase control word, fout is the shift value, and Fs is the system clock frequency.
The method embodiment and the system embodiment are based on the same principle, and the related parts can be mutually referred to and can achieve the same technical effect. The specific implementation process refers to the foregoing embodiment, and will not be described herein.
Those skilled in the art will appreciate that all or part of the flow of the methods of the embodiments described above may be accomplished by way of a computer program to instruct associated hardware, where the program may be stored on a computer readable storage medium. Wherein the computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.
The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application.
Claims (10)
1. The multipath baseband signal synthesis method is characterized by comprising the following steps:
acquiring multi-path baseband signal data;
determining the stage number of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signals and the grouping number of each stage of signals according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the number of paths of baseband signals;
from the first stage to the last stage, interpolation filtering is carried out on the signals of the stage according to the interpolation multiple corresponding to each stage, and the signals after the stage interpolation are grouped and synthesized according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage;
the signal output by the last stage is the synthesized signal.
2. The multi-path baseband signal synthesis method according to claim 1, wherein determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal, and the number of packets of each stage of signal according to the ratio of the target sampling rate and the initial sampling rate of the multi-path baseband signal and the number of paths of the baseband signal, comprises:
determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the factor of the ratio; wherein the product of the interpolation multiples of the sampling rate of each stage of signal is the same as the ratio of the target sampling rate to the initial sampling rate; and determining the grouping number of each stage of signals according to the stage number of the hierarchical synthesis and the path number of the baseband signals.
3. The method of synthesizing a plurality of baseband signals according to claim 1, wherein grouping the signals interpolated by the stage according to the number of packets of the signals corresponding to the stage comprises:
according to the sampling rate of the interpolated signals, frequency shifting is carried out on the signals in each group;
and synthesizing the signals after the frequency shifting in each packet into one path of signals.
4. A method of synthesizing a plurality of baseband signals according to claim 3, wherein frequency shifting the signals in each packet according to the sample rate of the interpolated signals comprises:
determining a frequency shift value of each path of signal in each packet according to the sampling rate of the interpolated signal;
and calculating a phase control word according to the frequency shift value of each signal in each packet, controlling the output signal of the IP core according to the phase control word, and multiplying the output signal of the IP core with the signal to obtain a frequency shifted signal.
5. The method of multiplexing baseband signals according to claim 4, wherein determining the frequency shift value of each signal in each packet according to the sample rate of the interpolated signal comprises:
and for each group, uniformly distributing the frequency shift value of each path of signal in a frequency band range corresponding to the sampling rate of the interpolated signal according to the sampling rate of the interpolated signal and the number of signal paths in the group.
6. The method of synthesizing a plurality of baseband signals according to claim 4, wherein for each signal, calculating a phase control word based on its frequency shift value comprises: the value of the Phase control word Phase _ in is calculated according to the following formula:
according to the formula |fout|2 θ Calculating the numerical value corresponding to the 0 th to theta-1 th bits of the phase_in of the Phase control word;
when Fout is more than or equal to 0, the highest bit phase_in [ theta-1 ] =0 of the Phase control word; when Fout <0, the highest bit phase_in [ theta-1 ] =1 of the Phase control word,
where θ is the bit width of the phase control word, fout is the shift value, and Fs is the system clock frequency.
7. A multi-path baseband signal synthesis system, comprising the following modules:
the baseband signal acquisition module is used for acquiring multiple paths of baseband signal data;
the hierarchical grouping determining module is used for determining the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal and the grouping number of each stage of signal according to the ratio of the target sampling rate to the initial sampling rate of the multipath baseband signals and the number of paths of baseband signals;
the grouping and synthesizing module is used for sequentially carrying out interpolation filtering on the signals of each stage from the first stage to the last stage according to the interpolation multiple corresponding to each stage, and grouping and synthesizing the signals after the stage interpolation according to the grouping number of the signals corresponding to the stage; the signal after the grouping synthesis of the previous stage is the input signal of the next stage;
and the signal transmitting module is used for transmitting the synthesized signal output by the last stage.
8. The system of claim 7, wherein the hierarchical packet determination module is configured to determine the number of stages of hierarchical synthesis, the interpolation multiple of the sampling rate of each stage of signal, and the number of packets of each stage of signal based on the factor of the ratio; wherein the product of the interpolation multiples of the sampling rate of each stage of signal is the same as the ratio of the target sampling rate to the initial sampling rate; the hierarchical packet determining module is further configured to determine the packet number of each level of signal according to the number of levels of hierarchical synthesis and the number of paths of the baseband signal.
9. The system of claim 7, wherein the packet synthesis module is configured to group the signals interpolated by the stage according to the number of packets of the signals corresponding to the stage, and comprises:
according to the sampling rate of the interpolated signals, frequency shifting is carried out on the signals in each group;
and synthesizing the signals after the frequency shifting in each packet into one path of signals.
10. The multi-path baseband signal synthesis system according to claim 9, wherein the packet synthesis module is configured to shift the frequency of the signal in each packet according to the sample rate of the interpolated signal, and comprises:
determining a frequency shift value of each path of signal in each packet according to the sampling rate of the interpolated signal;
and calculating a phase control word according to the frequency shift value of each signal in each packet, controlling the output signal of the IP core according to the phase control word, and multiplying the output signal of the IP core with the signal to obtain a frequency shifted signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210008244.9A CN114337697B (en) | 2022-01-05 | 2022-01-05 | Multipath baseband signal synthesis method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210008244.9A CN114337697B (en) | 2022-01-05 | 2022-01-05 | Multipath baseband signal synthesis method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114337697A CN114337697A (en) | 2022-04-12 |
| CN114337697B true CN114337697B (en) | 2023-09-08 |
Family
ID=81023948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210008244.9A Active CN114337697B (en) | 2022-01-05 | 2022-01-05 | Multipath baseband signal synthesis method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114337697B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7233268B1 (en) * | 2006-06-03 | 2007-06-19 | Rdw, Inc. | Multi-stage sample rate converter |
| US8417749B1 (en) * | 2010-01-07 | 2013-04-09 | Xilinx, Inc. | Specifying a multirate digital filter based on a ratio of an input sample rate to an output sample rate |
| US8650236B1 (en) * | 2009-08-04 | 2014-02-11 | Altera Corporation | High-rate interpolation or decimation filter in integrated circuit device |
| CN110365351A (en) * | 2019-06-28 | 2019-10-22 | 中国航空工业集团公司雷华电子技术研究所 | A kind of method and device for realizing Digital Channelized Receiving based on filter multiplexing architectures |
| CN111756389A (en) * | 2018-11-30 | 2020-10-09 | 成都德辰博睿科技有限公司 | Multi-channel digital signal processing method and device based on FPGA (field programmable Gate array), computer equipment and storage medium |
| CN113661655A (en) * | 2019-04-30 | 2021-11-16 | 谷歌有限责任公司 | Multi-channel, multi-rate, lattice wave filter system and method |
| CN113890548A (en) * | 2021-09-24 | 2022-01-04 | 哈尔滨工程大学 | Device for signal up-conversion and field programmable gate array |
-
2022
- 2022-01-05 CN CN202210008244.9A patent/CN114337697B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7233268B1 (en) * | 2006-06-03 | 2007-06-19 | Rdw, Inc. | Multi-stage sample rate converter |
| US8650236B1 (en) * | 2009-08-04 | 2014-02-11 | Altera Corporation | High-rate interpolation or decimation filter in integrated circuit device |
| US8417749B1 (en) * | 2010-01-07 | 2013-04-09 | Xilinx, Inc. | Specifying a multirate digital filter based on a ratio of an input sample rate to an output sample rate |
| CN111756389A (en) * | 2018-11-30 | 2020-10-09 | 成都德辰博睿科技有限公司 | Multi-channel digital signal processing method and device based on FPGA (field programmable Gate array), computer equipment and storage medium |
| CN113661655A (en) * | 2019-04-30 | 2021-11-16 | 谷歌有限责任公司 | Multi-channel, multi-rate, lattice wave filter system and method |
| CN110365351A (en) * | 2019-06-28 | 2019-10-22 | 中国航空工业集团公司雷华电子技术研究所 | A kind of method and device for realizing Digital Channelized Receiving based on filter multiplexing architectures |
| CN113890548A (en) * | 2021-09-24 | 2022-01-04 | 哈尔滨工程大学 | Device for signal up-conversion and field programmable gate array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114337697A (en) | 2022-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4748578A (en) | Process and apparatus for translating the sampling rate of a sampling sequence | |
| CN103513231A (en) | Chirp signal generating method for three-dimensional imaging microwave altimeter and chirp signal generator | |
| US5925093A (en) | Sampling frequency converting apparatus | |
| CN113615088B (en) | Clock domain crossing synchronization circuit and method | |
| CN106502309A (en) | It is zeroed based on DA and keeps time domain intertexture random waveform synthesizer and the method for function | |
| CN100571232C (en) | Number makeup is put, Waveform generating apparatus and method, conversion method and recording medium | |
| CN105335105A (en) | QDR IV ultrahigh-speed storage controller suitable for FPGA | |
| CN109977347A (en) | A kind of restructural fft processor for supporting multi-mode to configure | |
| CN114337697B (en) | Multipath baseband signal synthesis method and system | |
| WO2024016896A1 (en) | Multi-phase clock generation circuit and method | |
| CN105116424A (en) | Beidou satellite navigation signal simulation source based on file generation and playback | |
| CN201830239U (en) | Self-adaptive calibrating device for mismatch error of time-interleaved analog-to-digital converter | |
| US5905967A (en) | Timing generator with multiple coherent synchronized clocks | |
| CN113110821B (en) | Delay configurable asynchronous FIFO circuit | |
| CN103188186B (en) | Resampling processing unit and method and digital modulation signals generation device | |
| CN103259602B (en) | Method and system for signal generation | |
| CN117235420B (en) | Signal processing circuit, method, processor, storage medium and chip | |
| CN201663654U (en) | Non-integral multiple interpolation device and signal modulation system | |
| CN105720944A (en) | Universal FIR filter and configuration method thereof | |
| CN116701296B (en) | Quantum bit control signal parameterization generation method | |
| CN109976660A (en) | Any resampling methods and sampled-data system based on linear interpolation | |
| CN106941381B (en) | Measurement and control communication signal simulation method and device based on segmented Hermite interpolation | |
| CN102946251A (en) | Method for realizing multi-channel synchronous sampling by multi-channel asynchronous sampling ADC (Analog Digital Converter) | |
| CN115242321A (en) | Radio frequency signal phase difference calibration method and system | |
| US6968353B2 (en) | Interpolator and interpolation method when interpolating a digital input signal sequence at interpolation instants prescribed by a control signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |