CN114334976A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A stacked contact plug is formed in the substrate, and a contact hole communicated with the stacked contact plug is formed in the insulating layer. A lower electrode is also formed above the insulating layer, and the lower electrode also extends downwards into the contact hole to be contacted with the stacked contact plug. By removing the conductor film in the contact hole and in contact with the stacked contact plug and the landing pad in contact with the conductor film, the lower electrode formed above the insulating layer also extends downwards into the contact hole and in contact with the stacked contact plug, so that a part of the lower electrode in contact with the stacked contact plug forms a structure similar to an anchor, the whole lower electrode can be supported, and the whole lower electrode is prevented from inclining. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure part in the lower electrode can also prevent the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background

A Capacitor (Capacitor) is a component that can store electricity and electrical energy. Different amounts of charge can be stored in the capacitor by applying different voltages across the two electrodes of the capacitor. On this basis, the storage of different data can be realized by a capacitor. It follows that the quality of the capacitor directly affects the data storage performance of the semiconductor device.

In order to improve the driving performance of the memory, the capacitance of the capacitor needs to be increased. A common way to increase the capacitance of a capacitor is to increase the height of the capacitor. However, the height of the capacitor is increased, which results in an increase in the Aspect Ratio (Aspect Ratio) of the capacitor. The aspect ratio of the capacitor is increased, and the problems of capacitor inclination, bending and even collapse are easy to occur when Wet cleaning process is performed.

Disclosure of Invention

The invention provides a semiconductor device and a method for manufacturing the same, which is used for preventing a capacitor from inclining, bending or collapsing.

In a first aspect, the present invention provides a semiconductor device including a substrate, and an insulating layer stacked on the substrate. Wherein, a stacked Contact (BC) is formed in the substrate, and a Contact hole communicating with the stacked Contact is formed in the insulating layer. A lower electrode is also formed above the insulating layer, and the lower electrode also extends downwards into the contact hole to be contacted with the stacked contact plug.

In the above solution, the lower electrode formed above the insulating layer is further extended into the contact hole to contact with the stacked contact plug by removing the conductive film in the contact hole and the Landing Pad (LP) in contact with the conductive film, so that a portion of the lower electrode in contact with the stacked contact plug forms an anchor-like structure, which can support the entire lower electrode and prevent the entire lower electrode from tilting. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure part in the lower electrode can also prevent the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. And the part of the lower electrode extending into the contact hole can increase the surface area of the lower electrode, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode extends downwards to the contact hole to be directly contacted with the stacked contact plug, so that the mode that the lower electrode is contacted with the stacked contact plug through a landing pad and a conductor film is replaced, the number of contacts among different layers is reduced, and the resistance of interlayer current transmission is reduced. When the capacitor is applied, the whole lower electrode is supported by the anchor-like structure part in the lower electrode, so that the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is further improved.

In one embodiment, the portion of the lower electrode extending into the contact hole is deposited on the hole wall of the contact hole and the upper end surface of the stacked contact plug, so as to improve the contact strength between the lower electrode and the hole wall of the contact hole and the stacked contact plug and improve the supporting effect on the whole lower electrode.

In a specific embodiment, the lower electrode is cylindrical in shape; wherein the bottom wall of the lower electrode is deposited on the upper end face of the stacked contact plug; the side wall part of the lower electrode is deposited on the hole wall of the contact hole and is partially exposed outside the contact hole. By using the cylindrical lower electrode, the surface area of the lower electrode is increased, and the capacitance of the capacitor is increased.

In one embodiment, an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode are formed on the bottom wall, the inner sidewall and the outer sidewall exposed outside the contact hole of the lower electrode. Capacitor structures are arranged on the inner side and the outer side of the lower electrode, so that the capacitance of the capacitor is improved, and the storage effect is improved.

In a specific embodiment, an etching barrier layer is further stacked on the insulating layer, and the contact hole further penetrates through the etching barrier layer. By laminating the etching barrier layer on the insulating layer, the influence of subsequent operations such as etching or cleaning on the substrate is prevented, and the quality of the substrate and the insulating layer is ensured.

In a specific embodiment, the semiconductor device is a dynamic random access memory to prevent collapse of a capacitor in the dynamic random access memory due to inclination, bending, or the like of a lower electrode.

In a second aspect, the present invention also provides a method of manufacturing a semiconductor device, the method comprising:

providing a substrate, wherein a stacking contact plug is formed in the substrate;

laminating an insulating layer on a substrate;

forming a contact hole in the insulating layer;

filling a landing pad in conductive connection with the stacked contact plug in the contact hole;

removing the landing pad;

a lower electrode is formed over the insulating layer and extends down into the contact hole to be conductively connected to the stacked contact plug.

In the above solution, by removing the landing pad in the contact hole conductively connected to the stacked contact plug, the lower electrode formed above the insulating layer further extends downward into the contact hole to conductively connect to the stacked contact plug, so that a portion of the lower electrode located in the contact hole forms a structure similar to an anchor, which can support the entire lower electrode and prevent the entire lower electrode from tilting. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure part in the lower electrode can also prevent the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. And the part of the lower electrode extending into the contact hole can increase the surface area of the lower electrode, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode extends downwards into the contact hole to be electrically connected with the stacked contact plug, so that the mode that the lower electrode is electrically connected with the stacked contact plug through the landing pad is replaced, the number of contacts among different layers is reduced, and the resistance of interlayer current transmission is reduced. When the capacitor is applied, the whole lower electrode is supported by the anchor-like structure part in the lower electrode, so that the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is further improved.

In a specific embodiment, the landing pads filled in the contact holes and conductively connected with the stacked contact plugs are specifically: filling a conductor film in contact with the stacked contact plug in the contact hole; the contact hole is filled with a landing pad in contact with the conductor film. After removing the landing pad, before forming the lower electrode over the insulating layer, the manufacturing method further includes: the conductor film is removed. The lower electrode extends downwards into the contact hole to be directly contacted with the stacked contact plug, so that the mode that the lower electrode is contacted with the stacked contact plug through the landing pad and the conductor film is replaced, the contact number among different layers is reduced, and the resistance of interlayer current transmission is reduced.

In a specific embodiment, after the contact hole is filled with the landing pad conductively connected with the stacked contact plug, and before the landing pad is removed, the manufacturing method further includes: laminating a sacrificial film layer on the insulating layer; a capacitor hole communicated with the landing pad is formed in the sacrificial film layer. Forming a lower electrode above the insulating layer, wherein the lower electrode extends downwards into the contact hole and is electrically connected with the stacked contact plug: and forming lower electrodes which are contacted with the stacked contact plugs on the wall of the capacitor hole and the contact hole and the upper end surface of the stacked contact plug. So as to form the lower electrode.

In a specific embodiment, the removing the landing pad is specifically: and removing the landing pad by adopting a wet etching or remote plasma dry cleaning process so as to remove the landing pad without influencing other film qualities.

In a specific embodiment, the removing the conductor film is specifically: and removing the conductor film by adopting a wet etching or remote plasma dry cleaning process so as to remove the conductor film without influencing other film qualities.

In a specific embodiment, the lower electrode formed on the wall of the capacitor hole and the contact hole and on the upper end surface of the stacked contact plug to contact the stacked contact plug is specifically: depositing a lower electrode material layer on the surface of the sacrificial film layer, the wall of the capacitor hole and the contact hole and the upper end surface of the stacked contact plug; and removing the lower electrode material layer on the surface of the sacrificial film layer to form a lower electrode in contact with the stacked contact plug. So as to form the lower electrode, improve the contact strength of the lower electrode and the hole wall of the contact hole and the upper end surface of the stacked contact plug, and improve the effect of supporting the whole lower electrode.

In one specific embodiment, after forming the lower electrode over the insulating layer, the manufacturing method further includes: and removing the sacrificial film layer so as to form a capacitor structure on the inner side and the outer side of the lower electrode in the follow-up process, thereby improving the capacitance of the capacitor and the storage performance.

Drawings

FIG. 1a is a schematic diagram of one step in the prior art process for fabricating a capacitor;

FIG. 1b is a schematic diagram of another prior art process for fabricating a capacitor;

fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 4 is a schematic view of another step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;

fig. 5 is a schematic diagram illustrating another step in the method for manufacturing the semiconductor device according to the embodiment of the present invention.

Reference numerals in fig. 1a to 1 b:

1-substrate 2-sacrificial film layer 3-capacitor hole 4-landing pad 5-bottom electrode

Reference numerals in fig. 2 to 5:

10-substrate 11-stacked contact plug 12-insulation part

20-insulating layer 21-contact hole 22-spacer 23-conductor film

24-landing pad 30-bottom electrode 40-sacrificial film layer 50-capacitor via

60-etch stop layer 70-support layer 71-support structure

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

To facilitate understanding of the semiconductor device provided in the embodiment of the present invention, an application scenario of the semiconductor device provided in the embodiment of the present invention, which is applied to a memory having a capacitor, is first described below. The semiconductor device will be described in detail with reference to the drawings.

Referring to fig. 2, a semiconductor device according to an embodiment of the present invention includes a substrate 10 and an insulating layer 20 stacked on the substrate 10. The substrate 10 has a stacked contact plug 11 formed therein, and the insulating layer 20 has a contact hole 21 formed therein to communicate with the stacked contact plug 11. A lower electrode 30 is also formed above the insulating layer 20, and the lower electrode 30 also extends downward into the contact hole 21 to be in contact with the stacked contact plug 11.

In the above-described embodiment, by removing the conductor film in the contact hole 21 and the landing pad in contact with the stacked contact plug 11, the lower electrode 30 formed above the insulating layer 20 is extended downward into the contact hole 21 and contacts with the stacked contact plug 11, and the portion of the lower electrode 30 in contact with the stacked contact plug 11 is formed into an anchor-like structure, so that the entire lower electrode 30 can be supported and the entire lower electrode 30 can be prevented from tilting. The anchor-like structure portion of the lower electrode 30 also prevents the entire lower electrode 30 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 30 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 30 extending into the contact hole 21 can increase the surface area of the lower electrode 30, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 30 extends downwards to the contact hole 21 to be directly contacted with the stacked contact plug 11, so that the mode that the lower electrode 30 is contacted with the stacked contact plug 11 through a landing pad and a conductor film is replaced, the contact number between different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 30 supports the entire lower electrode 30, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance. The arrangement of the above-described structures will be described in detail with reference to the accompanying drawings.

When the substrate 10 is disposed, the substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, referring to fig. 2, the base 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a stacked contact plug 11, an insulating portion 12, and the like. The transistor may be formed on a semiconductor substrate of a semiconductor device. A bitline structure may be formed over the transistor. The stacked contact plug 11 and the insulating portion 12 are formed between adjacent bit line structures. The stacked contact plug 11 contacts a source region or a drain region of the transistor. The insulating portion 12 serves to isolate adjacent two stacked contact plugs 11.

With continued reference to fig. 2, an insulating layer 20 is stacked on the substrate 10, and a contact hole 21 communicating with the stacked contact plug 11 is opened in the insulating layer 20. That is, the contact hole 21 penetrates the entire insulating layer 20, an upper end of the contact hole 21 communicates with an upper surface of the insulating layer 20, and a lower end of the contact hole 21 communicates with the stacked contact plug 11 on the substrate 10.

As shown in fig. 2, a lower electrode 30 is further formed above the insulating layer 20, and the lower electrode 30 further extends downward into the contact hole 21 to be in contact with the stacked contact plug 11. That is, the lower electrode 30 includes two main portions, one of which is a portion located above the insulating layer 20 and exposed to the contact hole; the other portion is a portion located within the contact hole 21, and the lower end of the portion is in contact with the stacked contact plug 11.

Referring to fig. 1a, a method for manufacturing a capacitor in the prior art is shown in fig. 1a to 1b, first depositing a sacrificial film layer 2 on a substrate 1; then, etching the sacrificial film layer 2 to form a capacitor hole 3, wherein the capacitor hole 3 is communicated with a landing pad 4 in the substrate 1; then, depositing a lower electrode material layer on the sacrificial film layer 2, the inner wall of the capacitor hole 3 and the upper end surface of the landing pad 4; thereafter, referring to fig. 1b, the lower electrode material layer except the capacitor hole 3 is removed to form a lower electrode 5; thereafter, referring to fig. 1b, the sacrificial film layer 2 is removed; and depositing a dielectric layer and an upper electrode on the lower electrode 5 to form a capacitor.

Compared with the scheme in fig. 1b in the prior art, the scheme in the application removes the conductor film in the contact hole 21 and the landing pad in contact with the stacked contact plug 11, extends the lower electrode 30 formed above the insulating layer 20 into the contact hole 21 and contacts with the stacked contact plug 11, and makes the part of the lower electrode 30 in contact with the stacked contact plug 11 form an anchor-like structure, so that the whole lower electrode 30 can be supported and the whole lower electrode 30 is prevented from being inclined. The anchor-like structure portion of the lower electrode 30 also prevents the entire lower electrode 30 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 30 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 30 extending into the contact hole 21 can increase the surface area of the lower electrode 30, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 30 extends downwards to the contact hole 21 to be directly contacted with the stacked contact plug 11, so that the mode that the lower electrode 30 is contacted with the stacked contact plug 11 through a landing pad and a conductor film is replaced, the contact number between different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 30 supports the entire lower electrode 30, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance.

In particular, when the portion of the lower electrode 30 extending into the contact hole 21 is brought into contact with the stacked contact plug 11, the portion of the lower electrode 30 extending into the contact hole 21 may be deposited on the upper end surface of the stacked contact plug 11, so as to improve the contact strength of the lower electrode 30 with the stacked contact plug 11 and improve the supporting effect on the entire lower electrode 30. Meanwhile, the part of the lower electrode 30 extending into the contact hole 21 can be deposited on the hole wall of the contact hole 21, even if the part of the lower electrode 30 extending into the contact hole 21 is not only contacted with the stacked contact plug 11, but also contacted with the hole wall of the contact hole 21, so that the contact area of the lower electrode 30 with the contact hole 21 and the stacked contact plug 11 is increased, and the supporting effect on the whole lower electrode 30 is improved.

When the lower electrode 30 is provided, the lower electrode 30 may be shaped as a hollow cylindrical structure including a thin-walled bottom and a sidewall communicating with the bottom. The bottom wall of the lower electrode 30 may be deposited on the upper end face of the stacked contact plug 11, that is, the bottom of the lower electrode 30 is deposited on the upper end face of the stacked contact plug 11. The sidewall portion of the lower electrode 30 is deposited on the hole wall of the contact hole 21 and partially exposed outside the contact hole 21, i.e., the portion of the sidewall of the lower electrode 30 located inside the contact hole 21 is deposited on the hole wall of the contact hole 21 and the portion exposed outside the contact hole 21 vertically stands above the insulating layer 20. By using the cylindrical lower electrode 30, the surface area of the lower electrode 30 is increased, and the capacitance of the capacitor is increased.

When a dielectric layer and an upper electrode are formed on the lower electrode 30, the upper electrode and the dielectric layer for insulating and isolating the lower electrode 30 from the upper electrode may be formed on the bottom wall, the inner sidewall, and the outer sidewall exposed to the outer portion of the contact hole 21 of the lower electrode 30, so as to complete the manufacture of the capacitor. That is, the dielectric layer and the upper electrode are formed only on the inner sidewall and the bottom wall of the portion of the lower electrode 30 located in the contact hole 21, and the portion of the lower electrode 30 exposed outside the contact hole 21 is formed with the dielectric layer and the upper electrode on the inner sidewall as well as the dielectric layer and the upper electrode on the outer sidewall. The capacitor structures are arranged on the inner side and the outer side of the lower electrode 30, so that the capacitance of the capacitor is improved, and the storage effect is improved. It should be understood that the manner of providing the dielectric layer and the upper electrode is not limited to the above-described manner, and other manners may be adopted. For example, the dielectric layer and the upper electrode may be formed only on the inner wall and the bottom wall of the lower electrode 30, and the dielectric layer and the upper electrode may not be formed on the outer wall of the lower electrode 30.

In addition, as shown in fig. 2, the contact hole 21 may be formed in a shape having a large upper end, a small middle, and a large lower end, and the surface area of the lower electrode 30 contacting the sidewall of the contact hole 21 may be increased to improve the supporting effect of the lower electrode 30 located in the contact hole 21 on the entire lower electrode 30. And the lower end of the contact hole 21 is large, so that the contact area of the lower electrode 30 and the stacked contact plug 11 can be increased, and the resistance of interlayer current transmission can be reduced. The upper end of the contact hole 21 is large, so that the lower electrode 30 exposed out of the contact hole 21 has a large surface area, thereby improving the capacitance of the capacitor and improving the storage performance. Of course, the contact hole 21 may be provided as a hollow cylindrical through hole.

Referring to fig. 2, an etch stopper layer 60 may be further stacked on the insulating layer 20, and at this time, the contact hole 21 also penetrates the etch stopper layer 60. By laminating the etching barrier layer 60 on the insulating layer 20, the subsequent operations such as etching or cleaning are prevented from affecting the substrate 10, and the quality of the substrate 10 and the insulating layer 20 is ensured. When determining the material of the etching barrier layer 60, the material of the etching barrier layer 60 may be selected from SiN, SiBN, or SiCN, so as to improve the barrier effect during etching.

As shown in fig. 2, a support structure 71 supporting the lower electrode 30 may be further disposed above the etch stop layer 60, and the support structure 71 surrounds the outer sidewall of the lower electrode 30 to improve the supporting effect on the lower electrode 30. Specifically, when the support structure 71 is disposed, the support structure 71 may be disposed at an upper end of the lower electrode 30, or disposed at a middle position of the lower electrode 30, and the support structures 71 may be disposed at different positions of the lower electrode 30.

In determining the type of the semiconductor device, the semiconductor device may be a Dynamic Random Access Memory (DRAM) to prevent collapse of a capacitor in the DRAM due to inclination, bending, or the like of the lower electrode 3040. The semiconductor device may also be a Static Random-Access Memory (SRAM), a flash Memory (flash Memory), or the like that employs a capacitor as a storage unit.

By removing the conductor film in the contact hole 21 in contact with the stacked contact plug 11 and the landing pad in contact with the conductor film, the lower electrode 30 formed above the insulating layer 20 is extended further downward into the contact hole 21 in contact with the stacked contact plug 11, so that the portion of the lower electrode 30 in contact with the stacked contact plug 11 forms an anchor-like structure, and the entire lower electrode 30 can be supported, preventing the entire lower electrode 30 from tilting. The anchor-like structure portion of the lower electrode 30 also prevents the entire lower electrode 30 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 30 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 30 extending into the contact hole 21 can increase the surface area of the lower electrode 30, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 30 extends downwards to the contact hole 21 to be directly contacted with the stacked contact plug 11, so that the mode that the lower electrode 30 is contacted with the stacked contact plug 11 through a landing pad and a conductor film is replaced, the contact number between different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 30 supports the entire lower electrode 30, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance.

In addition, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, and with reference to fig. 1 to 5, the method includes:

the method comprises the following steps: providing a substrate 10, wherein a stacking contact plug 11 is formed in the substrate 10;

step two: laminating an insulating layer 20 on the substrate 10;

step three: forming a contact hole 21 in the insulating layer 20;

step four: filling the contact hole 21 with a landing pad 24 conductively connected to the stacked contact plug 11;

step five: removing the landing pad 24;

step six: a lower electrode 30 is formed over the insulating layer 20, and the lower electrode 30 extends down into the contact hole 21 to be conductively connected to the stacked contact plug 11.

In the above-mentioned solution, by removing the landing pad 24 in the contact hole 21 and conductively connected to the stacked contact plug 11, the lower electrode 30 formed above the insulating layer 20 is further extended downward into the contact hole 21 and conductively connected to the stacked contact plug 11, so that a portion of the lower electrode 30 located in the contact hole 21 forms an anchor-like structure, which can support the entire lower electrode 30 and prevent the entire lower electrode 30 from tilting. The anchor-like structure portion of the lower electrode 30 also prevents the entire lower electrode 30 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 30 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 30 extending into the contact hole 21 can increase the surface area of the lower electrode 30, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 30 extends downwards into the contact hole 21 to be in conductive connection with the stacked contact plug 11, so that the mode that the lower electrode 30 is in conductive connection with the stacked contact plug 11 through the landing pad 24 is replaced, the number of contacts between different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 30 supports the entire lower electrode 30, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance. The above steps will be described in detail with reference to the accompanying drawings.

First, referring to fig. 3, a substrate 10 is provided, and a stacked contact plug 11 is formed in the substrate 10. The substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, referring to fig. 3, the base 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a stacked contact plug 11, an insulating portion 12, a landing pad 24, and an isolation portion 22. The transistor may be formed on a semiconductor substrate of a semiconductor device. A bitline structure may be formed over the transistor. The stacked contact plug 11 and the insulating portion 12 are formed between adjacent bit line structures. The stacked contact plug 11 contacts a source region or a drain region of the transistor. The insulating portion 12 serves to isolate adjacent two stacked contact plugs 11.

Next, referring to fig. 3, an insulating layer 20 is stacked on the substrate 10.

Next, referring to fig. 3, a contact hole 21 is opened in the insulating layer 20. That is, the contact hole 21 penetrates the entire insulating layer 20, an upper end of the contact hole 21 communicates with an upper surface of the insulating layer 20, and a lower end of the contact hole 21 communicates with the stacked contact plug 11 on the substrate 10.

Next, referring to fig. 3, the contact hole 21 is filled with a landing pad 24 conductively connected to the stacked contact plug 11. Specifically, referring to fig. 3, the contact hole 21 may be filled with a conductor film 23 in contact with the stacked contact plug 11; then, the contact hole 21 is filled with a landing pad 24 in contact with the conductive film 23. That is, the conductor film 23 is filled between the landing pad 24 and the stacked contact plug 11, the conductor film 23 in contact with the stacked contact plug 11 and the landing pad 24 in contact with the conductor film 23 are sequentially filled in the contact hole 21 from the bottom up, and the landing pad 24 is electrically connected to the source region or the drain region of the transistor through the conductor film 23 and the stacked contact plug 11. The material of the conductive film 23 may be a metal silicide to increase the conductivity between the landing pad 24 and the stacked contact plug 11. Referring to fig. 3, an isolation portion 22 is also formed in the bit line structure and the insulating layer 20, and the isolation portion 22 is used to isolate two adjacent landing pads 24.

Next, referring to fig. 4, the landing pad 24 is removed. The landing pad 24 may be made of metal. When landing pad 24 is removed, a wet etch or remote plasma dry clean process may be used to remove landing pad 24 to affect other film qualities. Referring to fig. 5, when the landing pad 24 is in contact with the stacked contact plug 11 through the conductor film 23, the conductor film 23 may be removed after the landing pad 24 is removed and before the lower electrode 30 is formed over the insulating layer 20, so that the lower electrode 30 formed in the contact hole 21 in the subsequent process is directly in contact with the stacked contact plug 11. When removing the conductor film 23, the conductor film 23 may be removed by wet etching or a remote plasma dry cleaning process to remove it without affecting other film qualities. The lower electrode 30 extends downwards into the contact hole 21 to be directly contacted with the stacked contact plug 11, so that the mode that the lower electrode 30 is contacted with the stacked contact plug 11 through the landing pad 24 and the conductor film 23 is replaced, the contact number between different layers is reduced, and the resistance of interlayer current transmission is reduced. Of course, it is also possible to remove only the landing pad 24 without removing the conductor film 23, and to electrically connect the lower electrode 30 to the stacked contact plug 11 through the conductor film 23.

Next, the lower electrode 30 is formed over the insulating layer 20, and the lower electrode 30 extends downward into the contact hole 21 to be conductively connected to the stacked contact plug 11. Specifically, referring to fig. 3, after the landing pad 24 conductively connected to the stacked contact plug 11 is filled in the contact hole 21, a sacrificial film layer 40 may be stacked on the insulating layer 20 before the landing pad 24 is removed. Thereafter, a capacitor hole 50 communicating with the landing pad 24 is opened in the sacrificial film layer 40.

When depositing the sacrificial film layer 40 on the insulating layer 20, the sacrificial film layer 40 may be deposited directly on the insulating layer 20. An etch stop layer 60 may also be deposited between the sacrificial film layer 40 and the insulating layer 20, and the capacitor hole 50 may communicate with the landing pad 24 after penetrating the sacrificial film layer 40 and the etch stop layer 60. By arranging the etching barrier layer 60 between the sacrificial film layer 40 and the insulating layer 20, after the sacrificial film layer 40 is removed in the subsequent process, the etching barrier layer 60 can prevent subsequent operations such as etching or cleaning from affecting the substrate 10 and the insulating layer 20, and ensure the quality of the substrate 10 and the insulating layer 20.

With continued reference to fig. 3, at least one support layer 70 may also be formed in or over the sacrificial film layer 40, wherein the capacitor holes 50 not only extend through the sacrificial film layer 40 and the etch stop layer 60, but also extend through each support layer 70 and then communicate with the landing pads 24. After the lower electrode 30 is formed in the subsequent process, in the process of removing the sacrificial film layer 40, a part of the support layer 70 is also removed, and the remaining part of the support layer 70 serves as a support structure 71 to support the lower electrode 30.

When the lower electrode 30 is formed on the insulating layer 20, the lower electrode 30 may be formed on the walls of the capacitor hole 50 and the contact hole 21, and on the upper end surface of the stacked contact plug 11 so as to be in contact with the stacked contact plug 11. Specifically, first, a lower electrode material layer may be deposited on the surface of the sacrificial film layer 40, the wall of the capacitor hole 50 and the contact hole 21, and the upper end surface of the stacked contact plug 11; and then, removing the lower electrode material layer on the surface of the sacrificial film layer 40 to form the lower electrode 30 in contact with the stacked contact plug 11, and specifically, removing the lower electrode material layer on the surface of the sacrificial film layer 40 by adopting a plasma etching or wet etching method. So as to form the lower electrode 30, and improve the contact strength between the lower electrode 30 and the hole wall of the contact hole 21 and the upper end surface of the stacked contact plug 11, thereby improving the effect of supporting the whole lower electrode 30.

After the lower electrode 30 is formed, the sacrificial film layer 40 may be removed to form the semiconductor device shown in fig. 2, so that a capacitor structure is formed on both the inner side and the outer side of the lower electrode 30, the capacitance of the capacitor is improved, and the storage performance is improved. The sacrificial film layer 40 may be removed by plasma etching or wet etching. When at least one support layer 70 is further formed in the sacrificial film layer 40, it is also necessary to remove a portion of the support layer 70 of each support layer 70, and to leave a portion of the support layer 70 of each layer connected to the outer wall of the lower electrode 30 as a support structure 71 for supporting the lower electrode 30, and the support structure 71 surrounds at least one circle around the outer wall of the lower electrode 30.

By removing the landing pad 24 in the contact hole 21 conductively connected to the stacked contact plug 11, the lower electrode 30 formed above the insulating layer 20 is extended further down into the contact hole 21 to be conductively connected to the stacked contact plug 11, so that a portion of the lower electrode 30 located in the contact hole 21 forms an anchor-like structure, which can support the entire lower electrode 30 and prevent the entire lower electrode 30 from tilting. The anchor-like structure portion of the lower electrode 30 also prevents the entire lower electrode 30 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 30 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 30 extending into the contact hole 21 can increase the surface area of the lower electrode 30, thereby improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 30 extends downwards to the contact hole 21 to be in conductive connection with the stacked contact plug 11, so that the mode that the lower electrode 30 is in conductive connection with the stacked contact plug 11 through the landing pad 24 is replaced, the number of contacts among different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 30 supports the entire lower electrode 30, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A semiconductor device, comprising:

a substrate having a stacking contact plug formed therein;

an insulating layer stacked on the substrate, wherein a contact hole communicated with the stacked contact plug is formed in the insulating layer;

a lower electrode formed over the insulating layer and extending down into the contact hole to contact the stacked contact plug.

2. The semiconductor device according to claim 1, wherein a portion of the lower electrode extending into the contact hole is deposited on a wall of the contact hole and an upper end surface of the stacked contact plug.

3. The semiconductor device according to claim 2, wherein the lower electrode is cylindrical in shape; wherein a bottom wall of the lower electrode is deposited on an upper end face of the stacked contact plug; the side wall part of the lower electrode is deposited on the hole wall of the contact hole, and is partially exposed out of the contact hole.

4. The semiconductor device according to claim 3, wherein an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode are formed on the bottom wall, the inner sidewall of the lower electrode and the outer sidewall exposed to the outer portion of the contact hole.

5. The semiconductor device according to claim 1, wherein an etching stopper layer is further stacked on the insulating layer, and the contact hole further penetrates the etching stopper layer.

6. The semiconductor device according to claim 1, wherein the semiconductor device is a dynamic random access memory.

7. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a stacking contact plug is formed in the substrate;

laminating an insulating layer on the substrate;

forming a contact hole in the insulating layer;

filling a landing pad in contact with the stacked contact plug in the contact hole;

removing the landing pad;

a lower electrode is formed over the insulating layer and extends down into the contact hole in conductive connection with the stacked contact plug.

8. The manufacturing method according to claim 7, wherein the step of filling the landing pad conductively connected to the stacked contact plug in the contact hole is specifically as follows:

filling a conductor film in contact with the stacked contact plug in the contact hole;

filling a landing pad in contact with the conductor film in the contact hole;

after the removing the landing pad and before forming a lower electrode over the insulating layer, the manufacturing method further includes: and removing the conductor film.

9. The method of manufacturing of claim 8, wherein after the contact hole is filled with a landing pad conductively connected to the stacked contact plug, and before the landing pad is removed, the method further comprises:

laminating a sacrificial film layer on the insulating layer;

a capacitor hole communicated with the landing pad is formed in the sacrificial film layer;

the step of forming a lower electrode above the insulating layer, wherein the step of extending the lower electrode downward into the contact hole to be electrically connected with the stacked contact plug specifically comprises the following steps:

and forming lower electrodes which are contacted with the stacked contact plugs on the wall of the capacitor hole and the wall of the contact hole and the upper end surface of the stacked contact plug.

10. The manufacturing method according to claim 9, wherein the forming of the lower electrode in contact with the stacked contact plug on the hole walls of the capacitor hole and the contact hole and the upper end surface of the stacked contact plug is specifically:

depositing a lower electrode material layer on the surface of the sacrificial film layer, the wall of the capacitor hole and the wall of the contact hole and the upper end surface of the stacked contact plug;

and removing the lower electrode material layer on the surface of the sacrificial film layer to form the lower electrode in contact with the stacked contact plug.

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