CN114334977A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A first contact hole is formed in the first insulation lamination layer, a stacked contact plug is filled in the first contact hole from bottom to top, and the stacked contact plug is not filled in the first contact hole. A second contact hole communicated with the first contact hole is formed in the second insulating laminated layer. The lower electrode is formed above the second insulating lamination layer, and the lower electrode further extends downwards to the second contact hole and the first contact hole in sequence to be contacted with the stacked contact plug. And the lower electrodes formed above the two insulating laminated layers also extend downwards into the first contact hole and the second contact hole to be contacted with the reserved stacking contact plugs, so that the partial lower electrodes contacted with the stacking contact plugs form a structure similar to an anchor, and the whole lower electrode is supported to prevent the whole lower electrode from inclining. The surface area of the lower electrode is increased, and the capacitance of the capacitor is improved.

Description

A kind of semiconductor device and its manufacturing method

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

A capacitor is a component that can store electricity and electrical energy. Different amounts of charge can be stored in a capacitor by applying different voltages to the two electrodes of the capacitor. On this basis, the storage of different data can be realized through capacitors. It can be seen that the quality of the capacitor directly affects the data storage performance of the semiconductor device.

In order to improve the driving performance of the memory, the capacitance of the capacitor needs to be increased. The general way to increase the capacitance of a capacitor is to increase the height of the capacitor. However, as the height of the capacitor increases, the aspect ratio (Aspect Ratio) of the capacitor increases. When the aspect ratio of the capacitor increases, it is easy to have problems such as tilting, bending and even collapse of the capacitor during the Wet Clean process.

SUMMARY OF THE INVENTION

The invention provides a semiconductor device and a manufacturing method thereof, which can effectively increase the charge storage capacity of the capacitor, and at the same time can effectively prevent the capacitor from tilting, bending or collapsing.

In a first aspect, the present invention provides a semiconductor device including a substrate, a first insulating stack stacked on the substrate, and a second insulating stack stacked on the first insulating stack. Wherein, a first contact hole is opened on the first insulating layer, the first contact hole is filled with stacking contact plugs from bottom to top, and the stacking contact plug is not filled with the first contact hole. A second contact hole communicated with the first contact hole is opened on the second insulating stack. The semiconductor device further includes a lower electrode formed over the second insulating stack, and the lower electrode further extends downward into the second contact hole and the first contact hole in order to contact the stacked contact plugs.

In the above solution, by removing the conductor film in the second contact hole and the Landing Pad (LP) in contact with the conductor film, part of the stacked contact plug (Buried Contact, LP) in the first contact hole is also removed. (abbreviated as BC), the lower electrode formed above the two insulating stacks is also extended downward into the first contact hole and the second contact hole to contact the remaining stacking contact plugs, so that the part in contact with the stacking contact plugs is lower The electrode forms an anchor-like structure, which can support the entire lower electrode and prevent the entire lower electrode from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure portion in the lower electrode can also prevent the entire lower electrode from being bent and deformed, thereby preventing the capacitor from collapsing. And the part of the lower electrode extending into the first contact hole and the second contact hole can increase the surface area of the lower electrode, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And through the lower electrode extending down to the first contact hole and the second contact hole, it directly contacts with the remaining stacked contact plugs, instead of the way that the lower electrode contacts the stacked contact plugs through the landing pad and the conductor film, reducing the difference. The number of contacts between layers reduces the resistance of current transfer between layers. In application, since the entire lower electrode is supported by the anchor-like structural part in the lower electrode, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance.

In a specific embodiment, the lower electrode extending to the second contact hole and the hole wall of the first contact hole is deposited on the hole wall of the first contact hole and the second contact hole, and extends to the upper end surface of the stacked contact plug The lower electrode is deposited on the upper end surface of the stacked contact plug, so as to improve the contact strength of the lower electrode with the hole wall of the contact hole and the stacked contact plug, and improve the supporting effect of the entire lower electrode.

In a specific embodiment, the lower electrode is formed into a cylindrical shape; wherein, the bottom wall of the lower electrode is deposited on the upper end surface of the stacked contact plug; the sidewall of the lower electrode is partially deposited on the first contact hole and the second contact A part of the hole wall of the hole is exposed outside the first contact hole and the second contact hole. By adopting the cylindrical lower electrode, the surface area of the lower electrode is increased, the charge storage capacity of the capacitor is increased, and the capacitance of the capacitor is increased.

In a specific embodiment, an upper electrode is formed on the bottom wall, inner sidewall, and outer sidewall of the lower electrode exposed to the outer parts of the first contact hole and the second contact hole, and the lower electrode is insulated from the upper electrode. isolated dielectric layer. By arranging capacitor structures on both the inner and outer sides of the lower electrode, the charge storage capacity of the capacitor is increased, the capacitance of the capacitor is increased, and the storage effect is improved.

In a specific embodiment, the height of the stacked contact plugs is h1, and the height of the first contact hole is h2, wherein 20%×h2≤h1≤80%×h2. In order to ensure that the part of the lower electrode extending into the first contact hole has a larger contact surface with the side wall of the first contact hole, and to ensure the supporting effect of the formed anchor-like structure on the entire lower electrode. At the same time, the height of the stacked contact plugs is ensured, so that the stacked contact plugs and the lower electrode have a relatively stable bonding state.

In a specific embodiment, an etch barrier layer is further deposited on the second insulating stack, and the second contact hole also penetrates the etch barrier layer. By depositing an etch stop layer on the second insulating stack, the substrate and the quality of the insulating stack are ensured to prevent subsequent operations such as etching or cleaning from affecting the substrate.

In a specific embodiment, the semiconductor device is a dynamic random access memory, so as to prevent the collapse of the capacitor in the dynamic random access memory due to inclination, bending, etc. of the lower electrode.

In a second aspect, the present invention also provides a method for manufacturing a semiconductor device, the method comprising:

provide a base;

Laminate an insulating layer on the substrate;

A contact hole is opened in the insulating layer;

The contact holes are filled with stacked contact plugs, and the landing pads are conductively connected with the stacked contact plugs;

remove the landing pad;

Remove partially stacked contact plugs from top to bottom;

A lower electrode is formed over the insulating layer, and the lower electrode also extends down into the contact hole to make contact with the remaining stacked contact plugs.

In the above solution, by removing the landing pads in the contact holes, and also removing part of the stacked contact plugs in the contact holes, the lower electrodes formed above the insulating layer are also extended down into the contact holes and the remaining stacked contact plugs are also removed. The contact plugs are in contact, so that the part of the lower electrode in contact with the stacked contact plugs forms an anchor-like structure, which can support the entire lower electrode and prevent the entire lower electrode from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure portion in the lower electrode can also prevent the entire lower electrode from being bent and deformed, thereby preventing the capacitor from collapsing. And the part of the lower electrode extending into the contact hole can increase the surface area of the lower electrode, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And through the lower electrode extending down to the contact hole, it directly contacts with the remaining stacked contact plugs, instead of the way that the lower electrode contacts the stacked contact plugs through the landing pad and the conductor film, reducing the number of contacts between different layers. , which reduces the resistance of interlayer current transfer. In application, since the entire lower electrode is supported by the anchor-like structural part in the lower electrode, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance.

In a specific embodiment, the contact holes are filled with stacked contact plugs and the landing pads that are electrically connected to the stacked contact plugs are specifically: the contact holes are filled with stacked contact plugs; the contact holes are filled with The conductor film in contact with the stacked contact plugs; the contact holes are filled with landing pads in contact with the conductor film. After removing the landing pad, and before removing the partially stacked contact plug from top to bottom, the manufacturing method further includes removing the conductor film.

In a specific embodiment, the removal of the landing pad, the conductor film and the partially stacked contact plug is specifically: removing the landing pad, Conductor film and partially stacked contact plugs. to remove it without affecting other membranes.

In a specific embodiment, after the contact holes are filled with stacked contact plugs and the landing pads electrically connected to the stacked contact plugs, and before the landing pads are removed, the manufacturing method further includes: stacking a sacrificial layer on the insulating layer The film layer; the sacrificial film layer is provided with a capacitor hole communicating with the landing pad. The lower electrode is formed above the insulating layer, and the lower electrode extends downward into the contact hole and contacts with the remaining partially stacked contact plugs. Lower electrodes in contact with the remaining stacked contact plugs are formed on the end faces.

In a specific embodiment, forming a lower electrode in contact with the reserved stacked contact plug on the hole wall of the capacitor hole and the contact hole, and on the upper end surface of the reserved partial stacked contact plug is specifically: on the surface of the sacrificial film layer The lower electrode material layer is deposited on the hole wall of the capacitor hole and the contact hole, and the upper end surface of the reserved part of the stacked contact plug; the lower electrode material layer on the surface of the sacrificial film layer is removed to form a lower electrode in contact with the reserved stacked contact plug. . In order to facilitate the formation of the lower electrode, the strength of the contact between the lower electrode and the hole wall of the contact hole and the upper end surface of the remaining stacked contact plugs is improved, and the effect of supporting the entire lower electrode is improved.

In a specific embodiment, after the lower electrode is formed above the insulating layer, the manufacturing method further includes: removing the sacrificial film layer, so as to subsequently form a capacitor structure on both the inner and outer sides of the lower electrode, so as to improve the capacitance of the capacitor and improve the storage performance. .

Description of drawings

FIG. 1a is a schematic diagram of one of the steps of manufacturing a capacitor in the prior art;

FIG. 1b is a schematic diagram of another step in the process of manufacturing a capacitor in the prior art;

FIG. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

4 is a schematic diagram of another step in a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

5 is a schematic diagram of another step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Reference numerals in Figures 1a to 1b:

1-substrate 2-sacrificial film layer 3-capacitor hole 4-landing pad 5-bottom electrode

Reference numerals in Figures 2 to 6:

10-substrate 21-first insulating stack 211-stacking contact plugs 212-insulation

22-Second insulating laminate 221-Conductor film 222-Landing pad 223-Isolation

31-first contact hole 32-second contact hole 40-lower electrode 50-sacrificial film layer

60-capacitor hole 70-etch barrier 80-support layer 81-support structure

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In order to facilitate understanding of the semiconductor device provided by the embodiment of the present invention, the following first describes an application scenario of the semiconductor device provided by the embodiment of the present invention, where the semiconductor device is applied to a memory having a capacitor. The semiconductor device will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 2 , a semiconductor device provided by an embodiment of the present invention includes a substrate 10 , a first insulating stack 21 stacked on the substrate 10 , and a second insulating stack 22 stacked on the first insulating stack 21 . The first contact hole 31 is formed in the first insulating layer 21 , the first contact hole 31 is filled with stacked contact plugs 211 from bottom to top, and the stacked contact plug 211 is not filled with the first contact hole 31 . A second contact hole 32 communicating with the first contact hole 31 is opened in the second insulating stack 22 . The semiconductor device further includes a lower electrode 40 formed over the second insulating stack 22 , and the lower electrode 40 further extends downward into the second contact hole 32 and the first contact hole 31 in order to contact the stacked contact plugs 211 .

In the above solution, by removing the conductor film 221 in the second contact hole 32 and the landing pad 222 in contact with the conductor film 221, and also removing part of the stacked contact plug 211 in the first contact hole 31, the two The lower electrodes 40 above the insulating stacks also extend downward into the first contact holes 31 and the second contact holes 32 to contact the remaining stacked contact plugs 211 , so that the part of the lower electrode 40 in contact with the stacked contact plugs 211 is formed An anchor-like structure can support the entire lower electrode 40 and prevent the entire lower electrode 40 from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, the anchor-like structural portion in the lower electrode 40 can also prevent the entire lower electrode 40 from being bent and deformed, thereby preventing the capacitor from collapsing. Part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 can increase the surface area of the lower electrode 40 , thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And the lower electrode 40 extends down to the first contact hole 31 and the second contact hole 32 to directly contact with the remaining stacked contact plug 211, instead of the lower electrode 40 passing through the landing pad 222, the conductor film 221 and the stacked contact plug 211. The 211 contact method reduces the number of contacts between different layers and reduces the resistance of current transmission between layers. In application, since the entire lower electrode 40 is supported by the anchor-like structural part in the lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance. The settings of the above structures will be described in detail below with reference to the accompanying drawings.

When the substrate 10 is provided, the substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a laminated structure in which a part of the semiconductor structure has been formed. For example, the substrate 10 may include at least a semiconductor substrate, transistors, bit line structures, and the like. Transistors may be formed on semiconductor substrates of semiconductor devices. Bit line structures may be formed over the transistors.

Referring to FIG. 2 , a first insulating stack 21 is further stacked on top of the substrate 10 , and a first contact hole 31 is further opened in the first insulating stack 21 , that is, the first contact hole 31 is connected to the top of the first insulating stack 21 . surface and lower surface. The stacked contact plugs 211 are filled from bottom to top in the first contact holes 31 , and the stacked contact plugs 211 do not fill the first contact holes 31 . That is, the stacked contact plugs 211 are located at the lower ends of the first contact holes 31 , and the stacked contact plugs 211 do not fill the first contact holes 31 . When applied, the stacked contact plugs 211 are in contact with the source or drain regions of the transistors. Referring to FIG. 2 , insulating portions 212 for isolating adjacent two stacked contact plugs 211 are further formed in the first insulating stack 21 , and the stacked contact plugs 211 and the insulating portions 212 are formed between adjacent bit line structures.

Continuing to refer to FIG. 2 , a second insulating stack 22 is further stacked above the first insulating stack 21 , and a second contact hole 32 communicating with the first contact hole 31 is further opened in the second insulating stack 22 . That is, the second contact hole 32 penetrates through the upper and lower surfaces of the second insulating stack 22 , and the lower end of the second contact hole 32 is also communicated with the first contact hole 31 . The hole edges of the first contact hole 31 and the second contact hole 32 can be arranged to overlap, so that the size of the opening at the connection between the first contact hole 31 and the second contact hole 32 is equal, and the hole edges are coincident and opposite. The hole edges of the first contact hole 31 and the second contact hole 32 may also at least partially intersect, so that the first contact hole 31 and the second contact hole 32 are at least partially communicated. Of course, at the connection between the first contact hole 31 and the second contact hole 32, one contact hole has a large orifice, and the other contact hole has a small orifice, so that the contact hole with the small orifice is placed on the contact hole with the large orifice. in the contact hole.

As shown in FIG. 2 , when the lower electrode 40 is disposed, the lower electrode 40 mainly includes two parts, one of which is a part formed above the second insulating stack, and the part is exposed to the first contact hole 31 and the second contact hole 32 outside. The other portion is a portion extending downward to the second contact hole 32 and the first contact hole 31 in order to contact the stacked contact plugs 211 , and the portion is located in the first contact hole 31 and the second contact hole 32 .

The manufacturing method of a capacitor in the prior art is shown in FIG. 1a to FIG. 1b. Referring to FIG. 1a, first, a sacrificial film layer 2 is deposited on a substrate 1; after that, the sacrificial film layer 2 is etched to form a capacitor hole 3, and the capacitor hole 3 is connected to the substrate. The landing pad 4 in 1 is connected; after that, a lower electrode material layer is deposited on the sacrificial film layer 2, the inner wall of the capacitor hole 3 and the upper end surface of the landing pad 4; after that, referring to FIG. 1b, remove the lower electrode outside the capacitor hole 3 material layer to form the lower electrode 5; then, referring to FIG. 1b, the sacrificial film layer 2 is removed; subsequently, a dielectric layer and an upper electrode are deposited on the lower electrode 5 to form a capacitor. In the semiconductor device shown in FIG. 1b, the lower end of the lower electrode 5 is only in contact with the landing pad 4, and the contact area is relatively small, so that the foundation of the lower electrode 5 is poor, and it is easy to tilt, fall or even bend. After the sacrificial film layer 2 is removed, the lower electrode 5 is easily inclined or even toppled. When the dielectric layer and the upper electrode are deposited on the lower electrode 5, the lower electrode 4 is easily bent due to the weight of the dielectric layer and the upper electrode, thereby causing the collapse of the entire capacitor.

Compared with the solution in FIG. 1 b in the prior art, the solution in the present application removes the conductor film 221 in the second contact hole 32 and the landing pad 222 in contact with the conductor film 221 , and also removes the conductor film 222 in the first contact hole 31 . The contact plugs 211 are partially stacked, and the lower electrodes 40 to be formed above the two insulating stacks also extend down into the first contact holes 31 and the second contact holes 32 to contact the remaining stacked contact plugs 211, so as to make contact with the stacked contact plugs 211. The part of the lower electrode 40 in contact with the contact plug 211 forms an anchor-like structure, which can support the entire lower electrode 40 and prevent the entire lower electrode 40 from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, the anchor-like structural portion in the lower electrode 40 can also prevent the entire lower electrode 40 from being bent and deformed, thereby preventing the capacitor from collapsing. Part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 can increase the surface area of the lower electrode 40 , thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And the lower electrode 40 extends down to the first contact hole 31 and the second contact hole 32 to directly contact with the remaining stacked contact plug 211, instead of the lower electrode 40 passing through the landing pad 222, the conductor film 221 and the stacked contact plug 211. The 211 contact method reduces the number of contacts between different layers and reduces the resistance of current transmission between layers. In application, since the entire lower electrode 40 is supported by the anchor-like structural part in the lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance.

More specifically, when the portion of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 is brought into contact with the stacked contact plug 211 , the lower electrode 40 extending to the upper end surface of the stacked contact plug 211 can be deposited on the stacking contact plug 211 . The upper end surfaces of the stacked contact plugs 211 are stacked to improve the strength of the contact between the lower electrode 40 and the stacked contact plug 211 , and to improve the supporting effect for the entire lower electrode 40 . At the same time, the lower electrode 40 extending to the hole walls of the first contact hole 31 and the second contact hole 32 can also be deposited on the hole walls of the first contact hole 31 and the second contact hole 32, that is, the lower electrode 40 extends to the first contact hole 31 and the second contact hole 32. Parts in the first contact hole 31 and the second contact hole 32 are not only in contact with the stacked contact plugs 211, but also contact with the hole walls of the first contact hole 31 and the second contact hole 32. The contact area and contact strength of the lower electrode 40 with the two contact holes and the stacked contact plugs 211 improve the supporting effect for the entire lower electrode 40 .

When the lower electrode 40 is disposed, the shape of the lower electrode 40 may be a hollow cylindrical structure, and the cylindrical structure includes a thin-walled bottom and a side wall communicated with the bottom. The bottom wall of the lower electrode 40 can be deposited on the upper end surface of the stacked contact plug 211 , that is, the bottom of the lower electrode 40 can be deposited on the upper end surface of the stacked contact plug 211 . The sidewall of the lower electrode 40 is partially deposited on the hole walls of the first contact hole 31 and the second contact hole 32 , and is partially exposed outside the first contact hole 31 and the second contact hole 32 . That is, the part of the side wall of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32 is deposited on the hole walls of the first contact hole 31 and the second contact hole 32 and exposed to the first contact hole 31 and the second contact hole 32 . Portions of the two contact holes 32 stand vertically above the second insulating stack 22 . By adopting the cylindrical lower electrode 40, the surface area of the lower electrode 40 is increased, the charge storage capacity of the capacitor is increased, and the capacitance of the capacitor is increased.

When the dielectric layer and the upper electrode are formed on the lower electrode 40 , the upper electrode and the A dielectric layer that insulates and isolates the lower electrode 40 from the upper electrode to complete the fabrication of the capacitor. That is, the part of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32 is only formed with a dielectric layer and an upper electrode on the inner side wall and the bottom wall, and the lower electrode 40 is exposed to the first contact hole 31 and the second contact hole 31 and the second contact The portion outside the hole 32 is not only formed with a dielectric layer and an upper electrode on the inner sidewall, but also has a dielectric layer and an upper electrode formed on the outer sidewall. By arranging capacitor structures on both the inner and outer sides of the lower electrode 40, the charge storage capacity of the capacitor is increased, the capacitance of the capacitor is increased, and the storage effect is improved. It should be understood that the manner of disposing the dielectric layer and the upper electrode is not limited to the above manner, and other manners may also be used. For example, the dielectric layer and the upper electrode may be formed only on the inner sidewall and bottom wall of the lower electrode 40 , and the dielectric layer and the upper electrode may not be formed on the outer sidewall of the lower electrode 40 .

When determining the height of the stacked contact plugs 211 occupying the entire first contact hole 31 , it can be assumed that the height of the stacked contact plugs 211 is h1 , that is, between the lower surface of the stacked contact plugs 211 and the upper surface of the stacked contact plugs 211 The vertical distance of the first contact hole 31 is h1; the height of the first contact hole 31 is h2, that is, the vertical distance between the upper hole edge of the first contact hole 31 and the lower hole edge of the first contact hole 31 is h2. Can be set: 20%×h2≤h1≤80%×h2. Specifically, the heights of the stacked contact plugs 211 can be set to h1=20%×h2, h1=25%×h2, h1=30%×h2, h1=35%×h2, h1=40%×h2, h1=45 %×h2, h1=50%×h2, h1=55%×h2, h1=60%×h2, h1=65%×h2, h1=70%×h2, h1=75%×h2, h1=80% Any value such as ×h2 is between 20% and 80% of the height h2 of the first contact hole 31 . In order to ensure that the part of the lower electrode 40 extending into the first contact hole 31 has a larger contact surface with the side wall of the first contact hole 31 , and to ensure the supporting effect of the formed anchor-like structure on the entire lower electrode 40 . At the same time, the height of the stacked contact plugs 211 is ensured, so that the stacked contact plugs 211 and the lower electrode 40 have a relatively stable bonding state.

In addition, as shown in FIG. 2 , the shape of the second contact hole 32 can be set to a shape with a large upper end, a small middle, and a large lower end, and the first contact hole 31 can be set to be the same size as the opening at the lower end of the second contact hole 32 The apertures at the upper and lower ends of the first contact hole 31 may be equal in size, and the outer edge of the first contact hole 31 and the outer edge of the second contact hole 32 overlap. By adopting the above arrangement, the surface area of the lower electrode 40 in contact with the side wall of the second contact hole 32 is increased, and the supporting effect of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32 on the entire lower electrode 40 is improved. . In addition, the lower end of the first contact hole 31 is larger, which can increase the contact area between the lower electrode 40 and the stacked contact plug 211 and reduce the resistance of current transmission between layers. The upper end of the second contact hole 32 is large, so that the lower electrode 40 exposed outside the first contact hole 31 and the second contact hole 32 has a larger surface area, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage capacity. performance. Of course, both the first contact hole 31 and the second contact hole 32 can also be configured as a hollow cylindrical through hole.

Referring to FIG. 2 , an etching stopper layer 70 may be further deposited on the second insulating stack 22 , and at this time, the second contact hole 32 also penetrates the etching stopper layer 70 . By depositing an etch stop layer 70 on the second insulating stack 22, the substrate 10 and the two insulating stacks are prevented from being affected by subsequent operations such as etching or cleaning, thereby ensuring the quality of the substrate 10 and the insulating stacks. When determining the material of the etching barrier layer 70, the material of the etching barrier layer 70 can be selected from SiN, SiBN or SiCN, so as to improve the barrier effect during etching.

Direct contact between the first insulating stack 21 and the second insulating stack 22 may be made. It is also possible to deposit an etch stop layer between the first insulating stack 21 and the second insulating stack 22, that is, at this time, the first insulating stack 21 and the second insulating stack 22 are not directly stacked together, and between the two An etching barrier layer is also deposited therebetween. Correspondingly, at this time, a contact hole is also opened on the etching barrier layer between the first insulating stack 21 and the second insulating stack 22 to communicate with the first contact hole 31 and the second contact hole 32 . And the part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 is also deposited on the sidewalls of the contact holes opened on the etching barrier layer. By depositing an etch barrier layer between the two, in the manufacturing process, the etch barrier layer protects the first insulating stack 21 and the substrate 10, preventing subsequent operations such as etching or cleaning from affecting the substrate 10 and the substrate 10. The insulating stack affects the quality of the substrate 10 and the insulating stack.

As shown in FIG. 2 , a support structure 81 for supporting the lower electrode 40 may also be provided above the etching barrier layer 70 , and the support structure 81 surrounds the outer sidewall of the lower electrode 40 to improve the supporting effect for the lower electrode 40 . When specifically disposing the support structure 81 , the support structure 81 may be disposed at the upper end of the lower electrode 40 , or may be disposed at the intermediate position of the lower electrode 40 , and the support structure 81 may be disposed at different positions of the lower electrode 40 at the same time.

In determining the type of the semiconductor device, the semiconductor device may be a dynamic random access memory (DRAM) to prevent the collapse of capacitors in the DRAM due to inclination, bending, etc. of the lower electrode 40 . The semiconductor device may also be a memory using a capacitor as a storage unit, such as a Static Random-Access Memory (SRAM), a flash memory (flash memory), or the like.

By removing the conductor film 221 in the second contact hole 32 and the landing pad 222 in contact with the conductor film 221, and also removing part of the stacked contact plug 211 in the first contact hole 31, the conductive film 221 formed over the two insulating stacks will be removed. The lower electrode 40 also extends downward into the first contact hole 31 and the second contact hole 32 to contact the remaining stacked contact plugs 211, so that the part of the lower electrode 40 in contact with the stacked contact plugs 211 forms an anchor-like structure, The entire lower electrode 40 can be supported to prevent the entire lower electrode 40 from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, the anchor-like structural portion in the lower electrode 40 can also prevent the entire lower electrode 40 from being bent and deformed, thereby preventing the capacitor from collapsing. Part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 can increase the surface area of the lower electrode 40 , thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And the lower electrode 40 extends down to the first contact hole 31 and the second contact hole 32 to directly contact with the remaining stacked contact plug 211, instead of the lower electrode 40 passing through the landing pad 222, the conductor film 221 and the stacked contact plug 211. The 211 contact method reduces the number of contacts between different layers and reduces the resistance of current transmission between layers. In application, since the entire lower electrode 40 is supported by the anchor-like structural part in the lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance.

In addition, an embodiment of the present invention also provides a method for manufacturing a semiconductor device, the method comprising:

Step 1: provide a substrate 10;

Step 2: stacking an insulating layer on the substrate 10;

Step 3: opening a contact hole in the insulating layer;

Step 4: Filling the contact holes with stacked contact plugs 211 and landing pads 222 conductively connected to the stacked contact plugs 211;

Step 5: remove the landing pad 222;

Step 6: Remove some of the stacked contact plugs 211 from top to bottom;

Step 7: The lower electrode 40 is formed above the insulating layer, and the lower electrode 40 also extends downward into the contact hole to contact the remaining stacked contact plugs 211 .

In the above solution, by removing the landing pads 222 in the contact holes and also removing part of the stacked contact plugs 211 in the contact holes, the lower electrodes 40 formed above the insulating layer also extend down into the contact holes and remain The stacked contact plugs 211 are in contact with each other, so that the part of the lower electrode 40 in contact with the stacked contact plugs 211 forms an anchor-like structure, which can support the entire lower electrode 40 and prevent the entire lower electrode 40 from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, the anchor-like structural portion in the lower electrode 40 can also prevent the entire lower electrode 40 from being bent and deformed, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the contact hole can increase the surface area of the lower electrode 40, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And through the lower electrode 40 extending down to the contact hole, it directly contacts with the remaining stacked contact plugs 211, instead of the way that the lower electrode 40 contacts the stacked contact plugs 211 through the landing pad 222 and the conductor film 221, reducing the number of different layers. The number of contacts between them reduces the resistance of current transmission between layers. In application, since the entire lower electrode 40 is supported by the anchor-like structural part in the lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance. The specific operations of the above steps will be described in detail below with reference to the accompanying drawings.

First, referring to FIG. 3 , a substrate 10 is provided, and the substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10 , a polycrystalline silicon substrate 10 and the like. The substrate 10 may also be a laminated structure in which a part of the semiconductor structure has been formed. For example, the substrate 10 may include at least a semiconductor substrate, transistors, bit line structures, and the like. Transistors may be formed on semiconductor substrates of semiconductor devices. Bit line structures may be formed over the transistors.

Next, an insulating layer is laminated on the substrate 10 . Referring to FIG. 3 , the insulating layer may be a layer structure formed by one deposition, or may be formed by two depositions of the first insulating layer 21 and the second insulating layer 22 as mentioned in the foregoing description of the semiconductor device. layer structure. Of course, the insulating layer can also be a layer structure composed of the first insulating layer 21 and the second insulating layer 22, and an etching barrier layer therebetween. In this case, the insulating layer is deposited at least three times to form a layer structure. .

Next, contact holes are formed on the insulating layer. The contact hole may be a through hole opened on the insulating layer formed by one deposition, or may be a through hole formed on the insulating layer formed by at least two depositions. Referring to FIG. 3 , when the insulating layer is formed by stacking the aforementioned first insulating layer 21 and second insulating layer 22 , the contact hole includes a first contact hole 31 located below and a second contact hole 32 located above.

Next, referring to FIG. 3 , the contact holes are filled with stacked contact plugs 211 , and landing pads 222 electrically connected to the stacked contact plugs 211 . Specifically, referring to FIG. 3 , the contact holes may be filled with stacked contact plugs first; then, the contact holes may be filled with conductor films in contact with the stacked contact plugs; then, the contact holes may be filled with conductor films in contact with the conductor films. landing pads. That is, the contact plugs 211 , the conductor films 221 and the landing pads 222 are stacked from bottom to top and filled in the contact holes in sequence. The material of the conductor film 221 may be metal silicide, and the material of the landing pad 222 may be a metal material, so as to increase the electrical conductivity between the landing pad 24 and the stacked contact plug 11 .

In the substrate 10 shown in FIG. 3 , the stacked contact plugs 211 are filled with the first contact holes 31 , the conductor film 221 and the landing pads 222 are filled in the second contact holes 32 , and the conductor film 221 and the landing pads are filled in the second contact holes 32 . 222 fills the second contact hole 32 . The conductor film 221 is in contact with the stacked contact plugs 211 , and the landing pads 222 are in contact with the conductor film 221 .

When applied, the stacked contact plugs 211 are in contact with the source or drain regions of the transistors. Each landing pad 222 is formed on its corresponding stacked contact plug 211 . The landing pad 222 is electrically connected to the source region or the drain region of the transistor through the conductor film 221 and the stacked contact plug 211 . Referring to FIG. 3 , insulating portions 212 for isolating adjacent two stacked contact plugs 211 are further formed in the first insulating stack 21 , and the stacked contact plugs 211 and the insulating portions 212 are formed between adjacent bit line structures. An isolation part 223 is also formed in the second insulating stack 22 , and the isolation part 223 is used to isolate two adjacent landing pads 222 .

Next, referring to FIG. 4 , the landing pads 222 are removed. When removing the landing pad 222, the landing pad 222 may be removed by wet etching or a remote plasma dry cleaning process, so as to be removed without affecting other film qualities. Referring to FIG. 5 , when the contact holes are filled with stacked contact plugs 211 , conductor films 221 and landing pads 222 in order from bottom to top, the conductor films 221 may also be removed. When removing the conductor film 221, the conductor film 221 may be removed by wet etching or remote plasma dry cleaning process, so as to be removed without affecting other film qualities.

Next, referring to FIG. 6 , the partially stacked contact plugs 211 are removed from top to bottom. During specific removal, wet etching or remote plasma dry cleaning process may be used to remove some of the stacked contact plugs 211 in the contact holes from top to bottom, so as to remove them without affecting other film qualities. When removing the stacked contact plugs 211 in the contact holes, it is also necessary to retain a part of the stacked contact plugs 211 , and the partially stacked contact plugs 211 are located at the bottom of the contact holes, so that the lower electrodes 40 formed subsequently can be connected with the remaining stacked contact plugs. The contact plug 211 contacts.

Next, referring to FIG. 2 , the lower electrode 40 is formed over the insulating layer, and the lower electrode 40 also extends downward into the contact hole to make contact with the remaining stacked contact plugs 211 . Specifically, referring to FIG. 3 , after the contact holes are filled with the stacked contact plugs 211 and the landing pads 222 electrically connected to the stacked contact plugs 211 , and before the landing pads 222 are removed, a sacrificial layer may be stacked on the insulating layer. In the film layer 50 , the sacrificial film layer 50 is provided with a capacitor hole 60 that communicates with the landing pad 222 . When depositing the sacrificial film layer 50 on the insulating layer, the sacrificial film layer 50 may be directly deposited on the insulating layer. An etch barrier layer 70 may also be deposited between the sacrificial film layer 50 and the insulating layer. In this case, the capacitor hole 60 penetrates through the sacrificial film layer 50 and the etch barrier layer 70 and communicates with the landing pad 222 . By depositing the etch barrier layer 70 between the sacrificial film layer 50 and the insulating layer, after the sacrificial film layer 50 is removed in a subsequent process, the etch barrier layer 70 can prevent subsequent operations such as etching or cleaning from affecting the substrate 10 and the insulating layer. This affects the quality of the substrate 10 and the insulating layer.

As shown in FIG. 3 , at least one supporting layer 80 may also be formed inside or above the sacrificial film layer 50 . In this case, the capacitor hole 60 not only penetrates the sacrificial film layer 50 and the etching barrier layer 70 , but also penetrates each supporting layer. Layer 80 then communicates with landing pads 222 . After the lower electrode 40 is formed in the subsequent process, during the process of removing the sacrificial film layer 50 , part of the support layer 80 is also removed, and the remaining part of the support layer 80 serves as the support structure 81 to support the lower electrode 40 .

When the lower electrode 40 is formed above the insulating layer, the lower electrode 40 in contact with the stacked contact plug 211 may be formed on the capacitor hole 60 and the hole wall of the contact hole, and the upper end surface of the remaining part of the stacked contact plug 211 . Specifically, first, a lower electrode material layer may be deposited on the surface of the sacrificial film layer 50 , the hole walls of the capacitor hole 60 and the contact hole, and the upper end surface of the remaining part of the stacked contact plug 211 . After that, the lower electrode material layer on the surface of the sacrificial film layer 50 is removed to form the lower electrode 40 in contact with the remaining partially stacked contact plugs 211. Specifically, the surface of the sacrificial film layer 50 can be removed by plasma etching or wet etching. the lower electrode material layer. As shown in FIG. 6 , if the support layer 80 is deposited above the sacrificial film layer 50 , at this time, the lower electrode material layer is not deposited on the surface of the sacrificial film layer 50 , but is deposited on the surface of the top support layer 80 . Likewise, instead of removing the lower electrode material layer on the surface of the sacrificial film layer 50 , the lower electrode material layer on the surface of the top support layer 80 is removed. The lower electrode 40 is formed by deposition, so as to facilitate the formation of the lower electrode 40 and improve the contact strength between the lower electrode 40 and the hole wall of the contact hole and the upper end face of the stacked contact plug 211 , thereby improving the support for the entire lower electrode 40 . Effect.

After the lower electrode 40 is formed, the sacrificial film layer 50 may also be removed to form the semiconductor device shown in FIG. 2 . Specifically, the sacrificial film layer 50 may be removed by means of plasma etching or wet etching. When at least one supporting layer 80 is further formed in the sacrificial film layer 50 , part of the supporting layer 80 of each supporting layer 80 needs to be removed, and part of the supporting layer 80 connected to the outer wall of the lower electrode 40 in each layer is retained. , as the supporting structure 81 for supporting the lower electrode 40 , and the supporting structure 81 surrounds the outer wall of the lower electrode 40 at least once.

By removing the landing pads 222 in the contact holes and also removing part of the stacked contact plugs 211 in the contact holes, the lower electrodes 40 to be formed over the insulating layer also extend down into the contact holes and the remaining stacked contact plugs 211 contact, so that the part of the lower electrode 40 in contact with the stacked contact plugs 211 forms an anchor-like structure, which can support the entire lower electrode 40 and prevent the entire lower electrode 40 from tilting. When the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, the anchor-like structural portion in the lower electrode 40 can also prevent the entire lower electrode 40 from being bent and deformed, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the contact hole can increase the surface area of the lower electrode 40, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor, and improving the storage performance. And through the lower electrode 40 extending down to the contact hole, it directly contacts with the remaining stacked contact plugs 211, instead of the way that the lower electrode 40 contacts the stacked contact plugs 211 through the landing pad 222 and the conductor film 221, reducing the number of different layers. The number of contacts between them reduces the resistance of current transmission between layers. In application, since the entire lower electrode 40 is supported by the anchor-like structural part in the lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be appropriately increased to increase the capacitance of the capacitor and further improve the storage performance.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a first insulating laminated layer laminated on the substrate, wherein a first contact hole is formed in the first insulating laminated layer; wherein the first contact hole is filled with a stacked contact plug from bottom to top, and the stacked contact plug does not fill the first contact hole;

a second insulating laminated layer laminated on the first insulating laminated layer, wherein a second contact hole communicated with the first contact hole is formed in the second insulating laminated layer;

a lower electrode formed over the second insulating stack, and the lower electrode also extends down into the second contact hole and the first contact hole in sequence to contact the stacked contact plug.

2. The semiconductor device according to claim 1, wherein the lower electrode extending to the hole walls of the second contact hole and the first contact hole is deposited on the hole walls of the first contact hole and the second contact hole;

the lower electrode extending to the upper end face of the stacked contact plug is deposited on the upper end face of the stacked contact plug.

3. The semiconductor device according to claim 1, wherein the lower electrode is cylindrical in shape; wherein a bottom wall of the lower electrode is deposited on an upper end face of the stacked contact plug; the side wall part of the lower electrode is deposited on the hole walls of the first contact hole and the second contact hole, and part of the side wall part of the lower electrode is exposed out of the first contact hole and the second contact hole.

4. The semiconductor device of claim 1, wherein an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode are formed on the bottom wall and the inner side wall of the lower electrode and the outer side wall exposed outside the first contact hole and the second contact hole.

5. The semiconductor device according to claim 1, wherein a height of the stacked contact plug is h1, and a height of the first contact hole is h2, wherein 20% xh 2 ≦ h1 ≦ 80% xh 2.

6. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

laminating an insulating layer on the substrate;

forming a contact hole in the insulating layer;

the contact hole is filled with a stacked contact plug and a landing pad which is in conductive connection with the stacked contact plug;

removing the landing pad;

removing part of the stacked contact plug from top to bottom;

a lower electrode is formed over the insulating layer and also extends down into the contact hole to contact a remaining portion of the stacked contact plug.

7. The manufacturing method according to claim 6, wherein the filling of the contact hole with the stacked contact plug and the landing pad conductively connected to the stacked contact plug are embodied as follows:

filling and stacking contact plugs in the contact holes;

filling a conductor film in contact with the stacked contact plug in the contact hole;

filling a landing pad in contact with the conductor film in the contact hole;

after the removing the landing pad, before removing a portion of the stacked contact plug from top to bottom, the manufacturing method further includes: and removing the conductor film.

8. The manufacturing method according to claim 7, wherein the removing the landing pad, the conductor film and a portion of the stacked contact plug is embodied by: and removing the landing pad, the conductor film and part of the stacked contact plug in the contact hole from top to bottom by adopting a wet etching or remote plasma dry cleaning process.

9. The method of manufacturing of claim 6, wherein after filling the contact hole with a stacked contact plug, a landing pad conductively connected to the stacked contact plug, and before removing the landing pad, the method further comprises:

laminating a sacrificial film layer on the insulating layer;

a capacitor hole communicated with the landing pad is formed in the sacrificial film layer;

the step of forming the lower electrode above the insulating layer and extending the lower electrode downward into the contact hole to contact with the remaining part of the stacked contact plug is specifically as follows:

and forming lower electrodes which are contacted with the retained stacked contact plugs on the hole walls of the capacitor holes and the contact holes and the upper end surfaces of the retained part of the stacked contact plugs.

10. The manufacturing method according to claim 9, wherein the forming of the lower electrode in contact with the remaining stacked contact plug on the hole wall of the capacitor hole and the contact hole and the upper end surface of the remaining portion of the stacked contact plug is specifically:

depositing a lower electrode material layer on the surface of the sacrificial film layer, the wall of the capacitor hole and the wall of the contact hole and the upper end surface of the reserved part of the stacked contact plug;

and removing the lower electrode material layer on the surface of the sacrificial film layer to form a lower electrode in contact with the preserved stacking contact plug.

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