CN114334977A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A first contact hole is formed in the first insulation lamination layer, a stacked contact plug is filled in the first contact hole from bottom to top, and the stacked contact plug is not filled in the first contact hole. A second contact hole communicated with the first contact hole is formed in the second insulating laminated layer. The lower electrode is formed above the second insulating lamination layer, and the lower electrode further extends downwards to the second contact hole and the first contact hole in sequence to be contacted with the stacked contact plug. And the lower electrodes formed above the two insulating laminated layers also extend downwards into the first contact hole and the second contact hole to be contacted with the reserved stacking contact plugs, so that the partial lower electrodes contacted with the stacking contact plugs form a structure similar to an anchor, and the whole lower electrode is supported to prevent the whole lower electrode from inclining. The surface area of the lower electrode is increased, and the capacitance of the capacitor is improved.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background

A Capacitor (Capacitor) is a component that can store electricity and electrical energy. Different amounts of charge can be stored in the capacitor by applying different voltages across the two electrodes of the capacitor. On this basis, the storage of different data can be realized by a capacitor. It follows that the quality of the capacitor directly affects the data storage performance of the semiconductor device.

In order to improve the driving performance of the memory, the capacitance of the capacitor needs to be increased. A common way to increase the capacitance of a capacitor is to increase the height of the capacitor. However, the height of the capacitor is increased, which results in an increase in the Aspect Ratio (Aspect Ratio) of the capacitor. The aspect ratio of the capacitor is increased, and the problems of capacitor inclination, bending and even collapse are easy to occur when Wet cleaning process is performed.

Disclosure of Invention

The invention provides a semiconductor device and a manufacturing method thereof, which can effectively improve the charge storage capacity of a capacitor and simultaneously can effectively prevent the capacitor from inclining, bending or collapsing.

In a first aspect, the present invention provides a semiconductor device including a substrate, a first insulating stack layer stacked on the substrate, and a second insulating stack layer stacked on the first insulating stack layer. The first insulating laminated layer is provided with a first contact hole, the first contact hole is filled with a stacked contact plug from bottom to top, and the stacked contact plug is not filled with the first contact hole. A second contact hole communicated with the first contact hole is formed in the second insulating laminated layer. The semiconductor device further includes a lower electrode formed over the second insulating stack, and the lower electrode further extends down into the second contact hole and the first contact hole in sequence to contact the stacked contact plug.

In the above solution, by removing the conductive film in the second Contact hole and the Landing Pad (LP) in Contact with the conductive film, and also removing a part of the stacked Contact plug (BC) in the first Contact hole, the lower electrode formed above the two insulating stacked layers is further extended downward into the first Contact hole and the second Contact hole to Contact with the remaining stacked Contact plug, so that the part of the lower electrode in Contact with the stacked Contact plug forms a structure similar to an anchor, which can support the entire lower electrode and prevent the entire lower electrode from tilting. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure part in the lower electrode can also prevent the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. And the part of the lower electrode extending into the first contact hole and the second contact hole can increase the surface area of the lower electrode, thereby improving the charge storage capacity of the capacitor, improving the capacitance of the capacitor and improving the storage performance. And the lower electrode extends downwards to the first contact hole and the second contact hole to be directly contacted with the reserved stacking contact plug, so that the mode that the lower electrode is contacted with the stacking contact plug through the landing pad and the conductor film is replaced, the number of contacts among different layers is reduced, and the resistance of interlayer current transmission is reduced. When the capacitor is applied, the whole lower electrode is supported by the anchor-like structure part in the lower electrode, so that the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is further improved.

In one embodiment, the lower electrode extending to the second contact hole and the hole wall of the first contact hole is deposited on the hole walls of the first contact hole and the second contact hole, and the lower electrode extending to the upper end face of the stacked contact plug is deposited on the upper end face of the stacked contact plug, so that the contact strength of the lower electrode with the hole wall of the contact hole and the stacked contact plug is improved, and the supporting effect on the whole lower electrode is improved.

In a specific embodiment, the lower electrode is formed in a cylindrical shape; wherein the bottom wall of the lower electrode is deposited on the upper end face of the stacked contact plug; the side wall part of the lower electrode is deposited on the hole walls of the first contact hole and the second contact hole, and part of the side wall part is exposed out of the first contact hole and the second contact hole. By adopting the cylindrical lower electrode, the surface area of the lower electrode is increased, the charge storage capacity of the capacitor is increased, and the capacitance of the capacitor is increased.

In one embodiment, an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode are formed on the bottom wall and the inner side wall of the lower electrode and the outer side wall exposed outside the first contact hole and the second contact hole. All set up the capacitor structure through the inside and outside at the bottom electrode to improve the electric charge memory capacity of condenser, improve the electric capacity of condenser, improve the storage effect.

In a specific embodiment, the height of the stacked contact plug is h1, and the height of the first contact hole is h2, wherein 20% x h2 is less than or equal to h1 is less than or equal to 80% x h 2. So as to ensure that the part of the lower electrode extending into the first contact hole and the side wall of the first contact hole have larger contact surfaces, and ensure the supporting effect of the formed structure similar to an anchor on the whole lower electrode. Meanwhile, the height of the stacked contact plug is ensured, so that the stacked contact plug and the lower electrode have a stable bonding state.

In a specific embodiment, an etch stop layer is further deposited on the second insulating stack, and the second contact hole further extends through the etch stop layer. By depositing the etching barrier layer on the second insulating lamination, the influence of subsequent operations such as etching or cleaning on the substrate is prevented, and the quality of the substrate and the insulating lamination is ensured.

In a specific embodiment, the semiconductor device is a dynamic random access memory to prevent collapse of a capacitor in the dynamic random access memory due to inclination, bending, or the like of a lower electrode.

In a second aspect, the present invention also provides a method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

laminating an insulating layer on a substrate;

forming a contact hole in the insulating layer;

the contact hole is filled with a stacked contact plug and a landing pad which is conductively connected with the stacked contact plug;

removing the landing pad;

removing part of the stacked contact plugs from top to bottom;

a lower electrode is formed over the insulating layer and also extends down into the contact hole to contact the remaining stacked contact plug.

In the above solution, by removing the landing pad in the contact hole and also removing part of the stacked contact plug in the contact hole, the lower electrode formed above the insulating layer is further extended downward into the contact hole to contact with the remaining stacked contact plug, so that the part of the lower electrode in contact with the stacked contact plug forms a structure similar to an anchor, which can support the whole lower electrode and prevent the whole lower electrode from tilting. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the anchor-like structure part in the lower electrode can also prevent the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. And the part of the lower electrode extending into the contact hole can increase the surface area of the lower electrode, thereby improving the charge storage capacity of the capacitor, improving the capacitance of the capacitor and improving the storage performance. And the lower electrode extends downwards to the contact hole to be directly contacted with the reserved stacking contact plug, so that the mode that the lower electrode is contacted with the stacking contact plug through the landing pad and the conductor film is replaced, the contact number among different layers is reduced, and the resistance of interlayer current transmission is reduced. When the capacitor is applied, the whole lower electrode is supported by the anchor-like structure part in the lower electrode, so that the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is further improved.

In a specific embodiment, the landing pad filled with the stacked contact plug in the contact hole and conductively connected with the stacked contact plug is specifically: the contact hole is filled with a stacked contact plug; filling a conductor film in contact with the stacked contact plug in the contact hole; the contact hole is filled with a landing pad in contact with the conductor film. After removing the landing pad, before removing a part of the stacked contact plugs from above, the manufacturing method further includes: the conductor film is removed.

In one embodiment, the removing the landing pad, the conductor film and the partially stacked contact plug is: and removing the landing pad, the conductor film and part of the stacked contact plug in the contact hole from top to bottom by adopting a wet etching or remote plasma dry cleaning process. To remove it without affecting the other film qualities.

In a specific embodiment, after the contact hole is filled with the stacked contact plug and the landing pad conductively connected with the stacked contact plug, and before the landing pad is removed, the manufacturing method further comprises: laminating a sacrificial film layer on the insulating layer; a capacitor hole communicated with the landing pad is formed in the sacrificial film layer. Forming a lower electrode above the insulating layer, wherein the lower electrode extends downwards into the contact hole to be contacted with the reserved part of the stacked contact plug: and forming lower electrodes which are contacted with the reserved stacking contact plugs on the hole walls of the capacitor holes and the contact holes and the upper end surfaces of the reserved part of the stacking contact plugs.

In a specific embodiment, the lower electrode formed on the wall of the capacitor hole and the contact hole and on the upper end surface of the remaining part of the stacked contact plug and in contact with the remaining stacked contact plug is specifically: depositing a lower electrode material layer on the surface of the sacrificial film layer, the wall of the capacitor hole and the contact hole and the upper end surface of the reserved part of the stacked contact plug; and removing the lower electrode material layer on the surface of the sacrificial film layer to form a lower electrode in contact with the retained stacked contact plug. So as to form the lower electrode, improve the contact strength of the lower electrode, the hole wall of the contact hole and the upper end face of the retained stacked contact plug, and improve the effect of supporting the whole lower electrode.

In one specific embodiment, after forming the lower electrode over the insulating layer, the manufacturing method further includes: and removing the sacrificial film layer so as to form a capacitor structure on the inner side and the outer side of the lower electrode in the follow-up process, thereby improving the capacitance of the capacitor and the storage performance.

Drawings

FIG. 1a is a schematic diagram of one step in the prior art process for fabricating a capacitor;

FIG. 1b is a schematic diagram of another prior art process for fabricating a capacitor;

fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 4 is a schematic view of another step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;

fig. 5 is a schematic view of another step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;

fig. 6 is a schematic diagram illustrating another step in the method for manufacturing the semiconductor device according to the embodiment of the present invention.

Reference numerals in fig. 1a to 1 b:

1-substrate 2-sacrificial film layer 3-capacitor hole 4-landing pad 5-bottom electrode

Reference numerals in fig. 2 to 6:

10-substrate 21-first insulating stack 211-stacked contact plug 212-insulation part

22-second insulating stack 221-conductor film 222-landing pad 223-isolation

31-first contact hole 32-second contact hole 40-lower electrode 50-sacrificial film layer

60-capacitor hole 70-etching barrier layer 80-supporting layer 81-supporting structure

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

To facilitate understanding of the semiconductor device provided in the embodiment of the present invention, an application scenario of the semiconductor device provided in the embodiment of the present invention, which is applied to a memory having a capacitor, is first described below. The semiconductor device will be described in detail with reference to the drawings.

Referring to fig. 2, a semiconductor device according to an embodiment of the present invention includes a substrate 10, a first insulating stack 21 stacked on the substrate 10, and a second insulating stack 22 stacked on the first insulating stack 21. The first insulating stack 21 has a first contact hole 31 opened therein, the first contact hole 31 is filled with a stacked contact plug 211 from bottom to top, and the stacked contact plug 211 does not fill the first contact hole 31. A second contact hole 32 communicating with the first contact hole 31 is opened in the second insulating stack 22. The semiconductor device further includes a lower electrode 40 formed over the second insulating stack 22, and the lower electrode 40 further extends down into the second contact hole 32 and the first contact hole 31 in sequence to contact the stacked contact plug 211.

In the above-described embodiment, by removing the conductive film 221 in the second contact hole 32 and the landing pad 222 in contact with the conductive film 221, and also removing part of the stacked contact plug 211 in the first contact hole 31, the lower electrode 40 formed above the two insulating stacked layers is extended downward into the first contact hole 31 and the second contact hole 32 to be in contact with the remaining stacked contact plug 211, and the part of the lower electrode 40 in contact with the stacked contact plug 211 is formed into an anchor-like structure, so that the entire lower electrode 40 can be supported, and the entire lower electrode 40 can be prevented from being inclined. The anchor-like structure portion of the lower electrode 40 also prevents the entire lower electrode 40 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 can increase the surface area of the lower electrode 40, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor and improving the storage performance. And the lower electrode 40 extends downwards to the first contact hole 31 and the second contact hole 32 to be directly contacted with the reserved stacking contact plug 211, so that the mode that the lower electrode 40 is contacted with the stacking contact plug 211 through the landing pad 222 and the conductor film 221 is replaced, the contact number among different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance. The arrangement of the above-described structures will be described in detail with reference to the accompanying drawings.

When the substrate 10 is disposed, the substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, the base 10 may include at least a semiconductor substrate, a transistor, a bit line structure, and the like. The transistor may be formed on a semiconductor substrate of a semiconductor device. A bitline structure may be formed over the transistor.

Referring to fig. 2, a first insulating stack 21 is further stacked above the substrate 10, and a first contact hole 31 is further formed in the first insulating stack 21, i.e., the first contact hole 31 communicates with an upper surface and a lower surface of the first insulating stack 21. The stacked contact plug 211 is filled in the first contact hole 31 from the bottom to the top, and the stacked contact plug 211 does not fill the first contact hole 31. That is, the stacked contact plug 211 is located at the lower end within the first contact hole 31, and the stacked contact plug 211 does not fill the first contact hole 31. In application, the stacked contact plug 211 is in contact with a source region or a drain region of a transistor. Referring to fig. 2, an insulating portion 212 that separates adjacent two stacked contact plugs 211 is also formed in the first insulating stack 21, and the stacked contact plugs 211 and the insulating portion 212 are formed between adjacent bit line structures.

With continued reference to fig. 2, a second insulating stack 22 is further stacked above the first insulating stack 21, and a second contact hole 32 communicating with the first contact hole 31 is further opened in the second insulating stack 22. That is, the second contact hole 32 penetrates the upper and lower surfaces of the second insulation stack 22, and the lower end of the second contact hole 32 is also communicated with the first contact hole 31. The hole edges of the first contact hole 31 and the second contact hole 32 can be overlapped, so that the aperture size of the joint of the first contact hole 31 and the second contact hole 32 is equal, and the hole edges are overlapped and opposite. The aperture edges of the first contact aperture 31 and the second contact aperture 32 may also at least partially intersect such that the first contact aperture 31 is at least partially in communication with the second contact aperture 32. Of course, it is also possible to make the connection between the first contact hole 31 and the second contact hole 32, where the aperture of one contact hole is large and the aperture of the other contact hole is small, so that the contact hole with the small aperture is sleeved in the contact hole with the large aperture.

As shown in fig. 2, when the lower electrode 40 is disposed, the lower electrode 40 mainly includes two portions, one of which is a portion formed above the second insulating stack and exposed outside the first contact hole 31 and the second contact hole 32. The other portion is a portion which extends downward into the second contact hole 32 and the first contact hole 31 in this order and contacts the stacked contact plug 211, and is located in the first contact hole 31 and the second contact hole 32.

Referring to fig. 1a, a method for manufacturing a capacitor in the prior art is shown in fig. 1a to 1b, first depositing a sacrificial film layer 2 on a substrate 1; then, etching the sacrificial film layer 2 to form a capacitor hole 3, wherein the capacitor hole 3 is communicated with a landing pad 4 in the substrate 1; then, depositing a lower electrode material layer on the sacrificial film layer 2, the inner wall of the capacitor hole 3 and the upper end surface of the landing pad 4; thereafter, referring to fig. 1b, the lower electrode material layer except the capacitor hole 3 is removed to form a lower electrode 5; thereafter, referring to fig. 1b, the sacrificial film layer 2 is removed; and depositing a dielectric layer and an upper electrode on the lower electrode 5 to form a capacitor. As shown in fig. 1b, the lower end of the lower electrode 5 is only in contact with the landing pad 4, and the contact area is relatively small, so that the lower electrode 5 has a poor base and is prone to tilt, topple or even bend. After the sacrificial film layer 2 is removed, the lower electrode 5 is easily tilted or even toppled. When the dielectric layer and the upper electrode are deposited on the lower electrode 5, the lower electrode 4 is easily bent due to the weight of the dielectric layer and the upper electrode, thereby causing the collapse of the entire capacitor.

Compared with the scheme in the prior art shown in fig. 1b, the scheme in the application removes the conductor film 221 in the second contact hole 32 and the landing pad 222 in contact with the conductor film 221, also removes a part of the stacked contact plug 211 in the first contact hole 31, extends the lower electrode 40 formed above the two insulating stacked layers downwards into the first contact hole 31 and the second contact hole 32 to be in contact with the remaining stacked contact plug 211, and enables a part of the lower electrode 40 in contact with the stacked contact plug 211 to form an anchor-like structure, so that the whole lower electrode 40 can be supported, and the whole lower electrode 40 is prevented from being inclined. The anchor-like structure portion of the lower electrode 40 also prevents the entire lower electrode 40 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 can increase the surface area of the lower electrode 40, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor and improving the storage performance. And the lower electrode 40 extends downwards to the first contact hole 31 and the second contact hole 32 to be directly contacted with the reserved stacking contact plug 211, so that the mode that the lower electrode 40 is contacted with the stacking contact plug 211 through the landing pad 222 and the conductor film 221 is replaced, the contact number among different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance.

More specifically, when the portion of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 is in contact with the stacked contact plug 211, the lower electrode 40 extending to the upper end surface of the stacked contact plug 211 may be deposited on the upper end surface of the stacked contact plug 211, so as to improve the contact strength between the lower electrode 40 and the stacked contact plug 211, and improve the supporting effect on the entire lower electrode 40. Meanwhile, the lower electrode 40 extending to the hole walls of the first contact hole 31 and the second contact hole 32 can be deposited on the hole walls of the first contact hole 31 and the second contact hole 32, that is, the part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 is not only in contact with the stacked contact plug 211, but also in contact with the hole walls of the first contact hole 31 and the second contact hole 32, and the deposition mode is adopted in the contact mode, so that the contact area and the contact strength of the lower electrode 40 with the two contact holes and the stacked contact plug 211 are improved, and the support effect on the whole lower electrode 40 is improved.

When the lower electrode 40 is provided, the lower electrode 40 may be shaped as a hollow cylindrical structure including a thin-walled bottom and a sidewall communicating with the bottom. The bottom wall of the lower electrode 40 may be deposited on the upper end face of the stacked contact plug 211, that is, the bottom of the lower electrode 40 is deposited on the upper end face of the stacked contact plug 211. Sidewall portions of the bottom electrode 40 are deposited on the hole walls of the first contact hole 31 and the second contact hole 32, and are partially exposed out of the first contact hole 31 and the second contact hole 32. That is, the portions of the sidewalls of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32 are deposited on the hole walls of the first contact hole 31 and the second contact hole 32, and the portions exposed out of the first contact hole 31 and the second contact hole 32 vertically stand above the second insulating stack 22. By using the cylindrical lower electrode 40, the surface area of the lower electrode 40 is increased, the charge storage amount of the capacitor is increased, and the capacitance of the capacitor is increased.

When a dielectric layer and an upper electrode are formed on the lower electrode 40, the upper electrode and the dielectric layer for insulating and isolating the lower electrode 40 from the upper electrode may be formed on the bottom wall, the inner sidewall of the lower electrode 40 and the outer sidewall exposed outside the first contact hole 31 and the second contact hole 32, so as to complete the manufacture of the capacitor. That is, the dielectric layer and the upper electrode are formed only on the inner sidewall and the bottom wall of the portion of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32, and the portion of the lower electrode 40 exposed out of the first contact hole 31 and the second contact hole 32 is formed not only on the inner sidewall but also on the outer sidewall. The capacitor structures are arranged on the inner side and the outer side of the lower electrode 40, so that the charge storage capacity of the capacitor is improved, the capacitance of the capacitor is improved, and the storage effect is improved. It should be understood that the manner of providing the dielectric layer and the upper electrode is not limited to the above-described manner, and other manners may be adopted. For example, the dielectric layer and the upper electrode may be formed only on the inner wall and the bottom wall of the lower electrode 40, and the dielectric layer and the upper electrode may not be formed on the outer wall of the lower electrode 40.

In determining the height of the stacked contact plug 211 over the entire first contact hole 31, it may be assumed that the height of the stacked contact plug 211 is h1, i.e., the vertical distance between the lower surface of the stacked contact plug 211 and the upper surface of the stacked contact plug 211 is h 1; the height of the first contact hole 31 is h2, i.e., the vertical distance from the upper edge of the first contact hole 31 to the lower edge of the first contact hole 31 is h 2. It is possible to provide: h1 is more than or equal to 20% and less than or equal to h2 and less than or equal to 80% and less than or equal to h 2. Specifically, any value between 20% and 80% of the height h1 of the first contact hole 31 may be set, such as 20% × h2, 25% × h2, 25% × h2, 35% × h2, 40% × h2, 40% × h1, 45% × h2, 50% × h2, 55% × h2, 60% × h 367, 65% × h1, 70% × h1, 75% × h1, and 80% × h1, of the height h 3642 of the stacked contact plug 211. So as to ensure that the part of the lower electrode 40 extending into the first contact hole 31 has a larger contact surface with the side wall of the first contact hole 31, and ensure the supporting effect of the formed anchor-like structure on the whole lower electrode 40. Meanwhile, the height of the stacked contact plug 211 is ensured, so that the stacked contact plug 211 and the lower electrode 40 have a stable bonding state.

In addition, as shown in fig. 2, the second contact hole 32 may be formed in a shape having a large upper end, a small middle, and a large lower end, the first contact hole 31 may be formed in a large aperture such as an aperture at the lower end of the second contact hole 32, the apertures at the upper and lower ends of the first contact hole 31 may be formed in a large aperture, and the outer edge of the first contact hole 31 may coincide with the outer edge of the second contact hole 32. By adopting the above arrangement, the surface area of the lower electrode 40 contacting the sidewall of the second contact hole 32 is increased, and the supporting effect of the lower electrode 40 located in the first contact hole 31 and the second contact hole 32 on the whole lower electrode 40 is improved. And the lower end of the first contact hole 31 is larger, so that the contact area of the lower electrode 40 and the stacked contact plug 211 can be increased, and the resistance of interlayer current transmission can be reduced. The upper end of the second contact hole 32 is large, so that the lower electrode 40 exposed out of the first contact hole 31 and the second contact hole 32 has a large surface area, thereby improving the charge storage capacity of the capacitor, improving the capacitance of the capacitor and improving the storage performance. Of course, the first contact hole 31 and the second contact hole 32 may be provided as a hollow cylindrical through hole.

Referring to fig. 2, an etch stop layer 70 may also be deposited on the second insulating stack 22, at which time the second contact hole 32 also penetrates the etch stop layer 70. By depositing the etching stop layer 70 on the second insulating stack 22, the subsequent etching or cleaning operations are prevented from affecting the substrate 10 and the two insulating stacks, and the quality of the substrate 10 and the insulating stacks is ensured. When determining the material of the etching barrier layer 70, the material of the etching barrier layer 70 may be selected from SiN, SiBN, or SiCN, so as to improve the barrier effect during etching.

Direct contact between the first insulating stack 21 and the second insulating stack 22 may be made. An etch stop layer may also be deposited between the first insulating stack 21 and the second insulating stack 22, i.e. when the first insulating stack 21 and the second insulating stack 22 are not directly stacked together, an etch stop layer is also deposited between the two. Correspondingly, at this time, a contact hole is also formed on the etching barrier layer between the first insulation stack 21 and the second insulation stack 22 to communicate the first contact hole 31 and the second contact hole 32. And the portions of the lower electrode 40 extending into the first and second contact holes 31 and 32 are also deposited on the sidewalls of the contact holes opened on the etch stopper. By depositing the etching barrier layer between the first insulating stack layer and the second insulating stack layer, the first insulating stack layer 21 and the substrate 10 are protected by the etching barrier layer during the manufacturing process, so that the substrate 10 and the two insulating stack layers are prevented from being affected by subsequent etching or cleaning operations, and the quality of the substrate 10 and the insulating stack layers is ensured.

As shown in fig. 2, a support structure 81 for supporting the lower electrode 40 may be further disposed above the etch stop layer 70, and the support structure 81 surrounds the outer sidewall of the lower electrode 40 to improve the supporting effect on the lower electrode 40. When the supporting structure 81 is specifically provided, the supporting structure 81 may be disposed at an upper end of the lower electrode 40, or may be disposed at a middle position of the lower electrode 40, and the supporting structure 81 may be disposed at different positions of the lower electrode 40.

In determining the type of the semiconductor device, the semiconductor device may be a Dynamic Random Access Memory (DRAM) to prevent collapse of a capacitor due to inclination, bending, or the like of the lower electrode 40 in the DRAM. The semiconductor device may also be a Static Random-Access Memory (SRAM), a flash Memory (flash Memory), or the like that employs a capacitor as a storage unit.

By removing the conductor film 221 in the second contact hole 32 and the landing pad 222 in contact with the conductor film 221, and also removing part of the stacked contact plug 211 in the first contact hole 31, the lower electrode 40 formed above the two insulating stacked layers is extended down into the first contact hole 31 and the second contact hole 32 to be in contact with the remaining stacked contact plug 211, and the part of the lower electrode 40 in contact with the stacked contact plug 211 is formed into a structure similar to an anchor, so that the entire lower electrode 40 can be supported, and the entire lower electrode 40 is prevented from being inclined. The anchor-like structure portion of the lower electrode 40 also prevents the entire lower electrode 40 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the first contact hole 31 and the second contact hole 32 can increase the surface area of the lower electrode 40, thereby increasing the charge storage capacity of the capacitor, increasing the capacitance of the capacitor and improving the storage performance. And the lower electrode 40 extends downwards to the first contact hole 31 and the second contact hole 32 to be directly contacted with the reserved stacking contact plug 211, so that the mode that the lower electrode 40 is contacted with the stacking contact plug 211 through the landing pad 222 and the conductor film 221 is replaced, the contact number among different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance.

In addition, an embodiment of the present invention further provides a manufacturing method of a semiconductor device, where the manufacturing method includes:

the method comprises the following steps: providing a substrate 10;

step two: stacking an insulating layer on the substrate 10;

step three: forming a contact hole in the insulating layer;

step four: the contact hole is filled with a stacked contact plug 211 and a landing pad 222 conductively connected with the stacked contact plug 211;

step five: removing landing pad 222;

step six: partially stacking the contact plugs 211 from the top down;

step seven: a lower electrode 40 is formed over the insulating layer and the lower electrode 40 also extends down into the contact hole to contact the remaining stacked contact plug 211.

In the above solution, by removing the landing pad 222 in the contact hole and also removing part of the stacked contact plug 211 in the contact hole, the lower electrode 40 formed above the insulating layer is extended down into the contact hole to contact with the remaining stacked contact plug 211, so that the part of the lower electrode 40 contacting with the stacked contact plug 211 forms an anchor-like structure, which can support the whole lower electrode 40 and prevent the whole lower electrode 40 from tilting. The anchor-like structure portion of the lower electrode 40 also prevents the entire lower electrode 40 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the contact hole can increase the surface area of the lower electrode 40, thereby improving the charge storage capacity of the capacitor, improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 40 extends downwards to the contact hole to be directly contacted with the reserved stacking contact plug 211, so that the mode that the lower electrode 40 is contacted with the stacking contact plug 211 through the landing pad 222 and the conductor film 221 is replaced, the contact number between different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance. The specific operation of the above steps will be described in detail with reference to the accompanying drawings.

First, referring to fig. 3, a substrate 10 is provided, and the substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, the base 10 may include at least a semiconductor substrate, a transistor, a bit line structure, and the like. The transistor may be formed on a semiconductor substrate of a semiconductor device. A bitline structure may be formed over the transistor.

Next, an insulating layer is stacked on the substrate 10. Referring to fig. 3, the insulating layer may be a layer structure formed by one deposition, and may also be a layer structure formed by depositing the first insulating stack 21 and the second insulating stack 22 in two as mentioned in the foregoing description about the semiconductor device portion. Of course, the insulating layer may also be a layer structure composed of the first insulating stack 21 and the second insulating stack 22, and an etching barrier layer therebetween, in which case the insulating layer is deposited at least three times to form a layer structure.

Next, a contact hole is formed in the insulating layer. The contact hole can be a through hole formed in an insulating layer formed by one deposition, or can be a through hole formed in an insulating layer formed by at least two depositions. Referring to fig. 3, when the insulating layer is formed by stacking the first insulating stack 21 and the second insulating stack 22, the contact holes include a first contact hole 31 located below and a second contact hole 32 located above.

Next, referring to fig. 3, the contact hole is filled with the stacked contact plug 211, and the landing pad 222 conductively connected to the stacked contact plug 211. Specifically, referring to fig. 3, the contact hole may be filled with a stacked contact plug; then, filling a conductor film in contact with the stacked contact plug in the contact hole; after that, the contact hole is filled with a landing pad in contact with the conductor film. That is, the contact plug 211, the conductor film 221, and the landing pad 222 are stacked from the bottom up to be filled in the contact hole in this order. The conductive film 221 may be made of metal silicide, and the landing pad 222 may be made of metal to increase the conductivity between the landing pad 24 and the stacked contact plug 11.

As shown in the substrate 10 of fig. 3, the stacked contact plug 211 fills the first contact hole 31, the conductive film 221 and the landing pad 222 fill the second contact hole 32, and the conductive film 221 and the landing pad 222 fill the second contact hole 32. The conductor film 221 is in contact with the stacked contact plug 211, and the landing pad 222 is in contact with the conductor film 221.

In application, the stacked contact plug 211 is in contact with a source region or a drain region of a transistor. Each landing pad 222 is formed on the stacked contact plug 211 corresponding thereto. The landing pad 222 is electrically connected to a source region or a drain region of the transistor through the conductive film 221 and the stacked contact plug 211. Referring to fig. 3, an insulating portion 212 that separates adjacent two stacked contact plugs 211 is also formed in the first insulating stack 21, and the stacked contact plugs 211 and the insulating portion 212 are formed between adjacent bit line structures. An isolation portion 223 is also formed in the second insulating stack 22, and the isolation portion 223 is used to isolate the two adjacent landing pads 222.

Next, referring to fig. 4, the landing pad 222 is removed. When removing landing pad 222, a wet etch or remote plasma dry clean process may be used to remove landing pad 222 without affecting other film qualities. Referring to fig. 5, when the stacked contact plug 211, the conductive film 221, and the landing pad 222 are sequentially filled in the contact hole from bottom to top, the conductive film 221 may be removed. When removing the conductor film 221, the conductor film 221 may be removed by wet etching or a remote plasma dry cleaning process to remove it without affecting other film qualities.

Next, referring to fig. 6, a part of the stacked contact plug 211 is removed from the top down. In the specific removal process, a wet etching process or a remote plasma dry cleaning process may be used to remove a portion of the stacked contact plugs 211 in the contact holes from top to bottom, so as to remove the portions without affecting other film qualities. When removing the stacked contact plug 211 within the contact hole, it is also necessary to leave a portion of the stacked contact plug 211, where the portion of the stacked contact plug 211 is located at the lowermost portion of the contact hole, so that the lower electrode 40 to be formed later is in contact with the remaining stacked contact plug 211.

Next, referring to fig. 2, a lower electrode 40 is formed over the insulating layer, and the lower electrode 40 also extends down into the contact hole to contact the remaining stacked contact plug 211. Specifically, referring to fig. 3, after the stacked contact plug 211 and the landing pad 222 conductively connected to the stacked contact plug 211 are filled in the contact hole, and before the landing pad 222 is removed, a sacrificial film 50 may be further stacked on the insulating layer, and a capacitor hole 60 communicating with the landing pad 222 is formed in the sacrificial film 50. When depositing the sacrificial film layer 50 on the insulating layer, the sacrificial film layer 50 may be deposited directly on the insulating layer. An etch stop layer 70 may also be deposited between the sacrificial film 50 and the insulating layer, and the capacitor hole 60 may communicate with the landing pad 222 after penetrating the sacrificial film 50 and the etch stop layer 70. By depositing the etching barrier layer 70 between the sacrificial film 50 and the insulating layer, after the sacrificial film 50 is removed in the subsequent process, the etching barrier layer 70 can prevent subsequent etching or cleaning operations from affecting the substrate 10 and the insulating layer, and ensure the quality of the substrate 10 and the insulating layer.

As shown in fig. 3, at least one supporting layer 80 may be formed in or above the sacrificial film 50, and in this case, the capacitor holes 60 not only extend through the sacrificial film 50 and the etch stop layer 70, but also extend through each supporting layer 80 and then communicate with the landing pads 222. After the lower electrode 40 is formed in the subsequent process, in the process of removing the sacrificial film layer 50, a part of the support layer 80 is also removed, and the remaining part of the support layer 80 serves as a support structure 81 to support the lower electrode 40.

When the lower electrode 40 is formed over the insulating layer, the lower electrode 40 in contact with the stacked contact plug 211 may be formed on the wall of the capacitor hole 60 and the contact hole, and on the upper end surface of the remaining portion of the stacked contact plug 211. Specifically, first, a lower electrode material layer may be deposited on the surface of the sacrificial film layer 50, the walls of the capacitor holes 60 and the contact holes, and the upper end surface of the remaining portion of the stacked contact plug 211. Then, the lower electrode material layer on the surface of the sacrificial film layer 50 is removed, and the lower electrode 40 in contact with the remaining part of the stacked contact plug 211 is formed, and the lower electrode material layer on the surface of the sacrificial film layer 50 may be removed by using a plasma etching or wet etching method. As shown in fig. 6, if the support layer 80 is deposited over the sacrificial film layer 50, at this time, the lower electrode material layer is deposited not on the surface of the sacrificial film layer 50 but on the surface of the top support layer 80. Likewise, the lower electrode material layer on the surface of the sacrificial film layer 50 is not removed, but the lower electrode material layer on the surface of the top support layer 80 is removed. The lower electrode 40 is formed by adopting a deposition mode, so that the lower electrode 40 is formed, the contact strength of the lower electrode 40 with the hole wall of the contact hole and the upper end surface of the stacked contact plug 211 is improved, and the effect of supporting the whole lower electrode 40 is improved.

After the lower electrode 40 is formed, the sacrificial film 50 may be removed to form the semiconductor device as shown in fig. 2. Specifically, the sacrificial film 50 may be removed by plasma etching or wet etching. When at least one support layer 80 is further formed in the sacrificial film layer 50, it is also necessary to remove a portion of the support layer 80 of each support layer 80, and to leave a portion of the support layer 80 of each layer connected to the outer wall of the lower electrode 40 as a support structure 81 for supporting the lower electrode 40, and the support structure 81 surrounds at least one turn around the outer wall of the lower electrode 40.

By removing the landing pad 222 in the contact hole and also removing part of the stacked contact plug 211 in the contact hole, the lower electrode 40 formed above the insulating layer is extended downward into the contact hole to contact with the remaining stacked contact plug 211, so that the part of the lower electrode 40 in contact with the stacked contact plug 211 forms an anchor-like structure, which can support the whole lower electrode 40 and prevent the whole lower electrode 40 from tilting. The anchor-like structure portion of the lower electrode 40 also prevents the entire lower electrode 40 from being bent and deformed when the dielectric layer and the upper electrode are deposited on the lower electrode 40 in the subsequent process, thereby preventing the capacitor from collapsing. And the part of the lower electrode 40 extending into the contact hole can increase the surface area of the lower electrode 40, thereby improving the charge storage capacity of the capacitor, improving the capacitance of the capacitor and improving the storage performance. And the lower electrode 40 extends downwards to the contact hole to be directly contacted with the reserved stacking contact plug 211, so that the mode that the lower electrode 40 is contacted with the stacking contact plug 211 through the landing pad 222 and the conductor film 221 is replaced, the contact number between different layers is reduced, and the resistance of interlayer current transmission is reduced. In application, since the anchor-like structure portion of the lower electrode 40 supports the entire lower electrode 40, the capacitor structure is relatively firm, and the aspect ratio of the stacked capacitor can be increased appropriately to increase the capacitance of the capacitor, thereby further improving the storage performance.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a first insulating laminated layer laminated on the substrate, wherein a first contact hole is formed in the first insulating laminated layer; wherein the first contact hole is filled with a stacked contact plug from bottom to top, and the stacked contact plug does not fill the first contact hole;

a second insulating laminated layer laminated on the first insulating laminated layer, wherein a second contact hole communicated with the first contact hole is formed in the second insulating laminated layer;

a lower electrode formed over the second insulating stack, and the lower electrode also extends down into the second contact hole and the first contact hole in sequence to contact the stacked contact plug.

2. The semiconductor device according to claim 1, wherein the lower electrode extending to the hole walls of the second contact hole and the first contact hole is deposited on the hole walls of the first contact hole and the second contact hole;

the lower electrode extending to the upper end face of the stacked contact plug is deposited on the upper end face of the stacked contact plug.

3. The semiconductor device according to claim 1, wherein the lower electrode is cylindrical in shape; wherein a bottom wall of the lower electrode is deposited on an upper end face of the stacked contact plug; the side wall part of the lower electrode is deposited on the hole walls of the first contact hole and the second contact hole, and part of the side wall part of the lower electrode is exposed out of the first contact hole and the second contact hole.

4. The semiconductor device of claim 1, wherein an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode are formed on the bottom wall and the inner side wall of the lower electrode and the outer side wall exposed outside the first contact hole and the second contact hole.

5. The semiconductor device according to claim 1, wherein a height of the stacked contact plug is h1, and a height of the first contact hole is h2, wherein 20% xh 2 ≦ h1 ≦ 80% xh 2.

6. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

laminating an insulating layer on the substrate;

forming a contact hole in the insulating layer;

the contact hole is filled with a stacked contact plug and a landing pad which is in conductive connection with the stacked contact plug;

removing the landing pad;

removing part of the stacked contact plug from top to bottom;

a lower electrode is formed over the insulating layer and also extends down into the contact hole to contact a remaining portion of the stacked contact plug.

7. The manufacturing method according to claim 6, wherein the filling of the contact hole with the stacked contact plug and the landing pad conductively connected to the stacked contact plug are embodied as follows:

filling and stacking contact plugs in the contact holes;

filling a conductor film in contact with the stacked contact plug in the contact hole;

filling a landing pad in contact with the conductor film in the contact hole;

after the removing the landing pad, before removing a portion of the stacked contact plug from top to bottom, the manufacturing method further includes: and removing the conductor film.

8. The manufacturing method according to claim 7, wherein the removing the landing pad, the conductor film and a portion of the stacked contact plug is embodied by: and removing the landing pad, the conductor film and part of the stacked contact plug in the contact hole from top to bottom by adopting a wet etching or remote plasma dry cleaning process.

9. The method of manufacturing of claim 6, wherein after filling the contact hole with a stacked contact plug, a landing pad conductively connected to the stacked contact plug, and before removing the landing pad, the method further comprises:

laminating a sacrificial film layer on the insulating layer;

a capacitor hole communicated with the landing pad is formed in the sacrificial film layer;

the step of forming the lower electrode above the insulating layer and extending the lower electrode downward into the contact hole to contact with the remaining part of the stacked contact plug is specifically as follows:

and forming lower electrodes which are contacted with the retained stacked contact plugs on the hole walls of the capacitor holes and the contact holes and the upper end surfaces of the retained part of the stacked contact plugs.

10. The manufacturing method according to claim 9, wherein the forming of the lower electrode in contact with the remaining stacked contact plug on the hole wall of the capacitor hole and the contact hole and the upper end surface of the remaining portion of the stacked contact plug is specifically:

depositing a lower electrode material layer on the surface of the sacrificial film layer, the wall of the capacitor hole and the wall of the contact hole and the upper end surface of the reserved part of the stacked contact plug;

and removing the lower electrode material layer on the surface of the sacrificial film layer to form a lower electrode in contact with the preserved stacking contact plug.

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