CN114530449A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN114530449A CN114530449A CN202011213184.1A CN202011213184A CN114530449A CN 114530449 A CN114530449 A CN 114530449A CN 202011213184 A CN202011213184 A CN 202011213184A CN 114530449 A CN114530449 A CN 114530449A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 129
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000007772 electrode material Substances 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 18
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000007787 solid Substances 0.000 abstract description 12
- 238000005452 bending Methods 0.000 abstract description 7
- 238000010276 construction Methods 0.000 abstract description 3
- 238000003860 storage Methods 0.000 description 20
- 230000004888 barrier function Effects 0.000 description 11
- 230000008093 supporting effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910003697 SiBN Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Semiconductor Memories (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method thereof. A landing pad is formed in the substrate. The lower electrode mainly comprises two parts, wherein one part is a columnar structure which is formed on the substrate and is in contact with the landing pad, and the other part is a cylindrical structure which is formed on the columnar structure and is in contact with the upper end face of the columnar structure. The lower electrode is composed of a columnar structure positioned at the lower part and a cylindrical structure positioned at the upper part. Because the columnar structure that is located the below is solid construction, its rigidity is better, has better stability, can support the lower electrode that is the tubular structure that is located the top, prevents that whole lower electrode from inclining. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the lower electrode which is positioned below and has a columnar structure also prevents the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
A Capacitor (Capacitor) is a component that can store electricity and electrical energy. Different amounts of charge can be stored in the capacitor by applying different voltages across the two electrodes of the capacitor. On this basis, the storage of different data can be realized by a capacitor. It follows that the quality of the capacitor directly affects the data storage performance of the semiconductor device.
In order to improve the driving performance of the memory, the capacitance of the capacitor needs to be increased. A common way to increase the capacitance of a capacitor is to increase the height of the capacitor. However, the height of the capacitor is increased, which results in an increase in the Aspect Ratio (Aspect Ratio) of the capacitor. The aspect ratio of the capacitor is increased, and the problems of capacitor inclination, bending and even collapse are easy to occur when Wet cleaning process is performed.
Disclosure of Invention
The invention provides a semiconductor device and a method for manufacturing the same, which is used for preventing a capacitor from inclining, bending or collapsing.
In a first aspect, the present invention provides a semiconductor device including a substrate and a lower electrode. Wherein a landing pad is formed in the substrate. The lower electrode mainly comprises two parts, wherein one part is a columnar structure which is formed on the substrate and is in contact with the landing pad, and the other part is a cylindrical structure which is formed on the columnar structure and is in contact with the upper end face of the columnar structure.
In the above-described aspect, the lower electrode is composed of two parts, i.e., a columnar structure located below and a cylindrical structure located above. Because the columnar structure that is located the below is solid construction, its rigidity is better, has better stability, can support the tubular structure's that is located the top bottom electrode, prevents that whole bottom electrode from inclining. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the lower electrode which is positioned below and has a columnar structure also prevents the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. When the capacitor is used, the lower electrode which is positioned below and has the columnar structure has a good supporting effect on the whole lower electrode, the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved.
In a specific embodiment, the outer edge of the columnar structure coincides with the outer edge of the cylindrical structure, so that the lower electrode in the columnar structure is in better connection contact with the lower electrode in the cylindrical structure, and the supporting effect of the columnar structure on the cylindrical structure is improved.
In a specific embodiment, an etching barrier layer is deposited on the substrate, and the columnar structure penetrates through the etching barrier layer and then contacts with the landing pad. The etching barrier layer is deposited on the substrate, so that the influence of subsequent operations such as etching or cleaning on the substrate is prevented, and the quality of the substrate is ensured.
In a specific embodiment, the material of the columnar structure is the same as that of the cylindrical structure, so that the electrical properties of the columnar structure and the cylindrical structure are the same, and the electrical properties of the whole lower electrode are kept more consistent. When the material of the columnar structure and the cylindrical structure is specifically selected, titanium nitride or polysilicon can be selected as the material of the columnar structure and the cylindrical structure, so as to improve the electrical property of the lower electrode.
In a specific embodiment, the height of the columnar structure is h1, and the height of the cylindrical structure is h 2; wherein (h1+ h2) x is 50-50% of h 1-70% of (h1+ h 2). So as to ensure the supporting effect of the lower electrode in a columnar structure on the whole lower electrode and improve the capacitance of the capacitor.
In one embodiment, the outer walls of the columnar structures and the cylindrical structures and the bottom walls and the inner walls of the cylindrical structures are respectively provided with an upper electrode and a dielectric layer for insulating and isolating the lower electrode from the upper electrode. Capacitor structures are arranged on the inner side and the outer side of the lower electrode, so that the capacitance of the capacitor is improved, and the storage effect is improved.
In a specific embodiment, the semiconductor device is a dynamic random access memory to prevent collapse of a capacitor in the dynamic random access memory due to inclination, bending, or the like of a lower electrode.
In a second aspect, the present invention also provides a method of manufacturing a semiconductor device, the method comprising: providing a substrate, and forming a landing pad in the substrate; forming a lower electrode in a columnar structure in contact with the landing pad on the substrate; and forming a lower electrode in a cylindrical structure on the columnar structure, wherein the lower electrode is in contact with the upper end face of the columnar structure.
In the above-described aspect, the lower electrode is composed of two parts, i.e., a columnar structure located below and a cylindrical structure located above. Because the columnar structure that is located the below is solid construction, its rigidity is better, has better stability, can support the lower electrode that is the tubular structure that is located the top, prevents that whole lower electrode from inclining. When a dielectric layer and an upper electrode are deposited on the lower electrode in the subsequent process, the lower electrode which is positioned below and has a columnar structure also prevents the whole lower electrode from bending and deforming, thereby preventing the capacitor from collapsing. When the capacitor is used, the lower electrode which is positioned below and has the columnar structure has a good supporting effect on the whole lower electrode, the capacitor structure is firm, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved.
In one embodiment, forming a lower electrode in a pillar structure on a substrate in contact with a landing pad includes: forming a sacrificial film layer covering the substrate above the substrate; etching the sacrificial film layer from top to bottom to form a capacitor hole communicated with the landing pad; and forming a lower electrode in a columnar structure in contact with the landing pad in the capacitor hole, wherein the lower electrode in the columnar structure does not fill the capacitor hole. So as to form the lower electrode in a columnar structure and simultaneously ensure that the outer edge of the cylindrical structure formed in the subsequent process is superposed with the outer edge of the columnar structure.
In one embodiment, the step of forming a lower electrode in a columnar structure in contact with the landing pad in the capacitor hole, wherein the step of forming the columnar structure without filling the capacitor hole is as follows: filling a lower electrode material layer into the capacitor hole, wherein the capacitor hole is filled with the lower electrode material layer; and removing part of the lower electrode material layer in the capacitor hole to form a lower electrode with a columnar structure. So as to form the lower electrode which is not filled in the capacitor hole and has a columnar structure, and ensure that the columnar structure is a solid structure.
In a specific embodiment, the step of removing a portion of the bottom electrode material layer in the capacitor hole to form the bottom electrode having a pillar structure specifically includes: and etching part of the lower electrode material layer in the capacitor hole from top to bottom by adopting a plasma etching or wet etching mode, and reserving part of the lower electrode material layer in the capacitor hole to form a lower electrode in a columnar structure. So as to etch the lower electrode which is not filled with the capacitor hole and has a columnar structure.
In a specific embodiment, forming a lower electrode in a cylindrical structure on the columnar structure in contact with an upper end surface of the columnar structure includes: depositing a lower electrode material layer on the side wall of the capacitor hole, the upper end surface of the columnar structure and the surface of the sacrificial film layer; removing the lower electrode material layer outside the capacitor hole by adopting a plasma etching or wet etching mode to form a lower electrode in a cylindrical structure; and removing the sacrificial film layer. So as to form the lower electrode in a cylindrical structure.
Drawings
FIG. 1a is a schematic diagram of one step in the prior art process for fabricating a capacitor;
FIG. 1b is a schematic diagram of another prior art process for fabricating a capacitor;
FIG. 1c is a schematic diagram of another prior art process for fabricating a capacitor;
FIG. 1d is a schematic diagram of another prior art process for fabricating a capacitor;
FIG. 1e is a schematic diagram of another prior art process for fabricating a capacitor;
fig. 2a is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2b is a schematic structural view of the semiconductor device provided in fig. 2a from a top view;
fig. 3 is a schematic diagram illustrating a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4a is a schematic view of another step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 4b is a schematic structural view of a semiconductor device provided in fig. 4a from a top view;
fig. 5 is a schematic view of another step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 6 is a schematic view of another step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 7 is a schematic view of another process in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 8 is a schematic diagram illustrating another step in the method for manufacturing the semiconductor device according to the embodiment of the present invention.
Reference numerals in fig. 1a to 1 e:
1-substrate 2-etch stop layer 3-sacrificial film layer
4-capacitor hole 5-lower electrode material layer 6-lower electrode
Reference numerals in fig. 2 to 8
10-substrate 11-landing pad 12-isolation
20-lower electrode 21-columnar structure 22-cylindrical structure
221-disc 222-cylinder 30-capacitor hole
41-etching barrier layer 42-sacrificial film layer 43-lower electrode material layer
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
To facilitate understanding of the semiconductor device provided in the embodiment of the present invention, an application scenario of the semiconductor device provided in the embodiment of the present invention, which is applied to a memory having a capacitor, is first described below. The semiconductor device will be described in detail with reference to the drawings.
Referring to fig. 2a and 2b, a semiconductor device according to an embodiment of the present invention includes a substrate 10 and a bottom electrode 20. Wherein a landing pad 11 is formed in the substrate 10. The lower electrode 20 mainly includes two portions, one of which is a columnar structure 21 formed on the substrate 10 and in contact with the landing pad 11, and the other of which is a cylindrical structure 22 formed on the columnar structure 21 and in contact with an upper end face of the columnar structure 21.
In the above-described embodiment, the lower electrode 20 is composed of two parts, i.e., the lower columnar structure 21 and the upper cylindrical structure 22. Because the lower columnar structure 21 is a solid structure, the rigidity is good, the stability is good, and the lower electrode 20 which is positioned above and is in a cylindrical structure 22 can be supported, so that the whole lower electrode 20 is prevented from inclining. The lower electrode 20 having the pillar-shaped structure 21 located thereunder also prevents the entire lower electrode 20 from being bent and deformed when a dielectric layer and an upper electrode are deposited on the lower electrode 20 in the subsequent process, thereby preventing the capacitor from collapsing. When in use, the lower electrode 20 of the lower columnar structure 21 has a better supporting effect on the whole lower electrode 20, so that the capacitor structure is firmer, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved. The arrangement of the above components will be described in detail with reference to the accompanying drawings.
In providing the substrate 10, referring to fig. 2a, the substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, referring to fig. 2a, the base 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a memory contact, an insulating portion, a landing pad 11, and an isolation portion 12. The transistor may be formed on a semiconductor substrate of a semiconductor device. A bitline structure may be formed over the transistor. A storage contact and an insulating portion are formed between adjacent bit line structures. The storage contact portion is in contact with a source region or a drain region of the transistor. The insulating part is used for isolating two adjacent storage contact parts. Meanwhile, each landing pad 11 is formed on the storage contact portion corresponding thereto. The landing pad 11 is electrically connected to a source region or a drain region of the transistor through a storage contact. An isolation portion 12 is formed on the bit line structure and the insulating portion, and the isolation portion 12 is used to isolate the adjacent two landing pads 11.
When the lower electrode 20 is provided, referring to fig. 2a and 2b, the lower electrode 20 mainly includes two portions, one of which is a pillar structure 21 formed on the substrate 10 and contacting the landing pad 11, and the other of which is a cylinder structure 22 formed on the pillar structure 21 and contacting an upper end surface of the pillar structure 21. The columnar structure 21 is a solid structure, and may be a columnar structure 21 such as a cylinder or a prism. The lower end surface of the columnar structure 21 is in contact with the landing pad 11, and the upper end surface is in contact with the lower end surface of the cylindrical structure 22. The cylindrical structure 22 is a hollow structure, and includes a disc 221 contacting with the upper end surface of the cylindrical structure 21, and a cylinder 222 connected to the edge of the disc 221. Wherein the barrel 222 is a hollow, thin-walled structure. The disk 221 is a solid thin-walled structure, and is in contact with the upper end surface of the columnar structure 21, so that the columnar structure 21 of the lower electrode 20 can be in better contact with the cylindrical structure 22, and the resistivity can be reduced.
Referring to fig. 1a, firstly, depositing an etching barrier layer 2 and a sacrificial film layer 3 on a substrate 1; then, referring to fig. 1b, etching the sacrificial film layer 3 and the etching barrier layer 2 to form a capacitor hole 4; then, referring to fig. 1c, a lower electrode material layer 5 is deposited on the sacrificial film layer 3, the inner wall of the capacitor hole 4 and the bottom wall; thereafter, referring to fig. 1d, the lower electrode material layer 5 except the capacitor hole 4 is removed to form a lower electrode 6; thereafter, referring to fig. 1e, the sacrificial film 3 is removed; and depositing a dielectric layer and an upper electrode on the lower electrode 6 to form a capacitor.
Compared with the semiconductor device shown in fig. 2a of the present invention, in the semiconductor device shown in fig. 1e of the prior art, due to the adoption of the arrangement mode disclosed by the present invention, since the lower columnar structure 21 is a solid structure, the rigidity is good, the stability is good, the lower electrode 20 which is located above and is in the shape of the cylindrical structure 22 can be supported, and the whole lower electrode 20 is prevented from inclining. The lower electrode 20 having the pillar-shaped structure 21 located thereunder also prevents the entire lower electrode 20 from being bent and deformed when a dielectric layer and an upper electrode are deposited on the lower electrode 20 in the subsequent process, thereby preventing the capacitor from collapsing. When in use, the lower electrode 20 with the lower columnar structure 21 has a better supporting effect on the whole lower electrode 20, so that the capacitor structure is firmer, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved.
In addition, the outer edge of the columnar structure 21 and the outer edge of the cylindrical structure 22 may be overlapped, that is, the upper end surface of the columnar structure 21 and the lower end surface of the tray 221 in the cylindrical structure 22 are end surfaces with the same size and shape, and the outer edge of the upper end surface of the columnar structure 21 and the outer edge of the lower end surface of the tray 221 are overlapped, so that the lower electrode 20 in the columnar structure 21 and the lower electrode 20 in the cylindrical structure 22 are in better connection contact, the supporting effect of the columnar structure 21 on the cylindrical structure 22 is improved, and the resistivity of the conductive connection between the columnar structure 21 and the cylindrical structure 22 is reduced.
In determining the materials of the pillar structures 21 and the tube structures 22, the materials of the pillar structures 21 and the tube structures 22 can be selected to be the same, so that the electrical properties of the two are the same, and the electrical properties of the whole lower electrode 20 can be kept more consistent. When the material of the pillar structure 21 and the tube structure 22 is specifically selected, titanium nitride or polysilicon can be selected as the material of the pillar structure 21 and the tube structure 22 to improve the electrical performance of the lower electrode 20. It should be understood that the material of the pillar structures 21 may also be different from the material of the cylinder structures 22, for example, the material of the pillar structures 21 may be selected to be polysilicon, and the material of the cylinder structures 22 may be titanium nitride.
With continued reference to fig. 2a and 2b, an etch stop layer 41 may be deposited on the substrate 10, and the pillar structures 21 may penetrate the etch stop layer 41 and then contact the landing pads 11. I.e., a capacitor hole 30 is formed in the etch stop layer 41, and the capacitor hole 30 communicates with the landing pad 11. The pillar structure 21 penetrates the capacitor hole 30 and contacts the landing pad 11. By depositing the etching barrier layer 41 on the substrate 10, the subsequent etching or cleaning operations are prevented from affecting the substrate 10, and the quality of the substrate 10 is ensured.
When the dielectric layer and the upper electrode are further disposed to complete the manufacture of the whole capacitor, the upper electrode and the dielectric layer for insulating and isolating the lower electrode 20 from the upper electrode may be formed on the outer walls of the cylindrical structures 21 and 22 and the bottom wall and the inner wall of the cylindrical structure 22. That is, a dielectric layer and an upper electrode are formed on the outer side wall of the columnar structure 21 of the lower electrode 20, and a dielectric layer and an upper electrode are formed on the outer side wall as well as the inner side wall and the bottom wall of the columnar structure 22 of the lower electrode 20. The capacitor structures are arranged on the inner side and the outer side of the lower electrode 20, so that the capacitance of the capacitor is improved, and the storage effect is improved. It should be understood that the manner of providing the dielectric layer and the upper electrode is not limited to the above-described manner, and other manners may be adopted. For example, the dielectric layer and the upper electrode may be formed only on the inner wall and the bottom wall of the cylindrical structure 22 of the lower electrode 20, and the dielectric layer and the upper electrode may not be formed on the outer wall of the cylindrical structure 22 of the lower electrode 20.
In determining the heights of the two main portions of the lower electrode 20, referring to fig. 2a, it can be assumed that the height of the columnar structure 21 of the lower electrode 20 is h1, i.e., the vertical distance between the lower end face of the columnar structure 21 in contact with the landing pad 11 to the upper end face of the columnar structure 21 in contact with the disk 221 of the cylindrical structure 22 is h 1. The height of the cylindrical structure 22 of the lower electrode 20 is h2, i.e., the vertical distance between the lower end surface of the disk 221 in the cylindrical structure 22 and the upper end surface of the cylindrical body 222 is h 2. The height between h1 and h2 can be set to satisfy (h1+ h2) x 50% to h1 (h1+ h2) x 70%, that is, the height h1 of the columnar structure 21 accounts for 50% -70% of the total height of the lower electrode 20. Specifically, any value between 50% and 70% of the total height of the lower electrode 20 may be set, such as h1 ═ h1+ h2 × 50%, h1 ═ h1+ h2 × 55%, h1 ═ h1+ h2 × 60%, h1 ═ h1+ h2 × 65%, and h1 ═ h1+ h2 × 70%. When the relationship between the heights of the two portions of the lower electrode 20 satisfies the above relationship, the height of the columnar structure 21 is kept at a reasonable height, the columnar structure 21 can well support the whole lower electrode 20, and the support effect of the columnar structure 21 on the whole lower electrode 20 is ensured. Meanwhile, the height of the cylindrical structure 22 is appropriate, and the inner and outer side walls of the cylindrical structure 22 can be provided with the upper electrode, so that the surface area of the lower electrode 20 opposite to the upper electrode is increased, and the capacitance of the capacitor is increased.
In determining the type of the semiconductor device, the semiconductor device may be a Dynamic Random Access Memory (DRAM) to prevent collapse of a capacitor due to inclination, bending, or the like of the lower electrode 20 in the DRAM. The semiconductor device may also be a Static Random-Access Memory (SRAM), a flash Memory (flash Memory), or the like that employs a capacitor as a storage unit.
The lower electrode 20 is composed of two parts, a lower columnar structure 21 and an upper cylindrical structure 22. Because the lower columnar structure 21 is a solid structure, the rigidity is good, the stability is good, and the lower electrode 20 which is positioned above and is in a cylindrical structure 22 can be supported, so that the whole lower electrode 20 is prevented from inclining. The lower electrode 20 having the pillar-shaped structure 21 located thereunder also prevents the entire lower electrode 20 from being bent and deformed when a dielectric layer and an upper electrode are deposited on the lower electrode 20 in the subsequent process, thereby preventing the capacitor from collapsing. When in use, the lower electrode 20 of the lower columnar structure 21 has a better supporting effect on the whole lower electrode 20, so that the capacitor structure is firmer, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved.
In addition, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, and with reference to fig. 2a to 8, the method includes:
the method comprises the following steps: providing a substrate 10, forming a landing pad 11 in the substrate 10;
step two: forming a lower electrode 20 in a pillar structure 21 in contact with the landing pad 11 on the substrate 10;
step three: a lower electrode 20 in the form of a cylindrical structure 22 is formed on the columnar structure 21 in contact with the upper end face of the columnar structure 21.
In the above-described embodiment, the lower electrode 20 is composed of two parts, i.e., the lower columnar structure 21 and the upper cylindrical structure 22. Because the lower columnar structure 21 is a solid structure, the rigidity is good, the stability is good, and the lower electrode 20 which is positioned above and is in a cylindrical structure 22 can be supported, so that the whole lower electrode 20 is prevented from inclining. The lower electrode 20 having the pillar-shaped structure 21 located thereunder also prevents the entire lower electrode 20 from being bent and deformed when a dielectric layer and an upper electrode are deposited on the lower electrode 20 in the subsequent process, thereby preventing the capacitor from collapsing. When in use, the lower electrode 20 of the lower columnar structure 21 has a better supporting effect on the whole lower electrode 20, so that the capacitor structure is firmer, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved. The above steps will be described in detail with reference to the accompanying drawings.
First, referring to fig. 3, a substrate 10 is provided, and a landing pad 11 is formed in the substrate 10. The substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, referring to fig. 2a, the base 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a memory contact, an insulating portion, a landing pad 11, and an isolation portion 12. The transistor may be formed on a semiconductor substrate of the semiconductor device. A bitline structure may be formed over the transistor. A memory contact and an insulating portion are formed between adjacent bit line structures. The storage contact portion is in contact with a source region or a drain region of the transistor. The insulating part is used for isolating two adjacent storage contact parts. Meanwhile, each landing pad 11 is formed on the storage contact portion corresponding thereto. The landing pad 11 is electrically connected to a source region or a drain region of the transistor through a storage contact. An isolation portion 12 is formed on the bit line structure and the insulating portion, and the isolation portion 12 is used to isolate the adjacent two landing pads 11.
Next, the lower electrode 20 in the columnar structure 21 is formed on the substrate 10 in contact with the landing pad 11. In a specific processing, referring to fig. 3, a sacrificial film 42 covering the substrate 10 may be formed above the substrate 10; then, referring to fig. 4a and 4b, the sacrificial film 42 is etched from top to bottom to form the capacitor hole 30 communicating with the landing pad 11; thereafter, referring to fig. 6, the lower electrode 20 in the pillar structure 21 contacting the landing pad 11 is formed in the capacitor hole 30, and the lower electrode 20 in the pillar structure 21 does not fill the capacitor hole 30. Forming a lower electrode 20 in a columnar structure 21 in contact with the landing pad 11 by forming the lower electrode 20 in a columnar structure 21 in the capacitor hole 30; the columnar structure 21 does not fill the capacitor hole 30, and the outer edge of the cylindrical structure 22 formed in the subsequent process coincides with the outer edge of the columnar structure 21.
With continued reference to fig. 3, 4a, 4b, and 6, an etch stop layer 41 may be deposited between the sacrificial film 42 and the substrate 10, where the sacrificial film 42 is not directly disposed on the substrate 10, and the sacrificial film 42 is separated from the substrate 10 by the etch stop layer 41. By laminating the etching barrier layer 41 between the sacrificial film 42 and the substrate 10, the subsequent operations such as etching or cleaning are prevented from affecting the substrate 10, and the quality of the substrate 10 is ensured. When determining the material of the etching barrier layer 41, the material of the etching barrier layer 41 may be selected from SiN, SiBN, or SiCN, so as to improve the barrier effect during etching. At this time, when the capacitor hole 30 is formed, the sacrificial film layer 42 and the etching stopper layer 41 are sequentially etched from top to bottom so that the capacitor hole 30 communicates with the landing pad 11, and the lower end surface of the columnar structure 21 formed in the capacitor hole 30 contacts the landing pad 11. It should be noted that it is also possible to have a direct contact between the sacrificial film 42 and the substrate 10, i.e. in such a way that there is no etch stop layer 41 separating the sacrificial film 42 from the substrate 10.
When the lower electrode 20 in the columnar structure 21 is processed without filling the capacitor hole 30, referring to fig. 5, first, the capacitor hole 30 is filled with the lower electrode material layer 43, and the capacitor hole 30 is filled with the lower electrode material layer 43; referring to fig. 6, next, a portion of the lower electrode material layer 43 in the capacitor hole 30 is removed, and the lower electrode 20 having the pillar structure 21 is formed. The lower electrode material layer 43 is filled in the capacitor hole 30, and then the lower electrode material layer 43 in the capacitor hole 30 is removed to form the pillar structure not filled in the capacitor hole 30, so as to form the lower electrode 20 in the pillar structure 21 not filled in the capacitor hole 30, thereby ensuring that the pillar structure 21 is a solid structure. When the lower electrode 20 having the pillar-shaped structure 21 is formed by removing a portion of the lower electrode material layer 43 in the capacitor hole 30, a portion of the lower electrode material layer 43 in the capacitor hole 30 may be etched from top to bottom by plasma etching or wet etching, and a portion of the lower electrode material layer 43 in the capacitor hole 30 is remained to form the lower electrode 20 having the pillar-shaped structure 21. The lower electrode 20 in the columnar structure 21 which is not filled in the capacitor hole 30 is etched by adopting a plasma etching or wet etching mode. It should be understood that the manner of forming the lower electrode 20 in the pillar-shaped structure 21 to fill the capacitor hole 30 is not limited to the manner of filling first and then partially removing as shown above, and other manners may be adopted. For example, the lower electrode 20 having the pillar-shaped structure 21 can be directly formed without filling the capacitor hole 30 so that the lower electrode material layer 43 does not fill the capacitor hole 30.
Referring to fig. 5 and 6, when the lower electrode material layer 43 inside the capacitor hole 30 is removed, the lower electrode material layer 43 deposited on the sacrificial film 42 may also be removed. The lower electrode material layer 43 located outside the capacitor hole 30 may be removed together with the lower electrode 20 of the cylindrical structure 22 in the subsequent formation.
Next, the lower electrode 20 having the cylindrical structure 22 in contact with the upper end face of the columnar structure 21 is formed on the columnar structure 21. When the lower electrode 20 in the cylindrical structure 22 contacting with the upper end surface of the cylindrical structure 21 is formed on the cylindrical structure 21, referring to fig. 7, a lower electrode material layer 43 may be deposited on the sidewall of the capacitor hole 30, the upper end surface of the cylindrical structure 21 and the surface of the sacrificial film 42, where the deposited lower electrode material layer 43 is a thinner material layer deposited on the sidewall of the capacitor hole 30, the upper end surface of the cylindrical structure 21 and the surface of the sacrificial film 42, which is different from the process of the lower electrode material layer 43 in the process of filling the capacitor hole 30; thereafter, referring to fig. 8, the lower electrode material layer 43 is removed except the capacitor hole 30, and the lower electrode 20 having the cylindrical structure 22 is formed; thereafter, referring to fig. 2a and 2b, the sacrificial film 42 is removed, and the lower electrode 20 composed of the pillar structure 21 and the tube structure 22 is formed. When the lower electrode material layer 43 and the sacrificial film 42 outside the capacitor hole 30 are removed, the lower electrode material layer 43 and the sacrificial film 42 outside the capacitor hole 30 can be removed by plasma etching or wet etching, so as to form the lower electrode 20 in the cylindrical structure 22.
The lower electrode 20 is composed of two parts, a lower columnar structure 21 and an upper cylindrical structure 22. Because the lower columnar structure 21 is a solid structure, the rigidity is good, the stability is good, and the lower electrode 20 which is positioned above and is in a cylindrical structure 22 can be supported, so that the whole lower electrode 20 is prevented from inclining. The lower electrode 20 having the pillar-shaped structure 21 located thereunder also prevents the entire lower electrode 20 from being bent and deformed when a dielectric layer and an upper electrode are deposited on the lower electrode 20 in the subsequent process, thereby preventing the capacitor from collapsing. When in use, the lower electrode 20 of the lower columnar structure 21 has a better supporting effect on the whole lower electrode 20, so that the capacitor structure is firmer, the height-width ratio of the stacked capacitor can be properly increased, the capacitance of the capacitor is increased, and the storage performance is improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A semiconductor device, comprising:
a landing pad formed in the substrate;
a lower electrode, the lower electrode comprising:
a columnar structure formed on the substrate and in contact with the landing pad;
and the cylindrical structure is formed on the columnar structure and is in contact with the upper end face of the columnar structure.
2. The semiconductor device according to claim 1, wherein an outer edge of the columnar structure coincides with an outer edge of the columnar structure.
3. The semiconductor device of claim 1, wherein an etch stop layer is deposited on the substrate, and the columnar structure penetrates through the etch stop layer and contacts the landing pad.
4. The semiconductor device according to claim 1, wherein a material of the columnar structure is the same as a material of the columnar structure.
5. The semiconductor device according to claim 4, wherein the columnar structure and the cylindrical structure are made of titanium nitride or polysilicon.
6. The semiconductor device according to claim 1, wherein a height of the columnar structure is h1, a height of the columnar structure is h 2; wherein (h1+ h2) x is 50-50% of h 1-70% of (h1+ h 2).
7. The semiconductor device according to claim 1, wherein an upper electrode and a dielectric layer insulating and isolating the lower electrode from the upper electrode are formed on outer walls of the columnar structures and the cylindrical structures and on bottom walls and inner walls of the cylindrical structures.
8. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a landing pad is formed in the substrate;
forming a lower electrode in a columnar structure in contact with the landing pad on the substrate;
and forming a lower electrode in a cylindrical structure on the columnar structure, wherein the lower electrode is in contact with the upper end face of the columnar structure.
9. The method of manufacturing according to claim 8, wherein the forming a lower electrode in a pillar structure on the substrate in contact with the landing pad comprises:
forming a sacrificial film layer covering the substrate above the substrate;
etching the sacrificial film layer from top to bottom to form a capacitor hole communicated with the landing pad;
and forming the lower electrode in the columnar structure in contact with the landing pad in the capacitor hole, wherein the lower electrode in the columnar structure does not fill the capacitor hole.
10. The method of claim 9, wherein the forming of the lower electrode in a pillar structure in contact with the landing pad in the capacitor hole without filling the capacitor hole comprises:
filling a lower electrode material layer into the capacitor hole, wherein the capacitor hole is filled with the lower electrode material layer;
and removing part of the lower electrode material layer in the capacitor hole to form the lower electrode in the columnar structure.
11. The method according to claim 10, wherein the removing the portion of the bottom electrode material layer in the capacitor hole to form the bottom electrode having the pillar structure comprises:
and etching part of the lower electrode material layer in the capacitor hole from top to bottom by adopting a plasma etching or wet etching mode, and reserving part of the lower electrode material layer in the capacitor hole to form the lower electrode in the columnar structure.
12. The manufacturing method according to claim 9, wherein the forming of the lower electrode in a cylindrical structure on the columnar structure in contact with the upper end face of the columnar structure comprises:
depositing the lower electrode material layer on the side wall of the capacitor hole, the upper end surface of the columnar structure and the surface of the sacrificial film layer;
removing the lower electrode material layer outside the capacitor hole by adopting a plasma etching or wet etching mode to form the lower electrode in a cylindrical structure;
and removing the sacrificial film layer.
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| CN202011213184.1A CN114530449A (en) | 2020-11-03 | 2020-11-03 | Semiconductor device and manufacturing method thereof |
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| CN202011213184.1A CN114530449A (en) | 2020-11-03 | 2020-11-03 | Semiconductor device and manufacturing method thereof |
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