CN110970403A - Capacitor array structure, forming method thereof and semiconductor device - Google Patents
Capacitor array structure, forming method thereof and semiconductor device Download PDFInfo
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- CN110970403A CN110970403A CN201811151407.9A CN201811151407A CN110970403A CN 110970403 A CN110970403 A CN 110970403A CN 201811151407 A CN201811151407 A CN 201811151407A CN 110970403 A CN110970403 A CN 110970403A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 146
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 75
- 238000002955 isolation Methods 0.000 claims description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 description 10
- 239000007772 electrode material Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a capacitor array structure and a forming method thereof, and a semiconductor device.A peripheral wrapping type main body supporting layer is formed on a device area to obtain a flat capacitor array boundary, so that the problem of short circuit between a plug and the capacitor array boundary caused by cracks due to uneven capacitor array boundary when a filling material is deposited subsequently is avoided, and the reliability of the capacitor device is improved while the stability of an array area is improved.
Description
Technical Field
The present invention relates to the field of semiconductor devices and manufacturing, and more particularly, to a capacitor array structure and a method for forming the same.
Background
With the development of semiconductor technology, the performance requirements of capacitors in semiconductor integrated circuits are higher and higher, and for example, it is expected that the capacitors formed in a limited area can have a larger capacitance. One solution is to increase the contact area between the lower electrode and the capacitance medium layer by increasing the height of the lower electrode in the capacitor, so that the formed capacitor has a larger capacitance.
However, as the height of the bottom electrode increases, the aspect ratio of the bottom electrode also increases, which is very likely to cause the problem of bending deformation or collapse of the bottom electrode, and affects the reliability of the array area. At present, stability is increased by adding a transverse continuous supporting layer of an electrode, but the continuous supporting layer can form an uneven capacitor array boundary, and cracks are easily formed at the capacitor array boundary when a filling material is deposited subsequently, so that a plug and the capacitor array boundary are short-circuited. Therefore, protection of the capacitor array boundaries is necessary.
Disclosure of Invention
The invention aims to provide a capacitor array structure, a forming method thereof and a semiconductor device, which can avoid the short circuit problem caused by cracks formed at the boundary of the capacitor array when filling materials are deposited, and further improve the reliability of a capacitor.
The invention provides a method for forming a capacitor array structure, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a device area for forming a capacitor and a peripheral area positioned at the periphery of the device area;
forming a sacrificial layer and a main body supporting layer in the device area, wherein the main body supporting layer comprises a transverse supporting layer and a longitudinal supporting layer, the transverse supporting layer covers the upper surface of the sacrificial layer, the longitudinal supporting layer covers the side surface, close to the peripheral area, of the sacrificial layer, and the longitudinal supporting layer is connected with the transverse supporting layer and the substrate;
forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate through the transverse supporting layer and the sacrificial layer to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
and removing the sacrificial layer, and sequentially forming a capacitance dielectric layer and an upper electrode on the inner surface and the outer surface of the lower electrode to form the capacitor.
Preferably, at least one lower support layer is formed between the transverse support layer and the base, the lower support layer is parallel to the transverse support layer, and one end of the lower support layer is connected with the longitudinal support layer.
Preferably, the method for forming the lower support layer includes:
forming a lower laminated structure on the substrate, wherein the lower laminated structure is formed by alternately arranging a sacrificial layer and a lower supporting layer;
forming a body support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;
forming a plurality of through holes, wherein the through holes sequentially penetrate through the transverse supporting layer and the lower laminated structure to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area;
and removing the sacrificial layer, wherein the transverse supporting layer and the lower supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Preferably, the transverse support layer is formed with at least one upper support layer, the upper support layer is parallel to the transverse support layer, and one end of the upper support layer is flush with the longitudinal support layer in the direction perpendicular to the base.
Preferably, the method of forming the upper support layer includes:
forming an upper laminated structure on the transverse supporting layer, wherein the upper laminated structure is formed by alternately arranging a sacrificial layer and an upper supporting layer;
forming a plurality of through holes, wherein the through holes sequentially penetrate through the upper laminated structure, the transverse supporting layer and the sacrificial layer to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
and removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Preferably, at least one lower supporting layer is formed between the transverse supporting layer and the base, and at least one upper supporting layer is formed on the transverse supporting layer; the upper supporting layer and the lower supporting layer are parallel to the transverse supporting layer, one end of the lower supporting layer is connected with the longitudinal supporting layer, and one end of the upper supporting layer is flush with the longitudinal supporting layer in the direction perpendicular to the base.
Preferably, the method of forming the upper support layer and the lower support layer includes:
forming a lower laminated structure on the substrate, wherein the lower laminated structure is formed by alternately arranging a sacrificial layer and a lower supporting layer;
forming a body support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;
forming an upper laminated structure on the transverse supporting layer, wherein the upper laminated structure is formed by alternately arranging a sacrificial layer and an upper supporting layer;
forming a plurality of through holes which sequentially penetrate through the upper laminated structure, the transverse supporting layer and the lower laminated structure to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
and removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Preferably, the lower electrode also covers the side of the longitudinal support layer close to the peripheral region and the side of the upper laminated structure close to the peripheral region.
Preferably, an isolation layer is further formed between the sacrificial layer and the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure.
Preferably, a plurality of node contacts are formed in the substrate, the via holes expose the node contacts, and the lower electrodes are connected to the node contacts at the bottoms of the via holes.
Preferably, the material of the main body support layer, the upper support layer, the lower support layer and the isolation layer includes silicon nitride.
Further, the present invention provides a capacitor array structure, comprising:
a plurality of capacitors that are arranged in the substrate device area and are distributed in an array, each of the capacitors includes: the capacitor comprises a lower electrode, a capacitor dielectric layer and an upper electrode; the lower electrode is arranged on the substrate and has a plurality of cylindrical structures; the capacitor dielectric layer is arranged on the inner surface and the outer surface of the lower electrode; the upper electrode is arranged on the outer surface of the capacitor dielectric layer;
a body support layer comprising a lateral support layer and a longitudinal support layer; the transverse supporting layer is arranged on the device area and is connected with the outer wall of the lower electrode cylindrical structure; the longitudinal supporting layer is arranged at one end of the transverse supporting layer and is connected with the transverse supporting layer and the base; and a lower electrode is arranged on one side surface of the longitudinal supporting layer, which is different from the transverse supporting layer.
Preferably, at least one lower supporting layer is arranged between the transverse supporting layer and the base, the lower supporting layer is connected with the outer wall of the lower electrode cylindrical structure, and one end of the lower supporting layer is connected with the longitudinal supporting layer.
Preferably, at least one upper support layer is arranged on the transverse support layer, the upper support layer is connected with the outer wall of the lower electrode cylindrical structure, and one end of the upper support layer is flush with the longitudinal support layer in the direction perpendicular to the base.
Preferably, at least one lower supporting layer is arranged between the transverse supporting layer and the base, and at least one upper supporting layer is arranged on the transverse supporting layer.
Preferably, the lower support layer and the upper support layer are connected with the outer wall of the lower electrode cylindrical structure, one end of the lower support layer is connected with the longitudinal support layer, and one end of the upper support layer is flush with the longitudinal support layer in the direction perpendicular to the base.
Preferably, the lower electrode disposed on a side of the longitudinal support layer different from the lateral support layer is extended to connect the upper support layer.
Preferably, an isolation layer is further arranged on the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure; the capacitor array structure further comprises a plurality of node contacts located in the substrate, and the bottom of the lower electrode cylindrical structure is connected with the node contacts.
Preferably, the main body support layer, the upper support layer and the lower support layer are made of silicon nitride, and the sacrificial layer is made of silicon oxide.
Furthermore, the invention also provides a semiconductor device which comprises the capacitor array structure.
Preferably, the semiconductor device is applied to a dynamic random access memory.
In summary, in the method for forming the capacitor array structure provided by the invention, the planar capacitor array boundary is obtained by forming the main body support layer in a peripheral wrapping manner on the device region, so that cracks caused by unevenness of the capacitor array boundary during subsequent deposition of the filling material are avoided, the problem of short circuit between the plug and the capacitor array boundary due to the cracks is further avoided, and the reliability of the capacitor device is improved while the stability of the array region is increased.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art capacitor during its fabrication;
fig. 2 is a schematic flow chart illustrating a method for forming a capacitor array structure according to an embodiment of the invention;
fig. 3 to 9 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to an embodiment of the invention;
fig. 10 to fig. 15 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to a second embodiment of the invention;
fig. 16 to fig. 20 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to a third embodiment of the invention;
fig. 21 to 23 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to a fourth embodiment of the invention.
Wherein the reference numbers are as follows:
10/100-a substrate; 10A/100A-device region;
10B/100B-peripheral region; 100A-device region edge portion;
11-cracking; 12-a plug;
101-contact; 102-an isolation layer;
103-a sacrificial layer; 120-a body support layer;
104-lateral support layer; 105-a longitudinal support layer;
130-a through hole; 106-a lower electrode;
107-capacitor dielectric layer; 108-an upper electrode;
109-upper electrode fill layer; 110-upper electrode connection layer;
200-lower stack structure; 201-a first lower support layer;
202-a second lower support layer; 210-a first lower sacrificial layer;
220-a second lower sacrificial layer; 300-upper lamination mechanism;
301-a first upper support layer; 302-a second upper support layer;
310-a first upper sacrificial layer; 320-a second upper sacrificial layer;
Detailed Description
Fig. 1 is a schematic cross-sectional view of a capacitor in the prior art during a manufacturing process thereof, as shown in fig. 1, in a forming process of the prior art, a filling material layer is deposited after a process of completing a capacitor device in a device area (Array area)10A, a Crack 11(Crack) is easily generated at an uneven place (shown by a circle) due to an uneven boundary of a capacitor Array located in the device area 10A, in a subsequent process of forming a plug 12(CT), a dry etching and a wet cleaning of a plug hole aggravate the Crack, and then when a metal is filled, the metal also drills into the Crack, so that the plug and the capacitor Array boundary or the plug and the plug are directly short-circuited, thereby affecting reliability of the capacitor device.
The core idea of the invention is to provide a capacitor array structure, a forming method thereof and a semiconductor device, wherein a peripheral wrapping type supporting structure is formed in a device area to obtain a flat capacitor array boundary, so that the problem of short circuit between a plug and the capacitor array boundary caused by cracks due to uneven capacitor array boundary when a filling material is deposited subsequently is avoided, and the reliability of the capacitor device is improved while the stability of the array area is improved.
The capacitor array, the forming method thereof and the semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 2 is a schematic flow chart illustrating a method for forming a capacitor array structure according to an embodiment of the present invention, and as shown in fig. 2, the method for forming a capacitor array structure according to the present invention includes:
s01: providing a substrate, wherein the substrate is provided with a device area for forming a capacitor and a peripheral area positioned at the periphery of the device area;
s02: forming a sacrificial layer and a main body supporting layer in the device area, wherein the main body supporting layer comprises a transverse supporting layer and a longitudinal supporting layer, the transverse supporting layer covers the upper surface of the sacrificial layer, the longitudinal supporting layer covers the side surface, close to the peripheral area, of the sacrificial layer, and the longitudinal supporting layer is connected with the transverse supporting layer and the substrate;
s03: forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate through the transverse supporting layer and the sacrificial layer to expose the substrate;
s04: forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
s05: and removing the sacrificial layer, and sequentially forming a capacitance dielectric layer and an upper electrode on the inner surface and the outer surface of the lower electrode to form the capacitor.
Fig. 3 to 9 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to an embodiment of the invention. The method for forming the capacitor array in this embodiment will be further explained below with reference to the corresponding structural diagrams of the respective steps.
In step S01, referring to fig. 3, a substrate 100 is provided, the substrate 100 includes a device region 100A for forming a capacitor and a peripheral region 100B located at a periphery of the device region 100A, and the device region 100A and the peripheral region 100B are isolated by a trench isolation structure. In the following schematic sectional structure diagram of the capacitor array, only a portion of the capacitor device region 100A is shown.
The substrate 100 may be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, Silicon On Insulator (SOI), or the like, or other materials known to those skilled in the art, and a plurality of node contacts 101 are further formed in the substrate 100, wherein the node contacts 101 are electrically connected to a lower electrode of a capacitor to be formed subsequently. Of course, other device structures such as an isolation structure may also be formed in the substrate 100, which is not limited in the present invention.
In step S02, first, referring to fig. 3, an isolation layer 102 and a sacrificial layer 103 are sequentially formed on the substrate 100. Then, referring to fig. 4, a mask layer (not shown) is formed on the sacrificial layer 102, the mask layer is patterned, the patterned mask layer covers an area where the capacitor array is formed in the device region 100A, the peripheral region 100B and an edge portion 100A' of the device region 100A connected to the peripheral region 100B are exposed, and then the sacrificial layer 103 is etched by using the patterned mask layer as a mask until the isolation layer 102 is exposed, and the patterned mask layer is removed.
Next, referring to fig. 5, a body supporting layer 120 is formed on the sacrificial layer 102, where the body supporting layer 120 includes a lateral supporting layer 104 and a longitudinal supporting layer 105, the lateral supporting layer 104 covers an upper surface of the sacrificial layer 103, the longitudinal supporting layer 105 covers a side of the sacrificial layer 103 and the isolation layer 102 on the device region edge portion 100A', the side is a side of the longitudinal supporting layer 105 close to the peripheral region 100B, and the longitudinal supporting layer 105 connects the lateral supporting layer 104 and the isolation layer 102.
The material of the body support layer 120 and the isolation layer 102 includes, but is not limited to, silicon nitride, the material of the sacrificial layer includes, but is not limited to, silicon oxide, and the body support layer 120 and the sacrificial layer 103 may be formed by a deposition process, for example, a chemical vapor deposition process. The body support layer 120 may be formed in a one-step deposition process, or the lateral support layer 104 and the longitudinal support layer 105 may be formed separately in a two-step deposition process. Preferably, in this embodiment, the body support layer 120 may be formed in a one-step deposition process. The thickness of the sacrificial layer 103 defines the height of the subsequently formed lateral support layer 104, and therefore, the thickness of the sacrificial layer 103 can be adjusted according to the height position of the lateral support layer 104 to be formed.
In step S03, please refer to fig. 6, a plurality of through holes 130 are formed in the device region 100A, and the through holes 130 sequentially penetrate through the lateral supporting layer 104, the sacrificial layer 103 and the isolation layer 102 to expose the substrate 100.
Specifically, a mask layer is formed on the lateral support layer 104, the mask layer is patterned to expose a region where a through hole is to be formed, then the lateral support layer 104, the sacrificial layer 103 and the isolation layer 102 are sequentially etched by using the patterned mask layer as a mask to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal shape. It can be understood that, by forming the through hole 130 in the lateral support layer 104 and the sacrificial layer 103, a lower electrode having a cylindrical structure can be formed at the bottom and the sidewall of the through hole 130, and thus, the total height of the lateral support layer 104 and the sacrificial layer 103 can define the height of the cylindrical structure in the subsequently formed lower electrode, so that the height of the subsequently formed capacitor can be increased by increasing the thickness of the sacrificial layer 103, and thus the electrode surface area of the capacitor can be increased, and thus the capacitance value of the formed capacitor can be increased.
In step S04, please refer to fig. 7, a lower electrode 106 is formed in the through hole 130, and the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures.
The lower electrode 106 is located in the through hole 130, and the shape of the lower electrode 106 is consistent with the shape of the through hole 130, so that the lower electrode 106 located in the through hole 130 forms a cylindrical structure. Further, the lower electrode 106 may be a polysilicon electrode or a metal electrode. When the lower electrode 106 is a metal electrode, it may be formed of titanium nitride (TiN), for example.
Specifically, the lower electrode 106 may be formed in combination with a planarization process on the basis of a deposition process, for example, first, an electrode material layer is formed on the substrate 100, the electrode material layer covers the bottom and the sidewall of the through hole 130, and covers the lateral support layer 104; next, a planarization process (e.g., a chemical mechanical polishing process) is performed to remove a portion of the electrode material layer above the lateral support layer 104, so that the remaining electrode material layer is formed only in the through hole 130 to form a bottom electrode with a cylindrical structure.
Preferably, the lower electrode 106 is also formed on the isolation layer on the side of the longitudinal support layer 104 near the peripheral region 100B and the device region edge portion 100A'.
In addition, in the present embodiment, the node contact 101 is exposed through the through hole 130, so that the bottom of the cylindrical structure of the formed lower electrode 106 can be electrically connected to the node contact 101.
In step S05, please refer to fig. 8 to 9, the sacrificial layer 103 is removed, and a capacitance dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor.
Specifically, first, a first opening is formed in the lateral support layer 104 to expose the sacrificial layer 103, and the sacrificial layer 103 is removed by etching, so as to form the structure shown in fig. 8. Wherein one of the first openings overlaps only one of the through holes 130, or one of the first openings overlaps a plurality of the through holes 130 at the same time. After removing the sacrificial layer 103, the lateral support layer 104 connects to the outer wall of the cylindrical structure of the lower electrode 106, and the longitudinal support layer 105 connects the lateral support layer 104 and the isolation layer 102, so that a peripheral-wrapped support structure is formed on the device region 100A.
Then, referring to fig. 9, a capacitor dielectric layer 107 is formed on the inner and outer surfaces of the lower electrode 106 and the exposed surface of the lateral supporting layer 104. The capacitance medium layer 107 covers the inner surface of the cylindrical structure of the lower electrode 106 inside the cylinder and the outer surface of the cylindrical structure outside the cylinder, so that two opposite surfaces of the lower electrode 106 are fully utilized to form an integrated circuit capacitor with a large electrode surface area. Specifically, the capacitor dielectric layer 107 may be formed by a vapor deposition process. Preferably, the capacitor dielectric layer 107 may be a high-K dielectric layer. Further, the capacitor dielectric layer 107 has a multi-layer structure, for example, a two-layer structure of a silicon dioxide layer/a silicon nitride layer, and the silicon dioxide layer and the silicon nitride layer may be sequentially and respectively formed when the capacitor dielectric layer 107 is formed.
Further, in the present embodiment, the bottom of the can outer portion of the can structure of the lower electrode 106 is connected to the node contact 101 formed in the device region 100A, and the outer wall of the can structure of the lower electrode 106 is connected to the lateral support layer 104 and the isolation layer 102, so that the capacitance medium layer 107 does not cover a portion of the can structure bottom of the lower electrode 106, and a portion of the outer wall of the can structure of the lower electrode 106 that is connected to the lateral support layer 104.
Next, as shown in fig. 9, an upper electrode 108 is formed on the inner surface and the outer surface of the capacitor dielectric layer 107. The upper electrode 108, the capacitor dielectric layer 106 and the lower electrode 106 can form a capacitor in both the interior corresponding to the cylindrical structure and the exterior corresponding to the cylindrical structure.
Finally, as shown in fig. 9, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. The upper electrode filling layer 109 covers the upper electrodes 108 and fills gaps between the upper electrodes 108, and the material of the upper electrode filling layer 109 includes boron-doped polysilicon; the upper electrode connection layer 110 covers the outer surface of the upper electrode filling layer 109, and the material of the upper electrode connection layer 110 includes, but is not limited to, tungsten.
In the method for forming a capacitor array structure provided by the embodiment of the invention, the peripheral wrapping type main body supporting layer is formed on the device area, compared with a single transverse supporting layer in the prior art, the boundary of the capacitor array is a flat structure, so that cracks caused by unevenness of the boundary of the capacitor array when filling materials are deposited subsequently are avoided, the problem of short circuit between a plug and the boundary of the capacitor array caused by the cracks is further avoided, the stability of the array area is improved, and the reliability of the capacitor device is improved.
Example two
Compared with the first embodiment, in the present embodiment, at least one lower support layer is formed between the lateral support layer 104 of the main support layer and the isolation layer 102, the lower support layer is parallel to the lateral support layer 104, and one end of the lower support layer is connected to the longitudinal support layer 104. The specific forming steps comprise:
s11: forming a lower laminated structure on the substrate, wherein the lower laminated structure is formed by alternately arranging a sacrificial layer and a lower supporting layer;
s12: forming a body support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;
s13: forming a plurality of through holes, wherein the through holes sequentially penetrate through the transverse supporting layer and the lower laminated structure to expose the substrate;
s14: forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area;
s15: and removing the sacrificial layer, wherein the transverse supporting layer and the lower supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Fig. 10 to fig. 15 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to a second embodiment of the invention. In step S11, referring to fig. 10, a first lower sacrificial layer 210, a first lower supporting layer 201 and a second lower sacrificial layer 220 are sequentially formed on the substrate 100 to form a lower stacked structure 200 in which sacrificial layers and lower supporting layers are alternately disposed. Preferably, an isolation layer 102 is further formed between the first lower sacrificial layer 210 and the substrate 100 for isolating the storage transistor in the substrate 100 from the capacitor device above.
In step S12, please refer to fig. 11, a body supporting layer 120 is formed, the lateral supporting layer 104 covers the upper surface of the lower laminated structure 200, and the longitudinal supporting layer 105 covers the side of the lower laminated structure 200 close to the peripheral area 100B.
First, a mask layer (not shown) is formed on the second lower sacrificial layer 220, the mask layer is patterned, the patterned mask layer covers an area where a capacitor array is formed in the device area 100A, the peripheral area 100B and the edge portion 100A' of the device area 100A connected to the peripheral area 100B are exposed, then the second lower sacrificial layer 220, the first lower supporting layer 201 and the first lower sacrificial layer 210 are sequentially etched by using the patterned mask layer as a mask until the isolation layer 102 is exposed, and the patterned mask layer is removed.
Next, a body support layer 120 is formed on the second lower sacrificial layer 220, the body support layer 120 includes a lateral support layer 104 and a longitudinal support layer 105, the lateral support layer 104 covers an upper surface of the second lower sacrificial layer 220, the longitudinal support layer 105 covers a side of the lower stacked structure 200 and the isolation layer 102 on the device region edge portion 100A', the side is a side of the longitudinal support layer 105 near the peripheral region 100B, and the longitudinal support layer 105 connects the lateral support layer 104 and the isolation layer 102.
The material of the body support layer 120 and the isolation layer 102 includes, but is not limited to, silicon nitride, the material of the sacrificial layer includes, but is not limited to, silicon oxide, and the body support layer 120 and the sacrificial layer can be formed by a deposition process, for example, a chemical vapor deposition process. The thickness of the first lower sacrificial layer 210 defines the height of the subsequently formed first lower support layer 201, and therefore, the thickness of the first lower sacrificial layer 210 can be adjusted according to the height position of the first lower support layer 201 to be formed. The thickness of the second lower sacrificial layer 220 defines the height of the subsequently formed lateral support layer 105, and therefore, the thickness of the second lower sacrificial layer 220 can be adjusted according to the height position of the lateral support layer 105 to be formed.
In step S13, please refer to fig. 12, a plurality of through holes 130 are formed, wherein the through holes 130 sequentially penetrate through the lateral support layer 104 and the lower stacked structure 200 to expose the substrate 100.
Specifically, a mask layer is formed on the lateral support layer 104, the mask layer is patterned to expose a region where a through hole is to be formed, then the lateral support layer 104, the second lower sacrificial layer 220, the first lower support layer 201, the first lower sacrificial layer 210 and the isolation layer 102 are sequentially etched by using the patterned mask layer as a mask to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal shape. It is understood that the lower electrode having a cylindrical structure may be formed at the bottom and the sidewall of the via 130 by forming the via 130 on the lateral support layer 104 and the lower stacked structure 200, and thus, the total height of the lateral support layer 104 and the lower stacked structure 200 may define the height of the cylindrical structure in the subsequently formed lower electrode, so that the height of the subsequently formed capacitor may be increased by increasing the thickness of the first lower sacrificial layer 210 and the second lower sacrificial layer 220, and thus the electrode surface area of the capacitor may be increased, and thus, the capacitance value of the formed capacitor may be increased.
In step S14, please continue to refer to fig. 12, a lower electrode 106 is formed in the through hole 130, and the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures.
The lower electrode 106 is located in the through hole 130, and the shape of the lower electrode 106 is consistent with the shape of the through hole 130, so that the lower electrode 106 located in the through hole 130 forms a cylindrical structure. Further, the lower electrode 106 may be a polysilicon electrode or a metal electrode. When the lower electrode 106 is a metal electrode, it may be formed of titanium nitride (TiN), for example.
Specifically, the lower electrode 106 may be formed in combination with a planarization process on the basis of a deposition process, for example, first, an electrode material layer is formed on the substrate 100, the electrode material layer covers the bottom and the sidewall of the through hole 130, and covers the lateral support layer 104; next, a planarization process (e.g., a chemical mechanical polishing process) is performed to remove a portion of the electrode material layer above the lateral support layer 104, so that the remaining electrode material layer is formed only in the through hole 130 to form a bottom electrode with a cylindrical structure.
Preferably, the lower electrode 106 is also formed on the isolation layer on the side of the longitudinal support layer 105 near the peripheral region 100B and the device region edge portion 100A'.
In addition, in the present embodiment, the node contact 101 is exposed through the through hole 130, so that the bottom of the cylindrical structure of the formed lower electrode 106 can be electrically connected to the node contact 101.
In step S15, please refer to fig. 13, the sacrificial layer is removed, and the lateral support layer 104 and the first lower support layer 201 are connected to the outer wall of the cylindrical structure of the lower electrode 106.
Specifically, first, a first opening is formed in the lateral support layer 104 to expose the second lower sacrificial layer 220, and the second lower sacrificial layer 220 is removed by etching; forming a second opening in the first lower supporting layer 201 and exposing the first lower sacrificial layer 210; etching to remove the first lower sacrificial layer 210; wherein one of the first openings overlaps only one of the through holes 130, or one of the first openings overlaps a plurality of the through holes 130 at the same time; one of the second openings overlaps only one of the through holes 130, or one of the second openings overlaps a plurality of the through holes 130 at the same time. After removing the sacrificial layer 103, the transverse support layer 104 and the first lower support layer 201 are connected to the outer wall of the cylindrical structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the transverse support layer 104, the first lower support layer 201 and the isolation layer 102, so that a peripheral wrapping type support structure is formed on the device region 100A.
Then, referring to fig. 14, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. The specific forming method and please refer to the first embodiment.
In addition, a plurality of lower support layers 200 may also be formed between the lateral support layer 104 and the isolation layer 102, as shown in fig. 15, a first lower support layer 201 and a second lower support layer 202 are formed between the lateral support layer 104 and the isolation layer 102, and detailed description of the forming method is omitted.
EXAMPLE III
Compared with the first embodiment, the present embodiment forms at least one upper support layer on the lateral support layer 104 of the main body support layer, where the upper support layer is parallel to the lateral support layer 104, and one end of the upper support layer is flush with the longitudinal support layer 104 in a direction perpendicular to the base. The specific forming steps comprise:
s21: forming an upper laminated structure on the transverse supporting layer, wherein the upper laminated structure is formed by alternately arranging a sacrificial layer and an upper supporting layer;
s22: forming a plurality of through holes, wherein the through holes sequentially penetrate through the upper laminated structure, the transverse supporting layer and the sacrificial layer to expose the substrate;
s23: forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
s24: and removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Fig. 16 to fig. 20 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to a third embodiment of the invention. In step S21, please refer to FIG. 16, first, the lateral body support layer 120 is formed in steps S01-S02 according to the first embodiment. Then, a first upper sacrificial layer 310 and a first upper support layer 301 are sequentially formed on the lateral support layer 104 to constitute an upper stacked structure 300.
In step S21, please refer to fig. 17, a plurality of vias 130 are formed, wherein the vias 130 sequentially penetrate through the upper stacked structure 300, the lateral supporting layer 104 and the sacrificial layer 103 to expose the substrate 100.
Specifically, a mask layer is formed on the first upper support layer 301, the mask layer is patterned to expose a region where a through hole is to be formed, then the first upper support layer 301, the first upper sacrificial layer 310, the lateral support layer 104, the sacrificial layer 103, and the isolation layer 102 are sequentially etched by using the patterned mask layer as a mask to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal shape.
In step S23, please continue to refer to fig. 17, a lower electrode 106 is formed to cover the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures. Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 105 near the peripheral region 100B and the side of the upper stacked structure 300 near the peripheral region.
In step S23, please refer to fig. 18, the sacrificial layer is removed, and the upper support layer 300 and the lateral support layer 104 are connected to the outer wall of the cylindrical structure of the lower electrode 106.
Specifically, first, a first opening is formed in the first upper support layer 301 to expose the first upper sacrificial layer 310, and the first upper sacrificial layer 310 is removed by etching; forming a second opening on the transverse supporting layer 104 and exposing the sacrificial layer 103, and etching to remove the sacrificial layer 103; wherein one of the first openings overlaps only one of the through holes 130, or one of the first openings overlaps a plurality of the through holes 130 at the same time; one of the second openings overlaps only one of the through holes 130, or one of the second openings overlaps a plurality of the through holes 130 at the same time.
After removing the sacrificial layer, the first upper support layer 301 and the lateral support layer 104 connect to the outer wall of the cylindrical structure of the lower electrode 106, and the longitudinal support layer 105 connects the lateral support layer 104 and the isolation layer 102, so that a periphery-wrapped support structure is formed on the device region 100A. Furthermore, in this embodiment, one end of the first upper supporting layer 301 is flush with the longitudinal supporting layer 105 in a direction perpendicular to the substrate, and the lower electrode 106 is formed on the side of the longitudinal supporting layer 105 near the peripheral region 100B and extends and connects to the first upper supporting layer 301 in the direction perpendicular to the substrate 100, so that the flatness of the capacitor array boundary is ensured, cracks caused by unevenness of the capacitor array boundary during subsequent deposition of a filling material are avoided, and the problem of short circuit between a plug and the capacitor array boundary due to the cracks is avoided, and the reliability of a capacitor device is improved while the stability of the array region is increased.
Then, referring to fig. 19, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. Please refer to the first embodiment.
In addition, a plurality of upper support layers may be formed on the lateral support layer 104, as shown in fig. 20, a first upper support layer 301 and a second upper support layer 302 are formed on the lateral support layer 104, and a specific forming method is not described again.
Example four
In this embodiment, compared to the first embodiment, in the present embodiment, at least one lower support layer is formed between the lateral support layer 104 of the main body support layer 120 and the substrate 100, and at least one upper support layer is formed on the lateral support layer 105. The specific forming method comprises the following steps:
s31: forming a lower stacked structure 200 in which a sacrificial layer and a lower support layer are alternately disposed on the substrate 100;
s32: forming a body support layer 120, wherein the transverse support layer 104 covers the upper surface of the lower laminate structure 200, and the longitudinal support layer 105 covers the side of the lower laminate structure 200 close to the peripheral region;
s33: forming an upper stacked structure 300 in which sacrificial layers and upper support layers are alternately arranged on the lateral support layer 104;
s34: forming a plurality of through holes 130 sequentially penetrating the upper stacked structure 300, the lateral support layer 105, and the lower stacked structure 300 to expose the substrate 100;
s35: forming a lower electrode 106, wherein the lower electrode 106 covers the side wall and the bottom of the through hole 130 to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
s36: the sacrificial layer is removed and the upper and lateral support layers 104 and 200 connect the outer walls of the lower electrode can.
Fig. 21 to 23 are schematic cross-sectional views illustrating corresponding steps in a method for forming a capacitor array structure according to a fourth embodiment of the invention. Referring to fig. 21 in combination with the second embodiment of the present invention, step S31 and step S32 are executed. In step S31, a first lower sacrificial layer 210, a first lower support layer 201, and a second lower sacrificial layer 220 are sequentially formed on the substrate 100 to form a lower stacked structure 200 in which sacrificial layers and lower support layers are alternately arranged. Preferably, an isolation layer 102 is further formed between the first lower sacrificial layer 210 and the substrate 100 for isolating the storage transistor in the substrate 100 from the capacitor device above.
In step S32, a body support layer 120 is formed, the transverse support layer 104 covers the upper surface of the lower laminated structure 210, and the longitudinal support layer 105 covers the side of the lower laminated structure 210 close to the peripheral area 100B.
Referring to fig. 21 and 22 in combination with the third embodiment of the present invention, steps S33 to S36 are executed. First, in step S33, a first upper sacrificial layer 310 and a first upper support layer 301 are sequentially formed on the lateral support layer 104 to form an upper stacked structure 300.
In step S34, a plurality of vias 130 are formed, wherein the vias 130 sequentially penetrate through the upper stacked structure 300, the lateral support layer 104, the lower stacked structure 200 and the isolation layer 102 to expose the substrate 100.
In step S35, a lower electrode 106 is formed to cover the sidewall and the bottom of the via 130 to form a plurality of cylindrical structures. Preferably, a lower electrode 106 is also formed on the side of the vertical support layer 105 near the peripheral region 100B and the side of the upper stacked structure 300 near the peripheral region, and further, the lower electrode 106 also covers the isolation layer 102 on the device region edge portion 100A'.
In step S36, the sacrificial layer is removed, and the upper and lateral support layers 104 and the lower support layer connect the outer walls of the lower electrode 106 barrel structure, as shown in fig. 22.
Then, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108.
Further, a plurality of lower support layers may be formed between the lateral support layer 104 of the body support layer 120 and the base 100, and a plurality of upper support layers may be formed on the lateral support layer 104. As shown in fig. 23, a first lower support layer 201 and a second lower support layer 202 are formed between a lateral support layer 104 of a main body support layer 120 and the substrate 100, and a first upper support layer 301 and a second upper support layer 302 are formed on the lateral support layer 104, which is not described again.
EXAMPLE five
The present invention further provides a capacitor array structure, please refer to fig. 9, which includes: a plurality of capacitors that are arranged in the substrate device area and are distributed in an array, each of the capacitors includes: a lower electrode 106, a capacitor dielectric layer 107 and an upper electrode 108; wherein the lower electrode 106 is disposed on the substrate 100, and the lower electrode 106 has a plurality of cylindrical structures; the capacitor dielectric layer 107 is arranged on the inner surface and the outer surface of the lower electrode 106; the upper electrode 108 is arranged on the outer surface of the capacitor dielectric layer 107;
a body support layer 120 comprising a transverse support layer 104 and a longitudinal support layer 105; wherein the lateral support layer 104 is disposed on the device region 100A, and the lateral support layer 104 connects the outer wall of the lower electrode 106 barrel structure; the longitudinal support layer 105 is disposed at one end of the transverse support layer 104, and the longitudinal support layer 105 connects the transverse support layer 104 and the base 100; a lower electrode 106 is disposed on a side of the longitudinal support layer 105 different from the lateral support layer 104.
Preferably, as shown in fig. 14, at least one lower support layer (a first lower support layer 201) is disposed between the transverse support layer 104 and the substrate 100, the lower support layer is connected to the outer wall of the cylindrical structure of the lower electrode 106, and one end of the lower support layer is connected to the longitudinal support layer 104. And a lower electrode is arranged on one side of the longitudinal support layer 105 different from the transverse support layer 104.
Preferably, as shown in fig. 19, at least one upper support layer (a first upper support layer 301) is disposed on the transverse support layer 104, the upper support layer is connected to the outer wall of the cylindrical structure of the lower electrode 106, and one end of the upper support layer is flush with the longitudinal support layer 105 in a direction perpendicular to the substrate 100.
Preferably, the side of the longitudinal support layer 105 close to the peripheral region 100B is provided with a lower electrode 106, which is connected to an upper support layer extending in a direction perpendicular to the substrate 100, and the flatness of the capacitor array boundary is ensured because the upper support layer and the longitudinal support layer 105 are kept flush in the direction perpendicular to the substrate 100. ,
preferably, at least one lower support layer is disposed between the lateral support layer 104 and the base 100, and at least one upper support layer is disposed on the lateral support layer. Wherein, the lower support layer and the upper support layer are connected with the outer wall of the cylindrical structure of the lower electrode 106, one end of the lower support layer is connected with the longitudinal support layer 105, and one end of the upper support layer is flush with the longitudinal support layer 105 in the direction vertical to the substrate. Preferably, a lower electrode 106 is disposed on a side of the longitudinal support layer 105 different from the lateral support layer 104, and the lower electrode 106 is connected to the upper support layer in an extending manner.
Preferably, an isolation layer 102 is further disposed on the substrate 100, and the isolation layer 102 is disposed on the bottom periphery of the cylindrical structure of the lower electrode 106 and covers the device region edge portion 100A'. The capacitor array structure further includes a plurality of node contacts 101 located in the substrate 100, and the bottom of the lower electrode 106 cylindrical structure is connected to the node contacts.
Preferably, the material of the body support layer 120, the upper support layer, the lower support layer and the isolation layer 102 includes, but is not limited to, silicon nitride, and the body support layer 120 may be formed by a deposition process, such as a chemical vapor deposition process. The body support layer 120 may be formed in a one-step deposition process, or the lateral support layer 104 and the longitudinal support layer 105 may be formed separately in a two-step deposition process.
Preferably, the capacitor array structure further includes an electrode filling layer 109 and an electrode connection layer 110. The upper electrode filling layer 109 covers the upper electrodes 108 and fills gaps between the upper electrodes 108, and the material of the upper electrode filling layer 109 includes boron-doped polysilicon; the upper electrode connection layer 110 covers the outer surface of the upper electrode filling layer 109, and the material of the upper electrode connection layer 110 includes, but is not limited to, tungsten.
In the embodiment of the invention, the main body supporting layer is arranged, and the peripheral wrapping type supporting structure is formed on the device area, compared with the single transverse supporting layer in the prior art, the boundary of the capacitor array in the embodiment is a flat structure, so that the problem of short circuit between a plug and the boundary of the capacitor array caused by cracks due to uneven boundary of the capacitor array when filling materials are deposited subsequently is avoided, and the reliability of the capacitor device is improved while the stability of the array area is increased.
Further, the present invention also provides a semiconductor device comprising the capacitor array mechanism as described above. The semiconductor device is applied to a dynamic random access memory.
In summary, the present invention provides a capacitor array structure, a forming method thereof, and a semiconductor device, wherein a peripheral wrapping type main body supporting layer is formed on a device region to obtain a flat capacitor array boundary, so as to prevent cracks from being formed due to unevenness of the capacitor array boundary when a filling material is subsequently deposited, thereby preventing a short circuit between a plug and the capacitor array boundary due to the cracks, and improving reliability of the capacitor device while increasing stability of the array region.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (20)
1. A method of forming a capacitor array structure, comprising:
providing a substrate, wherein the substrate is provided with a device area for forming a capacitor and a peripheral area positioned at the periphery of the device area;
forming a sacrificial layer and a main body supporting layer in the device area, wherein the main body supporting layer comprises a transverse supporting layer and a longitudinal supporting layer, the transverse supporting layer covers the upper surface of the sacrificial layer, the longitudinal supporting layer covers the side surface, close to the peripheral area, of the sacrificial layer, and the longitudinal supporting layer is connected with the transverse supporting layer and the substrate;
forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate through the transverse supporting layer and the sacrificial layer to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
and removing the sacrificial layer, and sequentially forming a capacitance dielectric layer and an upper electrode on the inner surface and the outer surface of the lower electrode to form the capacitor.
2. The method of forming a capacitor array structure of claim 1 wherein at least one lower support layer is formed between said lateral support layer and said substrate, said lower support layer being parallel to said lateral support layer and said lower support layer being connected at one end to said longitudinal support layer.
3. The method of forming a capacitor array structure of claim 2, wherein the method of forming the lower support layer comprises:
forming a lower laminated structure on the substrate, wherein the lower laminated structure is formed by alternately arranging a sacrificial layer and a lower supporting layer;
forming a body support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;
forming a plurality of through holes, wherein the through holes sequentially penetrate through the transverse supporting layer and the lower laminated structure to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area;
and removing the sacrificial layer, wherein the transverse supporting layer and the lower supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
4. The method of forming a capacitor array structure as claimed in claim 1, wherein said lateral support layer has at least one upper support layer formed thereon, said upper support layer being parallel to said lateral support layer, and one end of said upper support layer being flush with said longitudinal support layer in a direction perpendicular to said base.
5. The method of forming a capacitor array structure of claim 4, wherein the method of forming the upper support layer comprises:
forming an upper laminated structure on the transverse supporting layer, wherein the upper laminated structure is formed by alternately arranging a sacrificial layer and an upper supporting layer;
forming a plurality of through holes, wherein the through holes sequentially penetrate through the upper laminated structure, the transverse supporting layer and the sacrificial layer to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
and removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
6. The method of forming a capacitor array structure of claim 1, wherein at least one lower support layer is formed between said lateral support layer and said substrate, and at least one upper support layer is formed on said lateral support layer;
the upper supporting layer and the lower supporting layer are parallel to the transverse supporting layer, one end of the lower supporting layer is connected with the longitudinal supporting layer, and one end of the upper supporting layer is flush with the longitudinal supporting layer in the direction perpendicular to the base.
7. The method of forming a capacitor array structure of claim 6, wherein the method of forming the upper support layer and the lower support layer comprises:
forming a lower laminated structure on the substrate, wherein the lower laminated structure is formed by alternately arranging a sacrificial layer and a lower supporting layer;
forming a body support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;
forming an upper laminated structure on the transverse supporting layer, wherein the upper laminated structure is formed by alternately arranging a sacrificial layer and an upper supporting layer;
forming a plurality of through holes which sequentially penetrate through the upper laminated structure, the transverse supporting layer and the lower laminated structure to expose the substrate;
forming a lower electrode covering the side wall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
and removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
8. The method as claimed in any one of claims 1 to 7, wherein an isolation layer is further formed between the sacrificial layer and the substrate, and the isolation layer is disposed at the bottom periphery of the lower electrode cylindrical structure.
9. The method of forming a capacitor array structure according to any one of claims 1 to 7, wherein a plurality of node contacts are formed in the substrate, the via holes expose the node contacts, and the lower electrode is connected to the node contacts at the bottom of the via holes.
10. The method of any of claims 1-7, wherein the material of the body support layer, the upper support layer, and the lower support layer comprises silicon nitride, and the material of the sacrificial layer comprises silicon oxide.
11. A capacitor array structure, comprising:
a plurality of capacitors that are arranged in the substrate device area and are distributed in an array, each of the capacitors includes: the capacitor comprises a lower electrode, a capacitor dielectric layer and an upper electrode; the lower electrode is arranged on the substrate and has a plurality of cylindrical structures; the capacitor dielectric layer is arranged on the inner surface and the outer surface of the lower electrode; the upper electrode is arranged on the outer surface of the capacitor dielectric layer;
a body support layer comprising a lateral support layer and a longitudinal support layer; the transverse supporting layer is arranged on the device area and is connected with the outer wall of the lower electrode cylindrical structure; the longitudinal supporting layer is arranged at one end of the transverse supporting layer and is connected with the transverse supporting layer and the base; and a lower electrode is arranged on one side surface of the longitudinal supporting layer, which is different from the transverse supporting layer.
12. The capacitor array structure of claim 11, wherein at least a lower support layer is disposed between the lateral support layer and the substrate, the lower support layer connecting the outer walls of the lower electrode can, and the lower support layer connecting the longitudinal support layer at one end.
13. The capacitor array structure of claim 11, wherein the lateral support layer has at least one upper support layer disposed thereon, the upper support layer connecting the outer walls of the lower electrode can structures, and the upper support layer having one end flush with the longitudinal support layer in a direction perpendicular to the base.
14. The capacitor array structure of claim 11, wherein at least one lower support layer is disposed between the lateral support layer and the substrate, and wherein at least one upper support layer is disposed on the lateral support layer.
15. The capacitor array structure of claim 14, wherein the lower support layer and the upper support layer connect to the outer walls of the lower electrode can, the lower support layer connecting to the longitudinal support layer at one end, the upper support layer remaining flush with the longitudinal support layer in a direction perpendicular to the base.
16. The capacitor array structure of claim 13 or 15, wherein the lower electrode disposed on a side of the longitudinal support layer other than the lateral support layer extends to connect to the upper support layer.
17. The capacitor array structure of any one of claims 11 to 16, wherein an isolation layer is further disposed on the substrate, the isolation layer being disposed at a bottom periphery of the lower electrode cylindrical structure; the capacitor array structure further comprises a plurality of node contacts located in the substrate, and the bottom of the lower electrode cylindrical structure is connected with the node contacts.
18. The electrical array structure of any one of claims 11 to 17, wherein the material of the main support layer, the upper support layer, the lower support layer and the isolation layer comprises silicon nitride.
19. A semiconductor device comprising the capacitor array structure according to any one of claims 11 to 18.
20. The semiconductor device according to claim 19, wherein the semiconductor device is applied to a dynamic random access memory.
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| WO2022088740A1 (en) * | 2020-11-02 | 2022-05-05 | 长鑫存储技术有限公司 | Semiconductor structure and formation method thereof |
| CN114446884A (en) * | 2020-11-02 | 2022-05-06 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN114446884B (en) * | 2020-11-02 | 2024-05-21 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| US12120862B2 (en) | 2020-11-02 | 2024-10-15 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for forming semiconductor structure |
| CN114639638A (en) * | 2022-04-29 | 2022-06-17 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| WO2024148797A1 (en) * | 2023-01-09 | 2024-07-18 | 长鑫存储技术有限公司 | Semiconductor device and preparation method therefor |
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