CN114284136A - Method for forming semiconductor structure - Google Patents
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- CN114284136A CN114284136A CN202111554731.7A CN202111554731A CN114284136A CN 114284136 A CN114284136 A CN 114284136A CN 202111554731 A CN202111554731 A CN 202111554731A CN 114284136 A CN114284136 A CN 114284136A
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Abstract
A method of forming a semiconductor structure, comprising: providing a substrate; forming a sacrificial structure on a substrate; forming isolation dielectric layers on the surface of the side wall and the surface of the top of the sacrificial structure; forming a first epitaxial layer on the substrate, wherein the first epitaxial layer exposes the top and the side wall surface of part of the isolation dielectric layer, and a second epitaxial layer is formed on the exposed surface of the isolation dielectric layer; modifying the first epitaxial layer and the second epitaxial layer, forming a first sacrificial layer on the surface of the first epitaxial layer, and converting the second epitaxial layer into a second sacrificial layer; after a first sacrificial layer and a second sacrificial layer are formed, carrying out ion implantation on the first epitaxial layer; and after the first epitaxial layer is subjected to ion implantation, removing the first sacrificial layer, the second sacrificial layer and the isolation medium layer. The forming method of the semiconductor structure improves the electrical performance of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor structure.
Background
With the continuous development of semiconductor technology, the size of various semiconductor devices is continuously decreasing. In the current semiconductor structure, a silicon germanium epitaxial layer structure is usually introduced to better improve the performance of a highly integrated semiconductor device.
However, in the current sige epitaxial process, defects are easily introduced in the sige epitaxial layer growth process, and in addition, the surface of the sige epitaxial layer is easily damaged by the ion implantation process of the sige epitaxial layer, and the ion implantation effect still needs to be improved, so that the electrical performance of the device is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for forming a semiconductor structure, which reduces the defects introduced in the growth process of the silicon-germanium epitaxial layer, improves the surface appearance of the silicon-germanium epitaxial layer after ion implantation, and improves the effect of the ion implantation, thereby improving the electrical performance of a device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a sacrificial structure on a substrate; forming isolation dielectric layers on the surface of the side wall and the surface of the top of the sacrificial structure; forming a first epitaxial layer on the substrate, wherein the first epitaxial layer exposes the top and the side wall surface of part of the isolation dielectric layer, and a second epitaxial layer is formed on the exposed surface of the isolation dielectric layer; modifying the first epitaxial layer and the second epitaxial layer, forming a first sacrificial layer on the surface of the first epitaxial layer, and converting the second epitaxial layer into a second sacrificial layer; after a first sacrificial layer and a second sacrificial layer are formed, carrying out ion implantation on the first epitaxial layer; and after the first epitaxial layer is subjected to ion implantation, removing the first sacrificial layer, the second sacrificial layer and the isolation medium layer.
Optionally, the substrate includes: the epitaxial structure comprises a substrate, an active region and an isolation structure which are positioned in the substrate, and an initial epitaxial layer positioned on the substrate.
Optionally, the method for forming the semiconductor structure further includes: forming an initial oxide layer on the substrate before forming the sacrificial structure, wherein the sacrificial structure is formed on the initial oxide layer.
Optionally, the material of the initial epitaxial layer comprises silicon germanium.
Optionally, the method for forming the isolation dielectric layer includes: forming an initial isolation dielectric layer on the initial oxide layer and the sacrificial structure; and etching back the initial isolation dielectric layer until the surface of the initial oxide layer is exposed, thereby forming the isolation dielectric layer.
Optionally, the method for etching back the initial isolation dielectric layer includes dry etching.
Optionally, the method for forming the semiconductor structure further includes: after the isolation medium layer is formed, etching the sacrificial structure and the initial oxide layers on two sides of the isolation medium layer until the surface of the substrate is exposed before the first epitaxial layer is formed, so that oxide layers between the substrate and the sacrificial structure and between the substrate and the isolation medium layer are formed.
Optionally, the method for etching the initial oxide layer includes wet etching.
Optionally, the material of the isolation dielectric layer includes silicon nitride.
Optionally, the material of the first epitaxial layer includes silicon germanium; the material of the second epitaxial layer includes silicon germanium.
Optionally, the forming process of the first epitaxial layer includes a selective epitaxial growth process.
Optionally, the method for modifying the first epitaxial layer and the second epitaxial layer includes oxidation treatment or nitridation treatment.
Optionally, the oxidation treatment process includes: wet oxidation treatment process, chemical vapor deposition oxidation process, or in-situ water vapor generation process.
Optionally, the nitridation process includes a plasma nitridation process.
Optionally, the material of the first sacrificial layer includes silicon oxide or silicon nitride, and the material of the second sacrificial layer includes silicon oxide or silicon nitride.
Optionally, the method for removing the first sacrificial layer, the second sacrificial layer and the isolation dielectric layer includes wet etching.
Optionally, after removing the first sacrificial layer, the second sacrificial layer, and the isolation dielectric layer, an interlayer dielectric layer is formed on the first epitaxial layer and the sacrificial structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the second epitaxial layer is converted into the second sacrificial layer and the second sacrificial layer is removed, so that the second epitaxial layer remained on the surface of the isolation medium layer in the process of forming the first epitaxial layer is better removed, the defects caused by the existence of the second epitaxial layer are avoided, and the electrical performance of the semiconductor device is improved. Secondly, because the first sacrificial layer is formed on the surface of the first epitaxial layer, the first sacrificial layer is used as a protective layer of the first epitaxial layer in the process of ion implantation of the first epitaxial layer, so that the damage to the surface of the first epitaxial layer in the process of ion implantation is reduced, and the first epitaxial layer still maintains a relatively perfect surface appearance after the ion implantation is finished; meanwhile, the first sacrificial layer effectively controls the depth of ion implantation, reduces the generation of a tunnel effect, improves the effect of ion implantation and improves the performance of a semiconductor device.
Further, since the material of the first sacrificial layer comprises silicon nitride or silicon oxide, the material of the second sacrificial layer comprises silicon nitride or silicon oxide, and the material of the isolation dielectric layer comprises silicon nitride, the process for removing the first sacrificial layer and the second sacrificial layer is similar to the process for removing the isolation dielectric layer, so that the first sacrificial layer and the second sacrificial layer can be removed at the same time when the isolation dielectric layer is removed, and the process steps are simplified.
Drawings
FIGS. 1-3 are schematic cross-sectional views illustrating a process for forming a semiconductor structure;
fig. 4-10 are cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background art, in the current sige epitaxial process, defects are easily introduced in the sige epitaxial layer growth process, and in addition, the surface of the sige epitaxial layer is easily damaged by the ion implantation process of the sige epitaxial layer, and the ion implantation effect still needs to be improved, so that the electrical performance of the device is reduced.
Fig. 1-3 are cross-sectional views illustrating a process of forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes a base 100 and a sacrificial structure 101 on the base; an isolation dielectric layer 102 is formed on the sacrificial structure 101, and the isolation dielectric layer 102 covers the sidewall and the top surface of the sacrificial structure 101.
Referring to fig. 2, a first epitaxial layer 103 is formed on the substrate 100, the first epitaxial layer 103 exposes a portion of the top and sidewall surfaces of the isolation dielectric layer 102, and a second epitaxial layer 104 is formed on the exposed surface of the isolation dielectric layer 102. The material of the first epitaxial layer 103 comprises silicon germanium; the material of the second epitaxial layer 104 includes silicon germanium.
Referring to fig. 3, after the first epitaxial layer 103 is formed, ion implantation is performed on the first epitaxial layer 103.
As part of the silicon germanium material is deposited on the surface of the isolation dielectric layer 102 during the process of forming the first epitaxial layer 103, the second epitaxial layer 104 is formed. The presence of the second epitaxial layer 104 introduces additional defects to the semiconductor structure during subsequent processing, thereby degrading the electrical performance of the device.
In addition, the surface of the first epitaxial layer 103 is easily damaged in the process of ion implantation into the first epitaxial layer 103, which affects the reliability of the subsequent process, and meanwhile, the depth of ion implantation is difficult to control, so that the effect of ion implantation needs to be improved, and the electrical performance of the formed device is poor.
In order to solve the technical problem, according to the forming method of the semiconductor structure provided by the technical scheme of the invention, a first sacrificial layer is formed on the surface of a first epitaxial layer by modifying the formed first epitaxial layer and a second epitaxial layer positioned on the partial surface of an isolation medium layer, and the second epitaxial layer is converted into a second sacrificial layer. Therefore, the second epitaxial layer is removed by removing the second sacrificial layer, and the defects caused by the existence of the second epitaxial layer are avoided; in addition, due to the existence of the first sacrificial layer, the damage on the surface of the first epitaxial layer in the ion implantation process is reduced, the ion implantation effect is improved, and the performance of the semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4-10 are cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided.
In this embodiment, the substrate 200 includes: a substrate 201, an active region (not shown) and an isolation structure 203 located within the substrate 201, and an initial epitaxial layer 202 located on the substrate 201.
The material of the substrate 201 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. In this embodiment, the substrate 201 is made of silicon.
The isolation structure 203 is used to isolate the active region. In the present embodiment, the material of the isolation structure 203 includes silicon oxide.
The presence of the initial epitaxial layer 202 facilitates better subsequent formation of the first epitaxial layer on the substrate 200. In this embodiment, the material of the initial epitaxial layer 202 includes silicon germanium. The process of forming the initial epitaxial layer 202 includes a selective epitaxial growth process.
Referring to fig. 5, an initial oxide layer 204 is formed on the substrate 200; a sacrificial structure 205 is formed on the initial oxide layer 204.
In the present embodiment, the initial oxide layer 204 serves as an etch stop layer for a subsequently formed sacrificial structure 205 and an isolation dielectric layer. The material of the initial oxide layer 204 is silicon oxide. The method for forming the initial oxide layer 204 includes a chemical vapor deposition process.
In this embodiment, the material of the sacrificial structure 205 includes polysilicon. The pattern of the sacrificial structures 205 projected onto the surface of the substrate 200 is located between the pattern of the isolation structures 203 projected onto the surface of the substrate 200.
Referring to fig. 6, an isolation dielectric layer 206 is formed on the sidewall surface and the top surface of the sacrificial structure 205.
The isolation dielectric layer 206 serves as a protective layer on the surface of the sacrificial structure 205, so that unnecessary deposition on the surface of the sacrificial structure 205 is avoided in the subsequent process of forming the first epitaxial layer on the surface of the substrate 200, and the influence of the formation process of the first epitaxial layer on the sacrificial structure 205 is reduced.
The forming method of the isolation dielectric layer 206 comprises the following steps: forming an initial isolation dielectric layer on the initial oxide layer 204 and the sacrificial structure 205; and etching back the initial isolation dielectric layer until the surface of the initial oxide layer 204 is exposed, thereby forming an isolation dielectric layer 206.
In this embodiment, the method for forming the initial isolation dielectric layer includes chemical vapor deposition.
The purpose of etching back the initial isolation dielectric layer is to remove the initial isolation dielectric layer on the surface of the initial oxide layer 204, so that a first epitaxial layer 208 can be formed on the substrate 200 subsequently. The process for etching back the initial isolation dielectric layer comprises dry etching.
In the present embodiment, the material of the isolation dielectric layer 206 includes silicon nitride.
In this embodiment, the method for forming a semiconductor structure further includes: after the isolation dielectric layer 206 is formed, the sacrificial structure 205 and the initial oxide layer 204 on both sides of the isolation dielectric layer 206 are etched until the surface of the substrate 200 is exposed, so as to form an oxide layer 207 between the substrate 200 and the sacrificial structure 205 and between the substrate 200 and the isolation dielectric layer 206.
Since the sacrificial structure 205 and the initial oxide layer 204 on both sides of the isolation dielectric layer 206 are etched and removed to expose the surface of the initial epitaxial layer 202 in the substrate 200, an epitaxial growth process can be subsequently performed on the initial epitaxial layer 202 to form a first epitaxial layer.
In this embodiment, the method for etching the initial oxide layer 204 includes wet etching.
Referring to fig. 7, a first epitaxial layer 208 is formed on the substrate 200, the first epitaxial layer 208 exposes a portion of the top and sidewall surfaces of the isolation dielectric layer 206, and a second epitaxial layer 209 is formed on the exposed surface of the isolation dielectric layer 206.
In the present embodiment, the material of the first epitaxial layer 208 includes silicon germanium. The formation process of the first epitaxial layer 208 includes a selective epitaxial growth process. The material of the second epitaxial layer 209 comprises silicon germanium.
A small amount of silicon germanium is deposited on the top and sidewall surfaces of the isolation dielectric layer 206 while the first epitaxial layer 208 is formed on the substrate 200. Since the top surface of the first epitaxial layer 208 is lower than the top surface of the isolation dielectric layer 206 after the first epitaxial layer 208 is formed, the top and sidewall surfaces of the isolation dielectric layer 206 exposed by the first epitaxial layer 208 are covered by a small amount of sige, thereby forming a second epitaxial layer 209 on a portion of the surface of the isolation dielectric layer 206.
Since the material of the isolation dielectric layer 206 is different from that of the second epitaxial layer 209, and the removal processes of the isolation dielectric layer 206 and the second epitaxial layer 209 are different, the second epitaxial layer 209 cannot be completely removed in the subsequent process of removing the isolation dielectric layer 206. The presence of the second epitaxial layer 209 introduces additional defects into the semiconductor structure, thereby degrading the electrical performance of the device and affecting the process window for subsequent device fabrication.
Referring to fig. 8, the first epitaxial layer 208 and the second epitaxial layer 209 are modified, a first sacrificial layer 210 is formed on the surface of the first epitaxial layer 208, and the second epitaxial layer 209 is converted into a second sacrificial layer 211.
The second epitaxial layer 209 is converted into the second sacrificial layer 211 which is easier to remove, and the second sacrificial layer 211 is removed, so that the second epitaxial layer 209 remained on the surface of the isolation dielectric layer 206 can be more thoroughly removed, defects caused by the existence of the second epitaxial layer 209 are avoided, and the electrical performance of the semiconductor device and the process window of device manufacturing are improved.
In addition, since the first sacrificial layer 210 is formed on the surface of the first epitaxial layer 208, in the subsequent process of ion implantation into the first epitaxial layer 208, the first sacrificial layer 210 serves as a protective layer for the first epitaxial layer 208, so that damage to the surface of the first epitaxial layer 208 in the ion implantation process is reduced, and the first epitaxial layer 208 still maintains a relatively perfect surface topography after the ion implantation is completed; meanwhile, the crystals of the first sacrificial layer 210 are more uniformly arranged, so that the uniformity of ion implantation is improved, the depth of ion implantation is effectively controlled, the generation of a tunnel effect is reduced, and the performance of a semiconductor device is improved.
Specifically, in this embodiment, the method for modifying the first epitaxial layer 208 and the second epitaxial layer 209 includes an oxidation process or a nitridation process. The material of the first sacrificial layer 210 includes silicon oxide or silicon nitride, and the material of the second sacrificial layer 211 includes silicon oxide or silicon nitride.
Since the isolation dielectric layer 206 is made of silicon nitride, when the first sacrificial layer 210 and the second sacrificial layer 211 are made of silicon nitride, the isolation dielectric layer 206 can be subsequently removed while the first sacrificial layer 210 and the second sacrificial layer 211 are removed, thereby simplifying the process steps. In addition, when the first sacrificial layer 210 and the second sacrificial layer 211 are made of silicon oxide, since the process of removing silicon oxide is similar to the process of removing silicon nitride, the first sacrificial layer 210 and the second sacrificial layer 211 can be removed while the isolation dielectric layer 206 is removed, thereby simplifying the process steps.
In this embodiment, the oxidation process includes: wet oxidation treatment process, chemical vapor deposition oxidation process, or in-situ water vapor generation process. The nitridation treatment process comprises a plasma nitridation treatment process.
Referring to fig. 9, after forming a first sacrificial layer 210 and a second sacrificial layer 211, ion implantation is performed on the first epitaxial layer 208.
In the present embodiment, the ion implantation is used to adjust the electrical property of the first epitaxial layer 208 to better engage with the subsequent Bi-CMOS process.
In the ion implantation process, due to the existence of the first sacrificial layer 210, the uniformity of the ion implantation is improved, the generation of the tunnel effect is reduced, and the depth of the ion implantation in the first epitaxial layer 208 is effectively controlled, so that the effect of the ion implantation is improved. In addition, the first sacrificial layer 210 serves as a protective layer of the first epitaxial layer 208, so that damage to the surface of the first epitaxial layer 208 in the ion implantation process is reduced, and after the first sacrificial layer 210 is subsequently removed, the surface of the first epitaxial layer 208 has a relatively perfect surface topography, so that a process window for subsequent device preparation is favorably improved, and the performance of a semiconductor device is improved.
In this embodiment, the ions used for the ion implantation include boron ions or arsenic ions.
Referring to fig. 10, after ion implantation is performed on the first epitaxial layer 208, the first sacrificial layer 210, the second sacrificial layer 211 and the isolation dielectric layer 206 are removed.
By removing the second sacrificial layer 211, the second epitaxial layer 209 remained on the surface of the isolation dielectric layer 206 in the process of forming the first epitaxial layer 208 is more thoroughly removed, so that the defects caused by the existence of the second epitaxial layer 209 are avoided, and the electrical performance of the semiconductor device is improved.
By removing the first sacrificial layer 210, the surface of the first epitaxial layer 208 with perfect surface topography is exposed to engage with other processes on the surface of the first epitaxial layer 208. The surface topography of the first epitaxial layer 208 is good, so that a process window of subsequent device preparation is improved, and the performance of a semiconductor device is improved.
Therefore, after the first sacrificial layer 210, the second sacrificial layer 211 and the isolation dielectric layer 206 are removed, the sacrificial structure 205 with a perfect surface topography and the first epitaxial layer 208 are exposed, and defects introduced in the formation process of the semiconductor structure are reduced, so that the uniformity of the structures formed on the surfaces of the sacrificial structure 205 and the first epitaxial layer 208 subsequently is improved, and the performance of the device is improved.
In this embodiment, since the processes for removing the isolation dielectric layer 206, the first sacrificial layer 210 and the second sacrificial layer 211 are the same or similar, the first sacrificial layer 210 and the second sacrificial layer 211 can be removed while the isolation dielectric layer 206 is removed, thereby simplifying the process steps and improving the process reliability.
In this embodiment, the method for removing the first sacrificial layer 210, the second sacrificial layer 211 and the isolation dielectric layer 206 includes wet etching.
In this embodiment, the method for forming a semiconductor structure further includes: after removing the first sacrificial layer 210, the second sacrificial layer 211 and the isolation dielectric layer 206, an interlayer dielectric layer is formed on the first epitaxial layer 208 and the sacrificial structure 205.
The method for forming the semiconductor structure set forth in this embodiment may be applied to a process for manufacturing a Heterojunction Bipolar Transistor (HBT) device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a sacrificial structure on a substrate;
forming isolation dielectric layers on the surface of the side wall and the surface of the top of the sacrificial structure;
forming a first epitaxial layer on the substrate, wherein the first epitaxial layer exposes the top and the side wall surface of part of the isolation dielectric layer, and a second epitaxial layer is formed on the exposed surface of the isolation dielectric layer;
modifying the first epitaxial layer and the second epitaxial layer, forming a first sacrificial layer on the surface of the first epitaxial layer, and converting the second epitaxial layer into a second sacrificial layer;
after a first sacrificial layer and a second sacrificial layer are formed, carrying out ion implantation on the first epitaxial layer; and after the first epitaxial layer is subjected to ion implantation, removing the first sacrificial layer, the second sacrificial layer and the isolation medium layer.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the epitaxial structure comprises a substrate, an active region and an isolation structure which are positioned in the substrate, and an initial epitaxial layer positioned on the substrate.
3. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the sacrificial structure: and forming an initial oxide layer on the substrate, wherein the sacrificial structure is formed on the initial oxide layer.
4. The method of forming a semiconductor structure of claim 2, wherein the material of the initial epitaxial layer comprises silicon germanium.
5. The method of forming a semiconductor structure of claim 3, wherein the method of forming the isolation dielectric layer comprises: forming an initial isolation dielectric layer on the initial oxide layer and the sacrificial structure; and etching back the initial isolation dielectric layer until the surface of the initial oxide layer is exposed, thereby forming the isolation dielectric layer.
6. The method of forming a semiconductor structure of claim 5, wherein the method of back-etching the initial isolation dielectric layer comprises dry etching.
7. The method of forming a semiconductor structure of claim 3, wherein after forming the isolation dielectric layer and before forming the first epitaxial layer, further comprising: etching the sacrificial structure and the initial oxide layers on two sides of the isolation medium layer until the surface of the substrate is exposed, thereby forming oxide layers between the substrate and the sacrificial structure and between the substrate and the isolation medium layer.
8. The method of forming a semiconductor structure of claim 7, wherein etching the initial oxide layer comprises wet etching.
9. The method of claim 1, wherein a material of the isolation dielectric layer comprises silicon nitride.
10. The method of forming a semiconductor structure of claim 1, wherein the material of the first epitaxial layer comprises silicon germanium; the material of the second epitaxial layer includes silicon germanium.
11. The method of forming a semiconductor structure of claim 1, wherein the process of forming the first epitaxial layer comprises a selective epitaxial growth process.
12. The method of forming a semiconductor structure of claim 1, wherein modifying the first and second epitaxial layers comprises oxidation or nitridation.
13. The method of forming a semiconductor structure of claim 12, wherein the oxidizing comprises: wet oxidation treatment process, chemical vapor deposition oxidation process, or in-situ water vapor generation process.
14. The method of forming a semiconductor structure of claim 12, wherein said nitridation process comprises a plasma nitridation process.
15. The method of claim 1, wherein the material of the first sacrificial layer comprises silicon oxide or silicon nitride, and the material of the second sacrificial layer comprises silicon oxide or silicon nitride.
16. The method of forming a semiconductor structure of claim 1, wherein the removing the first sacrificial layer, the second sacrificial layer, and the isolation dielectric layer comprises wet etching.
17. The method of claim 1, wherein an interlevel dielectric layer is formed over the first epitaxial layer and the sacrificial structure after removing the first sacrificial layer, the second sacrificial layer, and the isolation dielectric layer.
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| CN202111554731.7A CN114284136A (en) | 2021-12-17 | 2021-12-17 | Method for forming semiconductor structure |
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