CN110034068B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110034068B
CN110034068B CN201810026748.7A CN201810026748A CN110034068B CN 110034068 B CN110034068 B CN 110034068B CN 201810026748 A CN201810026748 A CN 201810026748A CN 110034068 B CN110034068 B CN 110034068B
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fin
forming
opening
fin portion
layer
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CN110034068A (en
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李程
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate is provided with a first fin part, a second fin part and a third fin part which are respectively positioned at two sides of the first fin part, the distance from the first fin part to the second fin part is different from the distance from the first fin part to the third fin part, and the top surface of the first fin part is provided with a mask layer; forming an initial isolation layer on the surface of the substrate, wherein the initial isolation layer covers the side wall of the first fin part and part of the side wall of the mask layer; removing the mask layer, and forming a first opening in the initial isolation layer; and forming a sacrificial film in the surface of the initial isolation layer and the first opening, wherein the sacrificial film is internally provided with a second opening positioned on the first opening, and the depth of the second opening is smaller than that of the first opening. The semiconductor device formed by the method has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
When the channel length is less than 100nm, in the conventional MOSFET, the source and drain regions interact with each other due to the semiconductor material of the semiconductor substrate surrounding the active region, the distance between the drain and the source is also shortened, and a short channel effect is generated, so that the control capability of the gate on the channel is deteriorated, the difficulty of pinching off (ping off) the channel by the gate voltage is increased, and the sub-threshold leakage (subthreshold leakage) phenomenon is more likely to occur.
A Fin Field effect transistor (FinFET) is a new type of metal oxide semiconductor Field effect transistor, and its structure is usually formed on a silicon-on-insulator (SOI) substrate, and includes narrow and isolated silicon strips (i.e., vertical channel structures, also called fins) with gate structures on both sides of the Fin. The FinFET structure makes the device smaller and has higher performance.
However, as the integration of semiconductor devices is further improved, the performance of finfet devices is expected to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a fin field effect transistor.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a first fin portion, a second fin portion and a third fin portion, the second fin portion and the third fin portion are respectively located on two sides of the first fin portion, the distance from the first fin portion to the second fin portion is different from the distance from the first fin portion to the third fin portion, and a mask layer is arranged on the top surface of the first fin portion; forming an initial isolation layer on the surface of the substrate, wherein the initial isolation layer covers the side wall of the first fin part and part of the side wall of the mask layer; removing the mask layer, and forming a first opening in the initial isolation layer; and forming a sacrificial film in the surface of the initial isolation layer and the first opening, wherein a second opening positioned on the first opening is formed in the sacrificial film, and the depth of the second opening is smaller than that of the first opening.
Optionally, the forming steps of the substrate, the first fin portion, the second fin portion, and the third fin portion include: providing an initial substrate, wherein the surface of the initial substrate is provided with the mask layer, and part of the initial top surface of the mask layer is exposed; and etching the initial substrate by taking the mask layer as a mask to form a substrate, a first fin portion positioned on the substrate, and a second fin portion and a third fin portion positioned on two sides of the first fin portion.
Optionally, the forming step of the initial isolation layer includes: forming an isolation material film on the surface of the substrate, the side wall of the first fin part, the side wall of the mask layer and the top surface of the substrate; flattening the isolation material film until the top surface of the mask layer is exposed; and after the isolation material film is flattened, removing part of the isolation material film to expose part of the side wall of the mask layer, and forming the initial isolation layer.
Optionally, the material of the isolation material film includes silicon oxide; the process of forming the film of barrier material comprises a fluid chemical vapor deposition process.
Optionally, the bottom of the first opening exposes a top surface of a portion of the initial isolation layer on one side of the first fin.
Optionally, the process for forming the sacrificial film includes: and (5) an atomic layer deposition process.
Optionally, a difference between the thickness of the sacrificial film and a half of a dimension of the first opening in the fin width direction is greater than 50 angstroms.
Optionally, after forming the sacrificial film, the forming method further includes: and removing part of the sacrificial film to form a sacrificial layer, wherein the sacrificial layer is internally provided with a third opening, and the depth of the third opening is smaller than that of the second opening.
Optionally, the process for forming the sacrificial layer includes: wet etch processes, Certas or SiCoNi processes.
Optionally, after forming the sacrificial layer, the forming method further includes: removing the sacrificial layer and part of the initial isolation layer to form an isolation layer, wherein the top surface of the isolation layer is lower than that of the first fin part and covers part of the side wall of the first fin part; after the isolation layer is formed, a grid electrode structure crossing the first fin portion is formed, and the grid electrode structure covers partial side wall and the top surface of the first fin portion; and forming source and drain doped regions in the first fin parts on two sides of the grid structure.
The present invention also provides a semiconductor structure comprising: the substrate is provided with a first fin portion, a second fin portion and a third fin portion, wherein the second fin portion and the third fin portion are respectively located on two sides of the first fin portion; an initial isolation layer on the substrate, the initial isolation layer covering a sidewall of the first fin portion; a first opening in the initial isolation layer; and the sacrificial film is positioned in the initial isolation layer and the first opening, and a second opening is arranged in the sacrificial film, and the depth of the second opening is smaller than that of the first opening.
Optionally, the material of the initial isolation layer comprises: silicon oxide.
Optionally, the bottom of the first opening exposes a top surface of a portion of the initial isolation layer on one side of the first fin.
Optionally, the material of the sacrificial film includes: silicon oxide.
Optionally, a difference between a thickness of the sacrificial film and a half of a dimension of the first opening in the fin width direction is greater than 50 angstroms.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming a semiconductor structure provided by the technical scheme of the present invention, since the distance from the first fin portion to the second fin portion is different from the distance from the first fin portion to the third fin portion, when an initial isolation layer is subsequently formed, the stresses on both sides of the first fin portion are different, and thus the first fin portion and the mask layer are easily dislocated, the initial isolation layer on one side of the first fin portion is easily exposed at the bottom of the first opening formed by subsequently removing the mask layer, and the initial isolation layer is not exposed on the other side of the first fin portion, that is: after the first opening is formed, the initial isolation layer covered by the sidewalls of the first fin portion easily has a thickness difference. And a sacrificial film is formed in the first opening subsequently, a second opening is formed in the sacrificial film, and the depth of the second opening is smaller than that of the first opening, so that the sacrificial film can weaken the thickness difference of two sides of the first fin part, and the height difference of two sides of the exposed first fin part is smaller after the isolation layer formed by part of the initial isolation layer is removed subsequently, thereby being beneficial to improving the performance of the semiconductor device.
Further, after the sacrificial film is formed, the forming method further includes: and removing part of the sacrificial film to form a sacrificial layer, wherein the sacrificial layer is internally provided with a third opening, and the depth of the third opening is greater than that of the second opening, so that the thickness difference of the two sides of the first fin part exposed by the isolation layer can be further weakened later.
Drawings
Fig. 1-3 are schematic structural diagrams illustrating steps in a method of forming a finfet transistor;
fig. 4 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, finfet performance is poor.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a finfet transistor.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a first fin portion 101, and a second fin portion 102 and a third fin portion 103 located at two sides of the first fin portion 101, a distance from the first fin portion 101 to the second fin portion 102 is different from a distance from the first fin portion 101 to the third fin portion 103, and a mask layer 104 is disposed on a top of the first fin portion 101; an initial isolation layer 105 is formed on the surface of the substrate 100, and the initial isolation layer 105 covers the sidewalls of the first fin 101 and a portion of the sidewalls of the mask layer 104.
Referring to fig. 2, the mask layer 102 is removed, and an opening 106 is formed in the initial isolation layer 103, where the opening 106 exposes the initial isolation layer 103 on one side of the first fin 101.
Referring to fig. 3, a portion of the initial isolation layer 103 is removed to form an isolation layer 107, where a top surface of the isolation layer 107 is lower than a top surface of the first fin 101 and covers a portion of the sidewall of the first fin 101.
In the above method, the step of forming the initial isolation layer 105 includes: forming an isolation material layer on the surface of the substrate 100 and on the sidewall and the top surface of the first fin portion 101; planarizing the isolation material layer until the top surface of the mask layer 104 is exposed; after planarizing the spacer material layer, a portion of the spacer material layer is removed to form the initial spacer layer 105. The material of the isolation material layer comprises silicon oxide, and the forming process of the isolation material layer comprises a fluid chemical vapor deposition process. The fluid chemical vapor deposition process is a high temperature process.
Because the distance from the first fin portion 101 to the second fin portion 102 is different from the distance from the first fin portion 101 to the third fin portion 103, in the process of forming the isolation material layer, the stress on two sides of the first fin portion 101 is different, and then the first fin portion 101 is prone to incline to the side with the larger stress, that is: if the first fin 101 and the mask layer 104 are dislocated, the mask layer 104 is subsequently removed, the formed opening 106 exposes the initial isolation layer 105 on one side of the first fin 101, and the other side of the top of the first fin 101 does not expose the top surface of the initial isolation layer 105, that is: after the opening 106 is formed, the initial isolation layer 105 on both sides of the first fin 101 has a height difference, and the isolation layer 107 formed by removing a portion of the initial isolation layer 105 is exposed at different heights on both sides of the first fin 101, which is not favorable for improving the performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: removing the mask layer, and forming a first opening in the initial isolation layer, wherein the bottom of the first opening exposes a part of the top surface of the initial isolation layer on one side of the first fin portion; and forming a sacrificial film in the surface of the initial isolation layer and the first opening, wherein a second opening is formed in the sacrificial film, and the depth of the second opening is smaller than that of one opening. The semiconductor device formed by the method has better performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, the surface of the substrate 200 has a first fin portion 201, and a second fin portion 202 and a third fin portion 203 located at two sides of the first fin portion 201, a distance from the first fin portion 201 to the second fin portion 202 is different from a distance from the first fin portion 201 to the third fin portion 203, and a mask layer 204 is disposed on a top of the first fin portion 201; an isolation material film 205 is formed on the surface of the substrate 200, the sidewalls of the first fin 201, and the sidewalls and top surface of the mask layer 204.
In this embodiment, the forming steps of the substrate 200, the first fin 201, the second fin 202, and the third fin 203 include: providing an initial substrate, wherein the surface of the initial substrate is provided with a mask layer 204, and the mask layer 204 exposes part of the top surface of the initial substrate; and etching the initial substrate by taking the mask layer 204 as a mask to form the substrate 200, a first fin portion 201 located on the substrate 200, and a second fin portion 202 and a third fin portion 203 located on two sides of the first fin portion 201.
In this embodiment, the initial substrate is made of silicon, and correspondingly, the base 200, the first fin 201, the second fin 202, and the third fin 203 are made of silicon.
In other embodiments, the initial substrate may also be a semiconductor substrate such as a germanium substrate, a silicon on insulator or a germanium on insulator, and accordingly, the materials of the base, the first fin portion, the second fin portion, and the third fin portion include: germanium, silicon on insulator, or germanium on insulator.
The material of the mask layer 204 includes: silicon nitride or titanium nitride.
The mask layer 204 is used for forming masks of the substrate 200, the first fin portion 201, the second fin portion 202 and the third fin portion 203, so that the mask layer 204 is the same as the first fin portion 201 in width direction along the first fin portion 201, and the mask layer 204 covers the top surface of the first fin portion 201. The width direction of the first fin portion 201 specifically refers to: perpendicular to the extending direction (X direction) of the first fin 201.
With the mask layer 204 as a mask, the process for etching the initial substrate includes: one or two of the dry etching process and the wet etching process are combined.
The material of the spacer material film 205 includes: silicon oxide, the process of forming the isolation material film 205 includes: a fluid chemical vapor deposition process, the forming step of the fluid chemical vapor deposition process comprising: forming precursors on the surface of the substrate 200, the side walls and the top surface of the first fin 201, the side walls and the top surface of the second fin 202, and the side walls and the top surface of the third fin 203; the precursor is subjected to curing treatment to cure the precursor, thereby forming the spacer material film 203.
The curing process is a high-temperature process, which is beneficial to completely converting the precursor into silicon oxide, and the silicon oxide has a better isolation effect.
However, the distance between the first fin portion 201 and the second fin portion 202 is different from the distance between the first fin portion 201 and the third fin portion 203, so that the high temperature processes on both sides of the first fin portion 201 have different influences, and the mask layer 204 and the first fin portion 201 are dislocated along the width direction (X direction) of the first fin portion 201. Namely: the mask layer 204 is located on a portion of the top surface of the first fin 201 and on the isolation material film 205 on one side of the top of the first fin 201.
Referring to fig. 5, the isolation material film 205 is planarized until the top surface of the mask layer 204 is exposed.
The process of planarizing the isolation material film 205 includes: and (5) carrying out a chemical mechanical polishing process.
The isolation material film 205 is planarized to expose the top surface of the mask layer 204, which facilitates the subsequent removal of the mask layer 204.
Before removing the mask layer 204, a portion of the isolation material film 204 is removed to expose a portion of the sidewall of the mask layer 204, please refer to fig. 6.
Referring to fig. 6, a portion of the isolation material film 205 (see fig. 5) is removed to expose a portion of the sidewall of the mask layer 204, thereby forming an initial isolation layer 206.
The significance of removing part of the isolation material film 206 to expose part of the sidewall of the mask layer 204, rather than completely exposing the sidewall of the mask layer 204, is that: the initial isolation layer 206 on the sidewall of the mask layer 204 can prevent the mask layer 204 from toppling over, and the toppling over phenomenon is unpredictable, so that the problem that the subsequent initial isolation layer 206 is difficult to remove due to toppling over of the mask layer 204 can be effectively solved, the controllability of a process can be improved, and the performance of a semiconductor device can be improved.
Referring to fig. 7, the mask layer 204 (see fig. 6) is removed, and a first opening 207 is formed in the initial isolation layer 206, wherein the first opening 207 exposes the top of the initial isolation layer 206 on one side of the first fin 201.
The process for removing the mask layer 204 includes: one or two of the dry etching process and the wet etching process are combined.
The first opening 207 is used for subsequently accommodating a sacrificial film.
Referring to fig. 8, a sacrificial film 208 is formed on the surfaces of the first opening 207 (see fig. 7) and the initial isolation layer 206, the sacrificial film 208 has a second opening 209 therein, and the depth of the second opening 209 is smaller than the depth of the first opening 207 (see fig. 7).
The material of the sacrificial film 208 includes: silicon oxide, the forming process of the sacrificial film 208 includes: and (5) an atomic layer deposition process.
The sacrificial film 208 adopts an atomic layer deposition process, which has the advantages that: the thickness of the sacrificial film 208 is controllable, the variability caused by the increase of the process can be reduced, and the stability of the whole process can be maintained.
Moreover, the sacrificial film 208 formed by the atomic layer deposition process has fluidity, so that the filling capacity of the first opening 207 is strong, the depth of the second opening 209 in the sacrificial film 208 is smaller than that of the first opening 207, the sacrificial film 208 is used for balancing the thickness difference of the two sides of the first fin portion 201, the height difference of the two sides of the first fin portion 201 exposed by the isolation layer formed by subsequently removing the sacrificial film 208 and part of the initial isolation layer 206 is small, and the performance of the semiconductor device is improved.
The difference between the thickness of the sacrificial film 208 and the dimension of the first opening 207 along the width direction of the first fin 201 is greater than 50 angstroms.
Referring to fig. 9, a portion of the sacrificial film 208 is removed to form a sacrificial layer 210, wherein the sacrificial layer 210 has a third opening 211 therein, and a depth of the third opening 211 is smaller than a depth of the second opening 209 (see fig. 8).
The process of removing a portion of the sacrificial film 208 includes: wet etch processes, Certas or SiCoNi processes.
In this embodiment, the process of removing a portion of the sacrificial film 208 is a wet etching process.
In this embodiment, when the wet etching process is used to remove a portion of the sacrificial film 208, the etchant not only has an etching rate in a direction perpendicular to the surface of the substrate 200, but also has an etching rate in a direction parallel to the surface of the substrate 200, which is beneficial to further reduce the height difference between the two sides of the first fin 201, so that the subsequent removal of a portion of the sacrificial layer 210 and the initial isolation layer 206 results in a smaller difference in height of the first fin 201 exposed by the formed isolation layer, which is beneficial to improving the performance of the semiconductor device.
In other embodiments, a portion of the sacrificial film is not removed, and then a portion of the sacrificial film and the initial isolation layer are directly removed to form an isolation layer, where a top surface of the isolation layer is lower than a top surface of the first fin and covers a portion of the sidewall of the first fin.
Referring to fig. 10 and 11, fig. 11 is a cross-sectional view taken along line a-a1 of fig. 10, and fig. 10 is a cross-sectional view taken along line B-B1 of fig. 11, in which the sacrificial layer 210 and a portion of the initial isolation layer 206 are removed to form an isolation layer 212, a top surface of the isolation layer 212 is lower than a top surface of the first fin 201 and covers a portion of sidewalls of the first fin 201.
Fig. 10 corresponds to the cross-sectional direction of fig. 9.
The process of removing the sacrificial layer 210 and a portion of the initial isolation layer 206 includes: one or two of the dry etching process and the wet etching process are combined.
In the process of forming the isolation layer 212, the difference of the materials on the two sides of the first fin portion 201 is small, so that the difference of the heights of the formed isolation layer 212 exposed on the two sides of the first fin portion 201 is small, and the performance of the semiconductor device is improved.
After forming the isolation layer 212, the forming method includes: forming a gate structure crossing the first fin 201, wherein the gate structure covers part of the side wall and the top surface of the first fin 201; and forming source and drain doped regions in the first fin parts 201 on two sides of the grid structure.
The gate structure includes: a gate dielectric layer on the sidewalls and top surface of the first fin 201 and a gate layer on the top surface of the gate dielectric layer.
The gate dielectric layer is made of silicon oxide, and the forming process of the gate dielectric layer comprises the following steps: an in-situ steam generation process or a chemical oxidation process.
The material of the gate layer comprises: silicon.
The forming step of the source drain doped region comprises the following steps: forming source and drain openings in the first fin portions 201 on two sides of the gate structure; forming an epitaxial layer in the source drain opening; doping ions into the epitaxial layer to form the source-drain doped region.
The forming process of the source and drain openings comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The material of the epitaxial layer and the conductivity type of the dopant ions are related to the type of transistor. Specifically, when the type of the transistor is an NMOS transistor, the material of the epitaxial layer includes: silicon carbide or silicon, the doping ions are N-type ions, such as: phosphorus ions or arsenic ions; when the transistor is a PMOS transistor, the material of the epitaxial layer includes silicon germanium or silicon, and the dopant ions are P-type ions, such as: boron ions.
Accordingly, the present invention also provides a semiconductor structure, please refer to fig. 8, which includes:
the semiconductor device comprises a substrate 200, wherein the substrate 200 is provided with a first fin portion 201, a second fin portion 202 and a third fin portion 203, the second fin portion 202 and the third fin portion 203 are located on two sides of the first fin portion 201, and the distance from the first fin portion 201 to the second fin portion 202 is different from the distance from the first fin portion 201 to the third fin portion 203;
an initial isolation layer 206 on the substrate 200, the initial isolation layer 206 covering sidewalls of the first fin 201;
a first opening 207 (see fig. 7) in the initial isolation layer 206, wherein a portion of the initial isolation layer 206 on one side of the first fin 201 is exposed at the bottom of the first opening 207;
a sacrificial film 208 located within the initial isolation layer 206 and the first opening 207, the sacrificial film 208 having a second opening 209 therein, the second opening 209 having a depth less than the depth of the first opening 207.
The materials of the initial isolation layer 206 include: silicon oxide.
The material of the sacrificial film 208 includes: silicon oxide.
The difference between the thickness of the sacrificial film 208 and half of the dimension of the first opening 207 in the width direction of the fin 201 is greater than 50 angstroms.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first fin portion, a second fin portion and a third fin portion, the second fin portion and the third fin portion are respectively located on two sides of the first fin portion, the distance from the first fin portion to the second fin portion is different from the distance from the first fin portion to the third fin portion, and a mask layer is arranged on the top surface of the first fin portion;
forming an initial isolation layer on the surface of the substrate, wherein the initial isolation layer covers the side wall of the first fin portion and a part of the side wall of the mask layer;
removing the mask layer, and forming a first opening in the initial isolation layer;
and forming a sacrificial film in the surface of the initial isolation layer and the first opening, wherein a second opening positioned on the first opening is formed in the sacrificial film, and the depth of the second opening is smaller than that of the first opening.
2. The method of forming a semiconductor structure of claim 1, wherein the forming the substrate, the first fin, the second fin, and the third fin comprises: providing an initial substrate, wherein the surface of the initial substrate is provided with the mask layer, and part of the initial top surface of the mask layer is exposed; and etching the initial substrate by taking the mask layer as a mask to form a substrate, a first fin portion positioned on the substrate, and a second fin portion and a third fin portion positioned on two sides of the first fin portion.
3. The method of forming a semiconductor structure of claim 1, wherein the step of forming the initial isolation layer comprises: forming an isolation material film on the surface of the substrate, the side wall of the first fin part, the side wall of the mask layer and the top surface of the substrate; flattening the isolation material film until the top surface of the mask layer is exposed; and after the isolation material film is flattened, removing part of the isolation material film to expose part of the side wall of the mask layer, and forming the initial isolation layer.
4. The method of forming a semiconductor structure according to claim 3, wherein a material of the isolation material film includes silicon oxide; the process of forming the film of barrier material comprises a fluid chemical vapor deposition process.
5. The method of claim 4, wherein a bottom of the first opening exposes a top surface of a portion of the initial isolation layer on one side of the first fin.
6. The method of forming a semiconductor structure of claim 1, wherein a material of the sacrificial film comprises: silicon oxide.
7. The method of forming a semiconductor structure according to claim 6, wherein the process of forming the sacrificial film comprises: and (5) an atomic layer deposition process.
8. The method of claim 1, wherein a difference between a thickness of the sacrificial film and a half of a dimension of the first opening in a fin width direction is greater than 50 angstroms.
9. The method of forming a semiconductor structure of claim 1, wherein after forming the sacrificial film, the method of forming further comprises: and removing part of the sacrificial film to form a sacrificial layer, wherein the sacrificial layer is internally provided with a third opening, and the depth of the third opening is smaller than that of the second opening.
10. The method of forming a semiconductor structure of claim 9, wherein the process of forming the sacrificial layer comprises: wet etch processes, Certas or SiCoNi processes.
11. The method of forming a semiconductor structure of claim 9, wherein after forming the sacrificial layer, the method of forming further comprises: removing the sacrificial layer and part of the initial isolation layer to form an isolation layer, wherein the top surface of the isolation layer is lower than that of the first fin part and covers part of the side wall of the first fin part; after the isolation layer is formed, a grid electrode structure crossing the first fin portion is formed, and the grid electrode structure covers partial side wall and the top surface of the first fin portion; and forming source and drain doped regions in the first fin parts on two sides of the grid structure.
12. A semiconductor structure, comprising:
the substrate is provided with a first fin portion, a second fin portion and a third fin portion, wherein the second fin portion and the third fin portion are respectively located on two sides of the first fin portion;
an initial isolation layer on the substrate, the initial isolation layer covering a sidewall of the first fin portion;
a first opening in the initial isolation layer; the first opening is positioned at the top of the first fin part;
and the sacrificial film is positioned in the initial isolation layer and the first opening, a second opening positioned on the first opening is arranged in the sacrificial film, and the depth of the second opening is smaller than that of the first opening.
13. The semiconductor structure of claim 12, wherein the material of the initial isolation layer comprises: silicon oxide.
14. The semiconductor structure of claim 13, wherein a bottom of the first opening exposes a top surface of a portion of the initial isolation layer on one side of the first fin.
15. The semiconductor structure of claim 12, wherein a material of the sacrificial film comprises: silicon oxide.
16. The semiconductor structure of claim 12, wherein a difference between a thickness of the sacrificial film and a half of a dimension of the first opening in a fin width direction is greater than 50 angstroms.
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US8895446B2 (en) * 2013-02-18 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Fin deformation modulation
US9087796B2 (en) * 2013-02-26 2015-07-21 International Business Machines Corporation Semiconductor fabrication method using stop layer
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