CN114277409B - Electroplating method of semiconductor device - Google Patents
Electroplating method of semiconductor device Download PDFInfo
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- CN114277409B CN114277409B CN202111405176.1A CN202111405176A CN114277409B CN 114277409 B CN114277409 B CN 114277409B CN 202111405176 A CN202111405176 A CN 202111405176A CN 114277409 B CN114277409 B CN 114277409B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application discloses a method for electroplating a semiconductor device, which comprises the steps of arranging a resistance detection circuit on the basis of a pre-process layer, keeping the current intensity unchanged in the electroplating process, monitoring the resistance change of the detection circuit in real time in the electroplating process, recording the first time from the beginning of electroplating to the resistance change, and obtaining the electroplating rate according to the first height and the first time. And further, the total electroplating time is calculated according to the target thickness of the electroplated metal, so that the electroplated metal with the target thickness can be obtained in the total electroplating time. The resistance signal can be further transmitted by adopting the wireless transmission module, so that the application can not only reduce menu setting and save manufacturing cost, but also be more convenient and suitable for various different scenes.
Description
Technical Field
The application relates to the field of electroplating, in particular to an electroplating method of a semiconductor device.
Background
Electroplating (plating) is a common practice for producing metals, and has the advantage of faster electroplating efficiency than PVD, is suitable for large-area metal laying and thicker processes, and is widely used in the production of partial metal layers in semiconductors, such as the formation of air bridge.
The electroplating process comprises the following steps: sputtering titanium, titanium tungsten and other metals on the silicon wafer as an adhesion layer, sputtering a very thin layer of gold as an electroplated conductive layer, and forming a seed layer by the adhesion layer and the conductive layer; then coating photoresist on the seed layer, and developing a pattern required by electroplating by photoetching; after cleaning, electroplating metal; and removing the residual photoresist, and finally etching the seed layer outside the pattern to obtain the electroplated metal layer.
The parameter setting of general electroplating is related to the area ratio of metal formed on the wafer, namely the same target thickness, if the total electroplating time is unchanged, the current intensity is in direct proportion to the light transmittance of the photoetching plate, so that different products and different layers need to be set with different menus according to different light transmittance. Therefore, in the prior art, the current intensity is generally adjusted according to a menu, and then the thickness of the electroplated metal is controlled according to the preset time on the menu. In actual production, the conditions that the menu is modified according to the process but not in time are easy to exist, the current intensity is adjusted, and the like, so that the target thickness of the finally electroplated metal cannot meet the requirement, and the thickness of the electroplated metal cannot be found to meet the requirement until the electroplating is finished or the product production is finished, thereby bringing serious economic loss to manufacturers.
Disclosure of Invention
The application aims to overcome the defects in the prior art and provides an electroplating method of a semiconductor device.
In order to achieve the above object, the technical scheme of the present application is as follows:
a plating method comprising the steps of:
1) Providing a wafer structure to be electroplated, wherein the wafer structure to be electroplated comprises a preset electroplating area and a pre-process layer with a first height formed around the preset electroplating area, a seed layer is arranged on the preset electroplating area, and the top of the side wall of the pre-process layer around the preset electroplating area is free of the seed layer;
2) In the electroplating process, electroplating is carried out with a preset constant current value, a detection circuit for monitoring resistance is arranged above the pre-process layer around the preset electroplating area, the first time from the start of electroplating to the change of the resistance of the detection circuit is obtained, and the ratio of the first height to the first time is calculated to obtain the electroplating rate;
3) Obtaining the target thickness of the electroplated metal, and calculating the ratio of the target thickness of the electroplated metal to the electroplating rate to obtain the total electroplating time;
4) And finishing electroplating within the total electroplating time at the preset constant current value.
In some embodiments, the acquiring the first time from the start of electroplating to the change of the resistance of the detection circuit in step 2 specifically includes:
acquiring a first resistor of the detection circuit before electroplating;
a first time is monitored during the electroplating process when the resistance of the detection circuit changes from a first resistance to a second resistance.
In some embodiments, the second resistance is 20% -80% of the first resistance.
In some embodiments, a seed layer is disposed on a surface of the pre-process layer, and a contact point between the detection circuit and the seed layer of the pre-process layer is disposed in a non-photoresist coverage area.
In some embodiments, an angle formed between a sidewall of the pre-process layer around the pre-plating region and a surface of the pre-plating region is less than or equal to 90 °.
In some embodiments, the pre-process layer includes a first photoresist and a second photoresist on two opposite sides around the preset electroplating area a, the first photoresist and the second photoresist are disconnected, and the contact points of the detection circuit and the pre-process layer are respectively arranged on the surfaces of the first photoresist and the second photoresist.
In some embodiments, the pre-plating region and the pre-process layer are disposed in a non-device working area on the wafer structure to be plated.
In some embodiments, further comprising: and wirelessly transmitting the resistance signal obtained by the detection circuit test through a wireless transmission module.
In some embodiments, the wireless transmission module is disposed in a non-device working area on the wafer structure to be electroplated, and is fixed on the wafer structure to be electroplated through conductive adhesive and connected with the detection circuit.
In some embodiments, the wireless transmission module comprises a bluetooth module.
Compared with the prior art, the application has the following beneficial effects:
(1) The application adopts the detection circuit to measure the change of the resistance of the seed layer of the pre-process layer around the pre-process layer before and during the electroplating process, can realize the detection of the electroplating rate through the first height of the pre-process layer and the first time of the resistance change, and can automatically calculate the time required for electroplating to the target thickness.
(2) The application is based on the prior process layer, fixes the current intensity, lays out the plating layer resistance detection circuit, achieves the detection of the plating rate, and calculates the total plating time according to the plating rate and the target thickness, thereby avoiding the process of adjusting the current intensity by setting different menus, reducing the monitoring and menu setting and saving the manufacturing cost.
(3) The application can also adopt the line design of the Bluetooth patch, realize the wireless transmission of the resistance signal by the wireless connection of the Bluetooth module and the communication module of the detection circuit, is suitable for the scenes such as rotary electroplating, and is more intelligent and convenient.
Drawings
FIG. 1 is a top view of a wafer structure according to a first embodiment of the present application;
FIG. 2 is a schematic diagram of a pre-plating detection circuit for monitoring a first resistor according to a first embodiment of the present application;
FIG. 3 is a schematic diagram showing the monitoring of the second resistance by the in-electroplating detection circuit according to the first embodiment of the application;
FIG. 4 is a schematic diagram of a pre-plating detection circuit for monitoring a first resistor according to a second embodiment of the present application;
FIG. 5 is a schematic diagram of a detecting circuit monitoring a second resistance in electroplating according to a second embodiment of the application;
fig. 6 is a schematic diagram of a bluetooth module patch according to a third embodiment of the present application;
fig. 7 is a top view of a bluetooth module patch on a wafer according to a third embodiment of the present application.
Detailed Description
The application is further explained below with reference to the drawings and specific embodiments. The drawings of the present application are merely schematic to facilitate understanding of the present application, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
Example 1
The electroplating method of the present application is described in detail below with reference to FIGS. 1-3.
S1, providing a wafer structure to be electroplated, wherein the wafer structure to be electroplated comprises a preset electroplating area A and a pre-process layer 1 with a first height formed around the preset electroplating area A, and seed layers 2 are arranged on the surfaces of the preset electroplating area A and the pre-process layer 1. The wafer structure to be electroplated has completed part of the device manufacturing process, and is formed with a pre-process layer 1 and a preset electroplating area A with a first height h from the pre-process layer 1, wherein the thickness of the electroplated metal on the preset electroplating area A gradually increases in the electroplating process due to the fact that the height of the preset electroplating area A is lower than that of the pre-process layer 1, at least is level with the surface of the pre-process layer 1, and reaches the target thickness according to the total electroplating time. The pre-process layer 1 is an insulating layer or a semiconductor layer formed by a pre-process and having a certain height with respect to the predetermined electroplating area A for detection.
In a specific embodiment, the wafer structure to be electroplated is sputtered with the seed layer 2, coated with photoresist, exposed and developed, so that the seed layer 2 is disposed on both the pre-process layer 1 and the preset electroplating area a, and an included angle formed between the sidewall of the pre-process layer 1 and the surface of the preset electroplating area a is less than or equal to 90 °. In this case, the seed layer 2 is not sputtered on the sidewall of the pre-process layer 1, so as to avoid the conduction of the detection circuit, and it is noted that the top of the sidewall of the pre-process layer 1 around the preset electroplating area a has no seed layer 2, so that even if the seed layer 2 is sputtered on any position below the top of the sidewall of the pre-process layer 1 around the preset electroplating area a, the monitoring precision of the detection circuit is not affected. The preset electroplating area A is not covered with photoresist, and a resistance detection circuit is constructed above the non-photoresist covered area of the seed layer 2 of the prior art layer 1, wherein the specific detection circuit can adopt a two-probe or four-probe resistance detection mode. In a preferred embodiment, the contact points between the detection circuit and the seed layer 2 of the pre-process layer 1 are respectively disposed at two opposite sides around the preset electroplating area a, but not limited thereto, the seed layer 2 of the pre-process layer 1 may be disposed at any two positions of the non-photoresist covering area. Referring to fig. 1, the preset plating area and the pre-process layer are disposed in a non-device working area B on the wafer structure to be plated, for example, a passive area may be disposed at an edge of the device working area, which does not affect the manufacture of devices in the active area.
S2, acquiring a first resistor R1 of the detection circuit. Referring to fig. 2, the first resistor R1 may be a first resistor R1 obtained by testing a detection circuit before electroplating, or a first resistor R1 obtained by testing a detection circuit when the plating metal above the preset plating area a is not level with the seed layer 2 of the pre-process layer 1 and the plating metal on the preset plating area a is not connected with the plating metal on the pre-process layer 1, and the first resistor R1 is a high resistance.
And S3, keeping the current intensity of electroplating unchanged in the electroplating process, and monitoring the resistance change of the detection circuit until the resistance becomes a second resistance. Referring to fig. 3, in the electroplating process, when the height of the electroplated metal 3 formed in the preset electroplating area a reaches the first height h, the resistance becomes the second resistance R2 when the electroplated metal 3 formed in the preset electroplating area a is connected with the seed layer 2 above the pre-process layer 1, at this time, the surface of the electroplated metal 3 is flush with the surface of the seed layer 2 of the pre-process layer 1, and the electroplated metal on the preset electroplating area a is connected with the electroplated metal on the pre-process layer 1, so that the detection circuit is turned on, the resistance obtained by the detection circuit test is reduced to the second resistance R2, and the thickness of the electroplated metal 3 is equal to the first height h. Since the seed layer 2 is not formed on the top of the sidewall of the pre-process layer 1 around the preset plating area a, it is ensured that the thickness of the plated metal on the preset plating area a is equal to the first height h when the first resistance monitored by the detection circuit is changed to the second resistance. The second resistor R2 is 20% -80% of the first resistor R1.
S4, acquiring a first time t from the start of electroplating to the change of the resistor into a second resistor, wherein the first time t can be obtained by adopting a timer and the like. Obtaining an electroplating rate v according to the first height h and the first time t, and calculating the electroplating rate v by adopting the following formula:
v＝h/t。
that is, the plating rate v is a ratio of the first height h to the first time t.
S5, obtaining a target thickness H of the electroplated metal 3, and obtaining an electroplating total time T according to the target thickness H of the electroplated metal 3 and the electroplating rate v, wherein the calculation formula of the electroplating total time T is as follows: t=h/v.
That is, the total plating time T is the ratio of the target thickness H of the plated metal 3 to the plating rate v.
S6, electroplating is carried out within the total electroplating time T at a preset constant current value, so that the final thickness of the electroplated metal 3 reaches the target thickness H.
Because the current intensity is kept unchanged in the electroplating process, the electroplating rate is also fixed, and the embodiment of the application is based on the prior process layer, and the monitoring of the electroplating rate is achieved by arranging the resistance detection circuit, so that the total time required for electroplating to the target thickness can be automatically calculated, the parameter setting mode in the electroplating process is changed, the monitoring and menu setting are reduced, the economic loss caused by modification errors among different menus is effectively avoided, and the manufacturing cost can be effectively saved.
Example two
The second embodiment differs from the first embodiment in that: referring to fig. 4 and 5, the pre-process layer 1 is a photoresist coated on the wafer before the electroplating process, a position of a preset electroplating area a is defined by the photoresist, a seed layer 2 is not arranged on the photoresist, the pre-process layer 1 comprises a first photoresist and a second photoresist on two opposite sides around the preset electroplating area a, the first photoresist and the second photoresist are disconnected, electroplating metal is also deposited on the photoresist during the electroplating process, the first photoresist and the second photoresist are disconnected, the electroplating metal on the first photoresist and the second photoresist is mutually insulated before the thickness of the electroplating metal of the preset electroplating area a reaches a first height h, and contact points of the detection circuit and the seed layer 2 of the pre-process layer 1 are respectively arranged on the surfaces of the first photoresist and the second photoresist on two opposite sides around the preset electroplating area a, at the moment, before the thickness of the electroplating metal of the preset electroplating area a reaches the first height h, the detection circuit monitors that the resistance of the detection circuit is the disconnection, the resistance of the detection circuit is the first resistance R1, and the resistance of the detection circuit is infinite. When the thickness of the electroplated metal reaches the target thickness, the electroplated metal on the pre-process layer 1 is connected with the electroplated metal of the preset electroplating area A, the detection circuit is conducted, the resistance monitored by the detection circuit is changed into a second resistance R2, the second resistance R2 shows a resistance value, and the rest parts are the same as those of the first embodiment.
Example III
The third embodiment differs from the first embodiment or the second embodiment in that: in the third embodiment, a wireless transmission module is added on the basis of the detection circuit in the first embodiment or the second embodiment, and the wireless transmission module is arranged in a non-device working area of the wafer structure to be electroplated, for example, a bluetooth module, and in other alternative embodiments, a wifi module and the like can also be adopted. Referring to fig. 6 and 7, the bluetooth module 4 is fixed to the edge C of the wafer structure to be plated in a manner of a patch of conductive adhesive 5. The control module in the detection circuit is connected with the Bluetooth module 4 to realize wireless transmission of the resistance signal monitored in the detection circuit with the outside through the Bluetooth module 4, so as to meet the requirements of rotary electroplating and other scenes and avoid the influence on the test and transmission of the resistance signal of the detection circuit under the states of wafer rotation or movement and the like.
It should be noted that the electroplating method of the first embodiment, the second embodiment and the third embodiment is applicable to any semiconductor manufacturing method using an electroplating process, including, but not limited to, HBT devices and HEMT devices.
The foregoing embodiments are only for further illustrating a method for electroplating a semiconductor device according to the present application, but the present application is not limited to the embodiments, and any simple modification, equivalent variation and modification made to the foregoing embodiments according to the technical substance of the present application falls within the scope of the technical solution of the present application.
Claims (6)
1. A method of electroplating a semiconductor device, comprising the steps of:
1) Providing a wafer structure to be electroplated, wherein the wafer structure to be electroplated comprises a preset electroplating area and a pre-process layer with a first height, wherein the pre-process layer is an insulating layer or a semiconductor layer and is formed around the preset electroplating area, the surface of the pre-process layer is provided with a seed layer, the preset electroplating area is provided with a seed layer, and the top of the side wall of the pre-process layer around the preset electroplating area is free of the seed layer;
2) In the electroplating process, electroplating is carried out with a preset constant current value, a detection circuit for monitoring resistance is arranged above the pre-process layer around the preset electroplating area, the contact point between the detection circuit and the seed layer of the pre-process layer is arranged in a non-photoresist coverage area, the first time from the beginning of electroplating to the change of the resistance of the detection circuit is obtained, and the ratio of the first height to the first time is calculated to obtain the electroplating rate; the step 2 of obtaining the first time from the start of electroplating to the change of the resistance of the detection circuit specifically includes: acquiring a first resistor of the detection circuit before electroplating; monitoring a first time when the resistance of the detection circuit changes from a first resistance to a second resistance in an electroplating process, wherein the second resistance is 20% -80% of the first resistance;
3) Obtaining the target thickness of the electroplated metal, and calculating the ratio of the target thickness of the electroplated metal to the electroplating rate to obtain the total electroplating time;
4) And finishing electroplating within the total electroplating time at the preset constant current value.
2. The plating method according to claim 1, wherein an angle formed between a sidewall of the pre-process layer around the pre-plating area and a surface of the pre-plating area is less than or equal to 90 °.
3. The plating method of claim 1, wherein said pre-plating area and said pre-process layer are disposed in a non-device working area on said wafer structure to be plated.
4. The plating method as recited in claim 1, further comprising: and wirelessly transmitting the resistance signal obtained by the detection circuit test through a wireless transmission module.
5. The plating method according to claim 4, wherein the wireless transmission module is disposed in a non-device working area on the wafer structure to be plated, and is fixed on the wafer structure to be plated by conductive adhesive and connected to the detection circuit.
6. The plating method according to claim 4, wherein the wireless transmission module comprises a bluetooth module.
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| US9312140B2 (en) * | 2014-05-19 | 2016-04-12 | International Business Machines Corporation | Semiconductor structures having low resistance paths throughout a wafer |
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| JP2014103255A (en) * | 2012-11-20 | 2014-06-05 | Micronics Japan Co Ltd | Multilayer wiring board and method for manufacturing the same |
| CN103165571A (en) * | 2013-02-28 | 2013-06-19 | 江阴长电先进封装有限公司 | Novel silicon substrate low resistance inductance structure and wafer level encapsulating method thereof |
| CN104576428A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Film thickness detection method |
| US10529622B1 (en) * | 2018-07-10 | 2020-01-07 | International Business Machines Corporation | Void-free metallic interconnect structures with self-formed diffusion barrier layers |
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