CN114277409A - Electroplating method of semiconductor device - Google Patents
Electroplating method of semiconductor device Download PDFInfo
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- CN114277409A CN114277409A CN202111405176.1A CN202111405176A CN114277409A CN 114277409 A CN114277409 A CN 114277409A CN 202111405176 A CN202111405176 A CN 202111405176A CN 114277409 A CN114277409 A CN 114277409A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses an electroplating method of a semiconductor device, which is characterized in that a resistance detection circuit is arranged on the basis of a front process layer, a first height is formed between the front process layer and a preset electroplating area, the current intensity is kept unchanged in the electroplating process, the resistance change of the detection circuit in the electroplating process is monitored in real time, the first time from the beginning of electroplating to the resistance change is recorded, and the electroplating rate is obtained according to the first height and the first time. And then the total electroplating time is calculated according to the target thickness of the electroplated metal, so that the electroplated metal with the target thickness can be electroplated in the total electroplating time. Further, the resistance signal can be wirelessly transmitted by adopting a wireless transmission module, so that the menu setting can be reduced, the manufacturing cost can be saved, and the method is more convenient and fast and is suitable for various scenes.
Description
Technical Field
The invention relates to the field of electroplating, in particular to an electroplating method of a semiconductor device.
Background
Plating (plating) is a common method for manufacturing metal, and has the advantages of faster plating efficiency than PVD, suitability for large-area metal wire laying and thicker process, and is widely applied to manufacturing of partial metal layer in semiconductor, such as formation of air bridge.
The electroplating process comprises the following steps: sputtering metals such as titanium, titanium tungsten and the like on a silicon wafer to be used as an adhesion layer, sputtering a very thin layer of gold to be used as an electroplated conducting layer, and forming a seed layer by the adhesion layer and the conducting layer; then coating photoresist on the seed layer, and developing a pattern required by electroplating by photoetching; electroplating metal after cleaning; and removing the residual photoresist, and finally etching the seed layer outside the pattern to obtain the electroplated metal layer.
The general electroplating parameter setting is related to the metal area ratio formed on the wafer, i.e. the same target thickness, if the total electroplating time is not changed, the current intensity will be in direct proportion to the light transmittance of the photolithography plate, so different menus are required to be set for different products and different layers according to different light transmittances. Therefore, in the prior art, the current intensity is usually adjusted according to the menu, and then the thickness of the plated metal is controlled according to the time preset on the menu. In actual production, the condition that a menu is not timely modified and the current intensity is adjusted easily exists according to process modification, so that the target thickness of the final electroplated metal cannot meet the requirement, and the thickness of the final electroplated metal cannot meet the requirement until electroplating is finished or product production is finished, so that serious economic loss is brought to manufacturers.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides an electroplating method of a semiconductor device.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
an electroplating method comprising the steps of:
1) providing a wafer structure to be electroplated, wherein the wafer structure to be electroplated comprises a preset electroplating area and a front process layer with a first height formed around the preset electroplating area, a seed layer is arranged on the preset electroplating area, and no seed layer is arranged at the top of the side wall of the front process layer around the preset electroplating area;
2) electroplating at a preset constant current value in the electroplating process, arranging a detection circuit for monitoring a resistor above the pre-process layer around the preset electroplating area, acquiring first time from the beginning of electroplating to the change of the resistor of the detection circuit, and calculating the ratio of the first height to the first time to obtain an electroplating rate;
3) obtaining the target thickness of the electroplated metal, and calculating the ratio of the target thickness of the electroplated metal to the electroplating rate to obtain the total electroplating time;
4) and finishing the electroplating at the preset constant current value in the total electroplating time.
In some embodiments, the step 2 of obtaining a first time from the beginning of electroplating to the occurrence of the change in the resistance of the detection loop specifically includes:
acquiring a first resistor of the detection loop before electroplating;
a first time at which the resistance of the detection circuit changes from the first resistance to the second resistance is monitored during the electroplating process.
In some embodiments, the second resistance is 20% -80% of the first resistance.
In some embodiments, a seed layer is disposed on a surface of the pre-process layer, and a contact point of the detection circuit and the seed layer of the pre-process layer is disposed in a non-photoresist covering region.
In some embodiments, an included angle formed between a sidewall of the pre-process layer around the predetermined plating region and a surface of the predetermined plating region is less than or equal to 90 °.
In some embodiments, the pre-process layer includes a first photoresist and a second photoresist on two opposite sides of the periphery of the predetermined plating area a, the first photoresist and the second photoresist are disconnected, and the contact points of the detection circuit and the pre-process layer are respectively disposed on the surfaces of the first photoresist and the second photoresist.
In some embodiments, the pre-plating region and the pre-process layer are disposed in a non-device active region on the wafer structure to be plated.
In some embodiments, further comprising: and wirelessly transmitting the resistance signal obtained by the detection circuit through a wireless transmission module.
In some embodiments, the wireless transmission module is disposed in a non-device working area on the wafer structure to be electroplated, and is fixed on the wafer structure to be electroplated by a conductive adhesive and connected to the detection circuit.
In some embodiments, the wireless transmission module comprises a bluetooth module.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention adopts the detection circuit to measure the change of the resistance of the seed layer of the pre-process layer around the preset electroplating area before and during the electroplating, the detection of the electroplating speed can be realized through the first height of the pre-process layer and the first time of the resistance change, and the time required for electroplating to reach the target thickness can be automatically calculated.
(2) The invention is based on the prior process layer, fixes the current intensity, arranges the plating layer resistance detection circuit, achieves the detection of the plating rate, and obtains the total plating time by calculation according to the plating rate and the target thickness, thereby avoiding the process of adjusting the current intensity by setting different menus, reducing the monitoring and menu setting and saving the manufacturing cost.
(3) The resistance signal wireless transmission device can also adopt the circuit design of a Bluetooth patch, realizes the wireless transmission of the resistance signal by the wireless connection of the Bluetooth module and the communication module of the detection circuit, is suitable for scenes such as rotary electroplating and the like, and is more intelligent and convenient.
Drawings
Fig. 1 is a top view of a wafer structure according to a first embodiment of the invention;
FIG. 2 is a diagram illustrating a detection circuit for monitoring a first resistance before plating according to a first embodiment of the present invention;
FIG. 3 is a diagram illustrating a second resistance monitored by a detection circuit during electroplating according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating a detection circuit for monitoring a first resistance before plating according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating a second resistor monitored by a detection circuit during electroplating according to a second embodiment of the present invention;
fig. 6 is a schematic diagram of a bluetooth module patch according to a third embodiment of the present invention;
fig. 7 is a top view of a bluetooth module patch on a wafer according to a third embodiment of the present invention.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The definitions of the top and bottom relationships of the relative elements and the front and back sides of the figures described herein are understood by those skilled in the art to refer to the relative positions of the components and thus all of the components may be flipped to present the same components and still fall within the scope of the present disclosure.
Example one
The plating method of the present invention will be described in detail with reference to FIGS. 1 to 3.
S1, providing a wafer structure to be electroplated, wherein the wafer structure to be electroplated comprises a preset electroplating area A and a front process layer 1 with a first height formed around the preset electroplating area A, and seed layers 2 are arranged on the surfaces of the preset electroplating area A and the front process layer 1. The wafer structure to be electroplated has completed part of the device manufacturing process, and is formed with a front process layer 1 and a preset electroplating area A which is separated from the front process layer 1 by a first height h, because the height of the preset electroplating area A is lower than that of the front process layer 1, the thickness of electroplating metal on the preset electroplating area A is gradually increased in the electroplating process, and is at least flush with the surface of the front process layer 1, and the target thickness is reached according to the total electroplating time. The pre-process layer 1 is an insulating layer or a semiconductor layer formed by the pre-process and having a detection pattern with a certain height with respect to the predetermined plating area a.
In a specific embodiment, the seed layer 2 is sputtered on the wafer structure to be electroplated, the photoresist is coated, and the wafer structure is exposed and developed, so that the seed layer 2 is arranged on both the front process layer 1 and the preset electroplating area a, and an included angle formed between the side wall of the front process layer 1 and the surface of the preset electroplating area a is smaller than or equal to 90 °. In this case, the seed layer 2 is not sputtered on the sidewall of the pre-process layer 1, so as to avoid the conduction of the detection circuit, and it is noted that there is no seed layer 2 on the top of the sidewall of the pre-process layer 1 around the preset electroplating region a, so that even if the seed layer 2 is sputtered on any position below the top of the sidewall of the pre-process layer 1 around the preset electroplating region a, the monitoring accuracy of the detection circuit is not affected. The preset electroplating area A is not covered with photoresist, a resistance detection circuit is constructed above the non-photoresist covering area of the seed layer 2 of the prior process layer 1, and the specific detection circuit can adopt a two-probe or four-probe resistance detection mode. In a preferred embodiment, the contact points of the detection circuit and the seed layer 2 of the pre-process layer 1 are respectively disposed on two opposite sides around the preset electroplating region a, but not limited thereto, and the seed layer 2 of the pre-process layer 1 may also be disposed on any two positions of the non-photoresist covered region. Referring to fig. 1, the preset electroplating region and the pre-process layer are disposed in a non-device working region B on the wafer structure to be electroplated, for example, may be disposed in a passive region at the edge of the device working region, and may not affect the manufacturing of the device in the active region.
S2, obtain the first resistor R1 of the detection circuit. Referring to fig. 2, the first resistor R1 may be the first resistor R1 obtained by a detection circuit test before electroplating, or the first resistor R1 obtained by the detection circuit test when the plated metal above the predetermined plating area a is not even with the seed layer 2 of the previous process layer 1 and the plated metal on the predetermined plating area a is not connected with the plated metal on the previous process layer 1, and the first resistor R1 has a high resistance.
And S3, keeping the current intensity of the electroplating unchanged during the electroplating process, and monitoring the resistance change of the detection circuit until the resistance changes into a second resistance. Referring to fig. 3, in the electroplating process, when the height of the plated metal 3 formed in the predetermined plating area a reaches a first height h, the resistance becomes a second resistance R2 when the plated metal 3 formed in the predetermined plating area a is connected to the seed layer 2 above the front process layer 1, at this time, the surface of the plated metal 3 is flush with the surface of the seed layer 2 of the front process layer 1, the plated metal on the predetermined plating area a is connected to the plated metal on the front process layer 1, so that the detection circuit is turned on, the resistance obtained by the detection circuit is reduced to a second resistance R2, and the thickness of the plated metal 3 is equal to the first height h. Since there is no seed layer 2 on the top of the sidewall of the pre-process layer 1 around the predetermined electroplating area a, it can be ensured that the thickness of the electroplated metal on the predetermined electroplating area a is equal to the first height h when the first resistance monitored by the detection circuit is changed into the second resistance. The second resistor R2 is 20% -80% of the first resistor R1.
S4, a first time t from the beginning of electroplating to the time when the resistance changes to the second resistance is obtained, and the first time t can be obtained by using a timer or the like. Obtaining an electroplating rate v according to the first height h and the first time t, and calculating by adopting the following formula to obtain the electroplating rate v:
v＝h/t。
that is, the plating rate v is the ratio of the first height h to the first time t.
S5, obtaining the target thickness H of the electroplated metal 3, and obtaining the total electroplating time T according to the target thickness H of the electroplated metal 3 and the electroplating speed v, wherein the total electroplating time T is calculated according to the following formula: and T is H/v.
That is, the total plating time T is a ratio of the target thickness H of the plated metal 3 to the plating rate v.
And S6, electroplating at a preset constant current value in the total electroplating time T so as to achieve that the final thickness of the electroplated metal 3 reaches the target thickness H.
Because the current intensity is kept unchanged in the electroplating process, the electroplating speed is also fixed and unchanged, the monitoring of the electroplating speed is achieved by arranging the resistance detection circuit on the basis of the prior process layer, the total time required by electroplating to the target thickness can be automatically calculated, the parameter setting mode in the electroplating process is changed, the monitoring and menu setting are reduced, the economic loss caused by error modification among different menus is effectively avoided, and the manufacturing cost can be effectively saved.
Example two
The difference between the second embodiment and the first embodiment is that: referring to fig. 4 and 5, the pre-process layer 1 is a photoresist coated on the wafer before the electroplating process, the position of a preset electroplating region a is defined by the photoresist, the seed layer 2 is not on the photoresist, and the pre-process layer 1 includes a first photoresist and a second photoresist on two opposite sides around the preset electroplating region a, the first photoresist and the second photoresist are disconnected, a plating metal is also deposited on the photoresist during the electroplating process, due to the disconnection between the first photoresist and the second photoresist, the plating metals on the first photoresist and the second photoresist are insulated from each other before the thickness of the plating metal in the preset electroplating region a reaches a first height h, contact points of the detection circuit and the seed layer 2 of the pre-process layer 1 are respectively arranged on the surfaces of the first photoresist and the second photoresist on two opposite sides around the preset electroplating region a, at this time, before the thickness of the plating metal in the predetermined plating area a reaches the first height h, the detection circuit is turned off, the resistance monitored by the detection circuit is the first resistance R1, and the first resistance R1 is infinite. When the thickness of the plated metal reaches the target thickness, the plated metal on the front process layer 1 is connected to the plated metal in the predetermined plating area a, the detection circuit is turned on, and the resistance monitored by the detection circuit is changed to the second resistor R2, the second resistor R2 has a resistance, and the rest is the same as that of the first embodiment.
EXAMPLE III
The difference between the third embodiment and the first or second embodiment is that: in a third embodiment, a wireless transmission module is added to the detection circuit of the first or second embodiment, and the wireless transmission module is disposed in a non-device working area of a wafer structure to be plated, such as a bluetooth module. Referring to fig. 6 and 7, the bluetooth module 4 is mounted on the edge C of the wafer structure to be plated in the manner of a conductive adhesive 5 patch. The control module in the detection circuit is connected with the Bluetooth module 4, so that the resistance signal monitored in the detection circuit is wirelessly transmitted with the outside through the Bluetooth module 4, the requirements of scenes such as rotary electroplating are met, and the test and transmission of the resistance signal of the detection circuit are prevented from being influenced in the states of rotation or movement of a wafer and the like.
It should be noted that the electroplating methods of the first, second and third embodiments are applicable to any semiconductor manufacturing method using an electroplating process, including but not limited to HBT devices and HEMT devices.
The above embodiments are only intended to further illustrate the electroplating method of a semiconductor device according to the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
1. A method for electroplating a semiconductor device, comprising the steps of:
1) providing a wafer structure to be electroplated, wherein the wafer structure to be electroplated comprises a preset electroplating area and a front process layer with a first height formed around the preset electroplating area, a seed layer is arranged on the preset electroplating area, and no seed layer is arranged at the top of the side wall of the front process layer around the preset electroplating area;
2) electroplating at a preset constant current value in the electroplating process, arranging a detection circuit for monitoring a resistor above the pre-process layer around the preset electroplating area, acquiring first time from the beginning of electroplating to the change of the resistor of the detection circuit, and calculating the ratio of the first height to the first time to obtain an electroplating rate;
3) obtaining the target thickness of the electroplated metal, and calculating the ratio of the target thickness of the electroplated metal to the electroplating rate to obtain the total electroplating time;
4) and finishing the electroplating at the preset constant current value in the total electroplating time.
2. The electroplating method according to claim 1, wherein the step 2 of obtaining a first time from the beginning of electroplating to the occurrence of the change in the resistance of the detection loop comprises:
acquiring a first resistor of the detection loop before electroplating;
a first time at which the resistance of the detection circuit changes from the first resistance to the second resistance is monitored during the electroplating process.
3. The plating method of claim 2, wherein the second resistance is 20% to 80% of the first resistance.
4. The electroplating method of claim 1, wherein a seed layer is disposed on the surface of the pre-process layer, and the contact point of the detection circuit and the seed layer of the pre-process layer is disposed in a non-photoresist-covered region.
5. The plating method as recited in claim 4, wherein an angle formed between a sidewall of the pre-process layer around the pre-plating region and a surface of the pre-plating region is less than or equal to 90 °.
6. The electroplating method according to claim 1, wherein the pre-process layer comprises a first photoresist and a second photoresist on two opposite sides around the preset electroplating region A, the first photoresist and the second photoresist are disconnected, and contact points of the detection circuit and the pre-process layer are respectively arranged on the surfaces of the first photoresist and the second photoresist.
7. The electroplating method of claim 1, wherein the pre-plating region and the pre-process layer are disposed in a non-device active region on the wafer structure to be electroplated.
8. The plating method according to claim 1, further comprising: and wirelessly transmitting the resistance signal obtained by the detection circuit through a wireless transmission module.
9. The electroplating method according to claim 8, wherein the wireless transmission module is disposed in a non-device working area on the wafer structure to be electroplated, and is fixed on the wafer structure to be electroplated through a conductive adhesive and connected to the detection circuit.
10. The plating method of claim 8, wherein the wireless transmission module comprises a bluetooth module.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165571A (en) * | 2013-02-28 | 2013-06-19 | 江阴长电先进封装有限公司 | Novel silicon substrate low resistance inductance structure and wafer level encapsulating method thereof |
| JP2014103255A (en) * | 2012-11-20 | 2014-06-05 | Micronics Japan Co Ltd | Multilayer wiring board and method for manufacturing the same |
| CN104576428A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Film thickness detection method |
| US20150332925A1 (en) * | 2014-05-19 | 2015-11-19 | International Business Machines Corporation | Semiconductor structures having low resistance paths throughout a wafer |
| CN109545738A (en) * | 2018-11-12 | 2019-03-29 | 苏州汉骅半导体有限公司 | Air bridges manufacturing method |
| US10529622B1 (en) * | 2018-07-10 | 2020-01-07 | International Business Machines Corporation | Void-free metallic interconnect structures with self-formed diffusion barrier layers |
| CN113403657A (en) * | 2021-06-21 | 2021-09-17 | 北京世维通科技股份有限公司 | Electroplating method for accurately controlling thickness of coating |
-
2021
- 2021-11-24 CN CN202111405176.1A patent/CN114277409B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014103255A (en) * | 2012-11-20 | 2014-06-05 | Micronics Japan Co Ltd | Multilayer wiring board and method for manufacturing the same |
| CN103165571A (en) * | 2013-02-28 | 2013-06-19 | 江阴长电先进封装有限公司 | Novel silicon substrate low resistance inductance structure and wafer level encapsulating method thereof |
| CN104576428A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Film thickness detection method |
| US20150332925A1 (en) * | 2014-05-19 | 2015-11-19 | International Business Machines Corporation | Semiconductor structures having low resistance paths throughout a wafer |
| US10529622B1 (en) * | 2018-07-10 | 2020-01-07 | International Business Machines Corporation | Void-free metallic interconnect structures with self-formed diffusion barrier layers |
| CN109545738A (en) * | 2018-11-12 | 2019-03-29 | 苏州汉骅半导体有限公司 | Air bridges manufacturing method |
| CN113403657A (en) * | 2021-06-21 | 2021-09-17 | 北京世维通科技股份有限公司 | Electroplating method for accurately controlling thickness of coating |
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