CN113416988B - Electroplating method - Google Patents
Electroplating method Download PDFInfo
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- CN113416988B CN113416988B CN202110685013.7A CN202110685013A CN113416988B CN 113416988 B CN113416988 B CN 113416988B CN 202110685013 A CN202110685013 A CN 202110685013A CN 113416988 B CN113416988 B CN 113416988B
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- 238000009713 electroplating Methods 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 claims abstract description 30
- 238000007747 plating Methods 0.000 claims abstract description 18
- 239000007769 metal material Substances 0.000 claims abstract description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 24
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 229910052763 palladium Inorganic materials 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/16—Electroplating with layers of varying thickness
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/54—Electroplating of non-metallic surfaces
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention discloses an electroplating method, which comprises the following steps: manufacturing a graphical conductive seed layer on a substrate to be plated; manufacturing an electroplating mask pattern on the substrate to be plated and the graphical conductive seed layer, wherein the groove pattern of the electroplating mask pattern corresponds to a part needing to be thickened; and filling a metal material in the groove pattern of the electroplating mask pattern to obtain a thickened metal pattern. By adopting the scheme provided by the invention, the groove pattern is formed above the position, needing to be thickened, of the graphical conductive seed layer, the metal wire formed by filling metal in the groove pattern is directly connected with the graphical conductive seed layer, the thickness of the part of the conductive element is directly increased, and therefore, the thickness of the local plating layer can be accurately controlled according to the thickness requirement during electroplating, and the thickness of the local plating layer can be accurately controlled.
Description
Technical Field
The invention relates to the technical field of electroplating processes, in particular to an electroplating method for accurately controlling the thickness of a plating layer.
Background
Electroplating is a common traditional process in the fields of circuit board manufacturing, MEMS manufacturing, IC manufacturing, and the like, and is generally used for manufacturing metal interconnection structures to achieve electrical connection between elements and between layers of multilayer wiring circuits.
Because different application fields have different requirements on parameters such as the thickness, the height-width ratio, the uniformity and the like of an electric connecting wire, at present, the position of a substrate to be plated, the sizes and the shapes of an electroplating device and an electroplating anode, the size and the pulse period of electroplating current, a liquid medicine circulating system and the like are adjusted according to experience, and the current density of each area on the substrate to be plated is adjusted by changing the distribution of a power line outside a plating part, so that the purpose of controlling the thickness of a plating layer is achieved.
The above adjusting method can only integrally adjust the difference of the plating thickness in each area, and cannot accurately control the plating thickness of local lines, so that the application scene with higher precision requirement on the metal plating thickness cannot be met.
Disclosure of Invention
The embodiment of the application aims to provide an electroplating method to solve the technical problem that the electroplating process in the prior art cannot accurately control the thickness of a local line coating.
In order to solve the above problems, some embodiments of the present application provide an electroplating method, including the following steps:
manufacturing a graphical conductive seed layer on a substrate to be plated;
manufacturing an electroplating mask pattern on the substrate to be plated and the graphical conductive seed layer, wherein the groove pattern of the electroplating mask pattern corresponds to a part needing to be thickened;
and filling a metal material in the groove pattern of the electroplating mask pattern to obtain a thickened metal pattern.
Some embodiments provide the electroplating method, wherein the step of manufacturing a patterned conductive seed layer on a substrate to be plated comprises:
depositing a conductive seed layer on the substrate to be plated;
manufacturing a seed layer mask pattern on the conductive seed layer;
and etching the conductive seed layer with the seed layer mask pattern to expose the substrate to be plated, and reserving the conductive seed layer at the area covered by the seed layer mask pattern on the substrate to be plated to form the patterned conductive seed layer.
Some embodiments provide the electroplating method, wherein the step of forming a patterned conductive seed layer on the substrate to be plated includes:
manufacturing a seed layer mask pattern on the substrate to be plated;
depositing a conductive seed layer on the substrate to be plated with the seed layer mask pattern;
and removing the seed layer mask pattern to expose the substrate to be plated, and reserving the conductive seed layer in the region of the substrate to be plated covered by the seed layer-free mask pattern to form the patterned conductive seed layer.
Some embodiments provide the electroplating method, wherein the patterned conductive seed layer and the electroplating mask pattern have different projections in a thickness direction.
Some embodiments provide the electroplating method, wherein the projecting of the patterned conductive seed layer and the electroplating mask pattern in the thickness direction is different comprises:
the shapes of the electroplating mask pattern and the patterned conductive seed layer are not overlapped; and,
the electroplating mask pattern is not complementary to the patterned conductive seed layer in shape.
In some embodiments, in the electroplating method, a side of the substrate to be plated for forming the patterned conductive seed layer includes at least one of an insulating material and a semiconductor material.
Some embodiments provide the plating method, wherein the material of the conductive seed layer includes at least one of palladium, titanium, nickel, copper, gold, and silver; alternatively, an alloy material containing at least one of palladium, titanium, nickel, copper, gold, and silver is included.
In the electroplating method provided by some embodiments, in the step of forming the electroplating mask pattern on the substrate to be plated and the patterned conductive seed layer:
manufacturing the electroplating mask pattern by a photoresist manufacturing or hard mask material manufacturing mode;
wherein the photoresist comprises at least one of a photoresist and a dry film photoresist; the hard mask material comprises at least one of silicon, silicon oxide, silicon nitride and silicon oxynitride.
Some embodiments provide the electroplating method, further comprising the following steps:
removing the electroplating mask pattern;
and removing the patterned conductive seed layer which is not covered by the thickened metal pattern.
In the electroplating method provided in some embodiments, a metal material is filled in the groove pattern of the electroplating mask pattern to obtain a thickened metal pattern, and the step of:
in the thickened metal pattern, the ratio of the thickness to the width of the metal wire is more than 2.
Compared with the prior art, the technical scheme provided by the application at least has the following beneficial effects: according to the scheme, the graphical conductive seed layer is manufactured on the substrate to be plated, the electroplating mask graph is manufactured on the substrate to be plated and the graphical conductive seed layer, the electroplating mask graph is designed in a graphical mode according to the portion, needing to be thickened, of the graphical seed layer, the metal material is filled in the groove graph of the electroplating mask graph, and the thickened metal graph is obtained. Obviously, a groove pattern is formed above the position, needing to be thickened, of the patterned conductive seed layer, the metal wire formed by filling metal in the groove pattern is directly connected with the patterned conductive seed layer, the thickness of the part of the conductive element is directly increased, and therefore the thickness of the local plating layer can be accurately controlled according to the thickness requirement during electroplating.
Drawings
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
FIG. 1 is a flow chart illustrating steps of an electroplating method according to one embodiment of the present disclosure;
FIGS. 2 a-2 d are schematic views of a plated part at various stages during the execution of an electroplating method according to an embodiment of the present invention;
FIGS. 3 a-3 d are schematic views of the structure of the electroplating part at various stages in the process of forming the patterned conductive seed layer according to an embodiment of the present disclosure;
FIGS. 4 a-4 c are schematic views of the structure of an electroplating part at various stages of an execution process for forming a patterned conductive seed layer according to another embodiment of the present application;
FIG. 5 is a schematic structural diagram of a metal electrode fabricated by an electroplating method according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a metal electrode prepared by an electroplating method according to another embodiment of the present application.
Detailed Description
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only used for convenience of description of the present application, and do not indicate or imply that the device or component being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The present embodiment provides an electroplating method, as shown in fig. 1 and fig. 2a to fig. 2d, the electroplating method includes the following steps:
the method comprises the following steps: and manufacturing a patterned conductive seed layer 2 on the substrate 1 to be plated. The substrate 1 to be plated may be a substrate including a functional element or a circuit, and the method for manufacturing the patterned conductive seed layer 2 may select a deposition manner, and the deposition manner may select a chemical vapor deposition manner.
Step two: and manufacturing an electroplating mask pattern 3 on the substrate to be plated 1 and the patterned conductive seed layer 2, wherein a groove pattern 3a of the electroplating mask pattern 3 corresponds to a part needing to be thickened. As shown in the figure, the bottom of the groove pattern 3a directly exposes the patterned conductive seed layer 2, so that the thickening effect can be directly exerted on the part of the patterned conductive seed layer 2 which needs to be thickened after the groove pattern 3a is filled with metal.
Step three: and obtaining a thickened metal pattern from the metal material 4 in the groove pattern 3a of the electroplating mask pattern 3.
In the above scheme provided by this embodiment, the patterned conductive seed layer 2 is fabricated on the substrate to be plated 1, the electroplating mask pattern 3 is fabricated on the substrate to be plated 1 and the patterned conductive seed layer 2, the electroplating mask pattern 3 is designed in a patterned manner according to the portion of the patterned conductive seed layer 2 that needs to be thickened, and the groove pattern 3a of the electroplating mask pattern 3 is filled with the metal material 4 to obtain the thickened metal pattern. Obviously, a groove pattern 3a is formed above a position to be thickened of the patterned conductive seed layer 2, and a metal wire formed by filling a metal material 4 in the groove pattern 3a is directly connected with the patterned conductive seed layer 2, so that the thickness of the part of the conductive element is directly increased, and the thickness of a local plating layer can be accurately controlled according to the thickness requirement during electroplating.
In some embodiments, the electroplating method described above, in conjunction with fig. 3a to 3d, can fabricate the patterned conductive seed layer 2 on the substrate 1 to be plated by:
step 1.1: depositing a conductive seed layer 21 on the substrate 1 to be plated; the material of the conductive seed layer 21 may be at least one of palladium, titanium, nickel, copper, gold and silver, or an alloy material containing at least one of palladium, titanium, nickel, copper, gold and silver. The conductive seed layer 21 may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or the like.
Step 1.2: manufacturing a seed layer mask pattern 2A on the conductive seed layer 21; the mask can be made of photoresist or hard mask material. The photoresist comprises at least one of photoresist and dry film photoresist, and the hard mask material comprises at least one of silicon, silicon oxide, silicon nitride and silicon oxynitride.
Step 1.3: and etching the conductive seed layer 21 with the seed layer mask pattern 2A to expose the substrate 1 to be plated, and reserving the conductive seed layer 21 on the substrate 1 to be plated in the coverage area of the seed layer mask pattern 2A to form the patterned conductive seed layer 2.
In some embodiments, the electroplating method described above, in conjunction with fig. 4 a-4 c, can be used to fabricate the patterned conductive seed layer 2 on the substrate 1 to be plated by:
step 2.1: and manufacturing a seed layer mask pattern 2B on the substrate 1 to be plated. The mask can be made of photoresist or hard mask material. The photoresist comprises at least one of photoresist and dry film photoresist, and the hard mask material comprises at least one of silicon, silicon oxide, silicon nitride and silicon oxynitride.
Step 2.2: and depositing a conductive seed layer 22 on the substrate to be plated 1 with the seed layer mask pattern 2B. Physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, and the like may be used. The material of the conductive seed layer can be at least one of palladium, titanium, nickel, copper, gold and silver, or an alloy material containing at least one of palladium, titanium, nickel, copper, gold and silver.
Step 2.3: and removing the seed layer mask pattern 2B to expose the substrate 1 to be plated, and reserving the conductive seed layer 22 in the substrate area to be plated covered by the seed layer-free mask pattern 2B to form the patterned conductive seed layer 2.
In some embodiments, as shown in fig. 2c, the patterned conductive seed layer 2 and the plating mask pattern 3 have different projections in the thickness direction. According to the requirement, a part of the patterned conductive seed layer 2 needs to be increased in thickness to meet the requirement of passing a larger current, so that the thickened part does not coincide with the original conductive area of the patterned conductive seed layer 2. Further, the different projection of the patterned conductive seed layer 2 and the electroplating mask pattern 3 in the thickness direction includes: the shapes of the electroplating mask pattern 3 and the patterned conductive seed layer 2 are not overlapped; and, the shape of the electroplating mask pattern 3 is not complementary to the shape of the patterned conductive seed layer 2.
In the above solution, the substrate 1 to be plated may be a substrate including a functional element or a circuit, wherein one surface of the substrate 1 to be plated, on which the patterned conductive seed layer 2 is formed, includes at least one of an insulating material and a semiconductor material. The material of the conductive seed layer comprises at least one of palladium, titanium, nickel, copper, gold and silver; or an alloy material containing at least one of palladium, titanium, nickel, copper, gold, and silver. Therefore, it is preferable that the metal material 4 filled in the groove pattern 3a of the plating mask pattern 3 includes at least one of palladium, titanium, nickel, copper, gold, and silver; or an alloy material containing at least one of palladium, titanium, nickel, copper, gold, and silver. Further preferably, the metal material 4 is the same as the material of the patterned conductive seed layer 2.
In some embodiments, in the above solutions, the second step is to fabricate the electroplating mask pattern by means of photoresist fabrication or hard mask material fabrication; wherein the photoresist comprises at least one of a photoresist and a dry film photoresist; the hard mask material includes at least one of silicon, silicon oxide, silicon nitride, and silicon oxynitride.
Preferably, in some embodiments, the electroplating method further comprises the following steps:
step four: the plating mask pattern 3 is removed from the structure shown in fig. 2d, and the resulting structure is shown in fig. 5.
Step five: the patterned conductive seed layer not covered by the thickened metal pattern is removed, leaving only the seed layer 23 that requires the thickened portions.
The structure of the metal electrode obtained by the present scheme is as shown in fig. 5, and the thickness of the conductive portion is the sum of the thicknesses of the metal material 4 and the original patterned conductive seed layer 2. Therefore, by adopting the scheme in the embodiment of the application, the pattern is manufactured on the conductive seed layer, the conductive seed layer is modified, the current density distribution in the conductive seed layer near the electrode can be adjusted, the thickness uniformity of the electrode is improved, the plating thickness of local lines can be accurately controlled, and the application scene with higher precision requirement on the metal plating thickness can be met.
In some preferred embodiments, in step three, the ratio of the thickness to the width of the metal line in the thickened metal pattern is greater than 2, preferably greater than 3, and may even reach greater requirements of 5 or 10. In the application, the electroplating mask pattern 3 is manufactured on the substrate 1 to be plated and the patterned conductive seed layer 2, and the ratio of the depth to the width of the groove pattern 3a of the electroplating mask pattern 3 can be larger than 3 or larger. And then filling a metal material 4 in the groove pattern 3a of the electroplating mask pattern 3 to obtain a thickened metal pattern, wherein the metal material 4 is finally formed into the metal wire, and the filling thickness of the metal material 4 is less than or equal to the depth of the groove pattern 3a, so that the filling proportion of the metal material 4 can be adjusted according to the depth of the groove pattern 3a to achieve the purpose that the ratio of the thickness to the width of the metal wire is greater than 2. The metal electrode obtained by the scheme can finally realize that the ratio of the whole thickness to the whole width is more than 3 and even can reach 10 or 20, and the metal electrode prepared by the method can greatly improve the bandwidth of a photoelectronic device.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (6)
1. An electroplating method, comprising the steps of:
manufacturing a graphical conductive seed layer on a substrate to be plated;
manufacturing an electroplating mask pattern on the substrate to be plated and the graphical conductive seed layer, wherein the groove pattern of the electroplating mask pattern corresponds to a part needing to be thickened;
filling a metal material in the groove pattern of the electroplating mask pattern to obtain a thickened metal pattern;
the patterned conductive seed layer and the electroplating mask pattern have different projections in the thickness direction; the method comprises the following steps: the shapes of the electroplating mask pattern and the patterned conductive seed layer are not overlapped; the shapes of the electroplating mask pattern and the patterned conductive seed layer are not complementary;
the step of manufacturing the graphical conductive seed layer on the substrate to be plated comprises the following steps:
depositing a conductive seed layer on the substrate to be plated; manufacturing a seed layer mask pattern on the conductive seed layer; etching the conductive seed layer with the seed layer mask pattern to expose the substrate to be plated, and reserving the conductive seed layer in the region covered by the seed layer mask pattern on the substrate to be plated to form the patterned conductive seed layer; or,
manufacturing a seed layer mask pattern on the substrate to be plated; depositing a conductive seed layer on the substrate to be plated with the seed layer mask pattern; and removing the seed layer mask pattern to expose the substrate to be plated, and reserving the conductive seed layer in the region of the substrate to be plated covered by the seed layer-free mask pattern to form the patterned conductive seed layer.
2. The plating method according to claim 1, characterized in that:
one side of the substrate to be plated, which is used for manufacturing the graphical conductive seed layer, comprises at least one of an insulating material and a semiconductor material.
3. The plating method according to claim 2, characterized in that:
the material of the conductive seed layer comprises at least one of palladium, titanium, nickel, copper, gold and silver; alternatively, an alloy material containing at least one of palladium, titanium, nickel, copper, gold, and silver is included.
4. The electroplating method according to any one of claims 1 to 3, wherein in the step of patterning the electroplating mask on the substrate to be plated and the patterned conductive seed layer:
manufacturing the electroplating mask pattern by a photoresist manufacturing or hard mask material manufacturing mode;
wherein the photoresist comprises at least one of a photoresist and a dry film photoresist; the hard mask material comprises at least one of silicon, silicon oxide, silicon nitride and silicon oxynitride.
5. An electroplating method according to any one of claims 1 to 3, further comprising the step of:
removing the electroplating mask pattern;
and removing the patterned conductive seed layer which is not covered by the thickened metal pattern.
6. The electroplating method according to claim 5, wherein the step of filling a metal material in the groove pattern of the electroplating mask pattern to obtain a thickened metal pattern comprises:
in the thickened metal pattern, the ratio of the thickness to the width of the metal wire is more than 2.
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