CN114270495A - 用于选择性金属通孔填充的工艺集成方法 - Google Patents
用于选择性金属通孔填充的工艺集成方法 Download PDFInfo
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- CN114270495A CN114270495A CN202080036748.0A CN202080036748A CN114270495A CN 114270495 A CN114270495 A CN 114270495A CN 202080036748 A CN202080036748 A CN 202080036748A CN 114270495 A CN114270495 A CN 114270495A
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Abstract
用于形成于基板上的互连结构的方法及装置及在该基板上形成该互连结构的方法。在实施方式中,所述方法包括以下步骤:蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过该低k介电层的通孔及暴露导电表面;将该导电表面与稀释的氢氟酸接触以从该导电表面移除污染物;移除设置在该低k介电层的顶部上的该硬质掩模;及向该导电表面施用远程氢等离子体以形成该导电表面的暴露部分。
Description
技术领域
本公开内容的实施方式一般涉及改善的形成互连结构的方法。
背景技术
可靠地生产低于100nm及更小的特征是半导体器件的下一代超大规模集成(VLSI)及极大规模集成(ULSI)的关键技术挑战中的一者。然而,随着电路技术极限的驱使,缩小的VLSI及ULSI技术的尺度已在处理能力上产生了额外的需求。可靠地在基板上形成栅极结构对于VLSI及ULSI的成功及增加个别基板及裸片(die)的电路密度及质量的持续努力而言是重要的。
随着下一代器件的电路密度增加,互连结构(例如通孔、沟槽、触点、栅极结构、及其他的特征)以及其间的介电材料的宽度减少到45nm及32nm的尺度或更小,而介电层的厚度保持实质恒定,其结果是特征的深宽比增加。为了允许制造下一代的器件及结构,通常利用半导体芯片的三维(3D)堆叠来改善晶体管的性能。通过用三维方式而不是常规的二维方式布置晶体管,可以将多个晶体管彼此非常靠近地安置在集成电路(IC)中。半导体芯片的3D堆叠减少了导线长度且保持低的布线延迟。在制造时,通常利用半导体芯片的3D堆叠(阶梯状结构)以允许将多个互连结构设置在其上,从而形成高密度的垂直晶体管器件。
并且,在堆叠形成期间形成于通孔的底部处的导电表面(例如铜表面或钴表面)一般被在通孔开放及后续的金属硬质掩模移除期间形成的蚀刻副产物及残余物污染。虽然可以通过后续的干清洁工艺来移除大尺寸的颗粒,但干清洁工艺不能移除来自蚀刻相关的元素(例如氧、氟、及碳)或来自由导电互连表面上的空气暴露所造成的氧化作用的原子级污染物。
一般而言,可以经由湿清洁方法来移除氟、氧、及碳污染物。然而,发明人已经观察到,由于低k电介质的兼容性问题以及最近对低k损伤的较严格的需求(例如碳耗竭问题),这些技术不能用于较新的后道(back end of the line,BEOL)工艺。因此,持续需要后通孔蚀刻清洁技术以改善电性能。
进一步地,发明人已经观察到,常规的通孔形成由于工艺集成中所使用的材料而导致高电阻。例如,用相同的材料填充通孔及连接到该通孔的沟槽导致高互连电阻,这可能不合需要地导致半导体芯片中的电阻-电容延迟(RC延迟)及电压下降(IR下降)。并且,阻挡及衬垫层的定位可能导致高的电阻率,从而例如在沉积在通孔底部处时导致高的通孔电阻。
因此,持续需要改善的形成互连结构的方法以减少集成电路的制造成本、存储单元尺寸、及功耗。
发明内容
本文中提供了用于形成互连结构的方法及装置。在一些实施方式中,一种形成互连结构的方法包括以下步骤:蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过该低k介电层的通孔及暴露导电表面;将该导电表面与稀释的氢氟酸接触以从该导电表面移除污染物;移除设置在该低k介电层的顶部上的该硬质掩模;及向该导电表面施用远程氢等离子体以形成该导电表面的暴露部分。
在一些实施方式中,一种形成互连结构的方法包括以下步骤:在包括设置在基板上的硬质掩模及介电层的膜堆叠中形成通孔及沟槽以暴露导电表面;将该导电表面与稀释的氢氟酸接触;移除该硬质掩模;向该导电表面施用远程等离子体以形成该导电表面的暴露部分;在该通孔中沉积第一类型的第一金属;在该第一金属及该沟槽的暴露表面上沉积阻挡层;在该阻挡层上沉积衬垫层;及用与该第一金属不同的第二金属填充该沟槽。
在一些实施方式中,提供了一种非暂时性计算机可读介质,该非暂时性计算机可读介质具有存储在其上的指令,所述指令在被执行时造成执行形成互连结构的方法。该方法可以如本文中所公开的实施方式中的任一者中所描述。在一些实施方式中,该方法包括以下步骤:蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过该低k介电层的通孔及暴露导电表面;将该导电表面与稀释的氢氟酸接触以从该导电表面移除污染物;移除设置在该低k介电层的顶部上的该硬质掩模;及向该导电表面施用远程氢等离子体以形成该导电表面的暴露部分。
下文中描述本公开内容的其他及另外的实施方式。
附图说明
可以通过参照描绘于附图中的本公开内容的说明性实施方式来了解本公开内容的实施方式,所述实施方式在上文被简要概述且于下文被更详细地论述。然而,附图仅绘示本公开内容的典型实施方式且因此不要被视为范围的限制,因为本公开内容可以接纳其他同等有效的实施方式。
图1绘示依据本公开内容的一个实施方式的形成互连结构的方法。
图2A-图2K绘示依据本公开内容的一个实施方式的在图1的方法的不同阶段处形成于基板上的互连结构的侧横截面图。
图3绘示依据本公开内容的一个实施方式的多腔室处理系统,图1的方法可以实行在该处理系统上。
图4绘示依据本公开内容的一个实施方式的形成互连结构的方法。
图5绘示依据本公开内容的一个实施方式的形成互连结构的方法。
为了促进了解,已尽可能使用相同的附图标记来标志所述附图共有的相同构件。所述附图并不是按比例绘制的,且可以为了明确起见而简化所述附图。可以在不另外详述的情况下有益地将一个实施方式的构件及特征并入其他实施方式。
具体实施方式
本文中提供了用于处理基板的方法。本公开内容的实施方式有利地促进清洁和/或减少(例如部分或完全移除氧)导电互连表面,同时维持IC互连结构的低k完整性、导电率、及可靠度。在实施方式中,变化通孔及连接到通孔的沟槽中所使用的材料减少或消除了半导体芯片中的RC延迟及IR下降。进一步地,在通孔与连接到通孔的沟槽之间安置阻挡层及衬垫层减少了通孔电阻。本公开内容的方法可以用于在集成电路中形成金属互连结构,或用于形成金属栅极或金属-接点的间隙填充工艺,以及用于可以在通孔孔洞中执行金属清洁或减少的其他合适应用。
图1描绘依据本公开内容的一些实施方式用于处理基板的方法100的流程图。下文针对如图2A-图2K中所描绘的处理基板的阶段描述方法100,图2A-图2K绘示在图1的方法100之前及在方法100的不同阶段的基板的横截面图,并且,可以例如在合适的反应器(例如下文针对图3所描述的反应器)中执行方法100。可以用来执行本文中所公开的方法的示例性处理系统可以包括(但不限于)可从加州圣克拉拉市的应用材料有限公司购得的 或处理系统线中的任一者。也可以将其他的处理腔室(包括可从其他制造商取得的处理腔室)合适地与本文中所提供的教示结合使用。
图2A绘示在方法100开始之前的互连结构200的横截面图。一般而言,互连结构200包括多个膜层,所述膜层可以用来形成例如双镶嵌结构的互连结构。膜堆叠201形成于基板202上。膜堆叠201包括第二介电层204。如图2A中所示的第二介电层204被设置在基板202上,且具有形成于第二介电层204中且用该第二介电层为界的导电层206。在一个示例中,第二介电层204可以由一种或多种绝缘材料(例如氧化硅)所形成。在一个示例中,导电层206可以由例如铜或钴的导电层所形成。
回到图1,在方块102处,可以可选地将介电阻挡层208沉积于基板202上,如图2B中所绘示。例如,如所绘示,将介电阻挡层208沉积在第二介电层204及导电层206上方。因此,介电阻挡层208可以在第二介电层204及导电层206上方形成均匀、不间断的层。介电阻挡层可以由低k材料所形成。例如,介电阻挡层208可以由含碳硅层(SiC)、掺氮的含碳硅层(SiCN)、氮化硅层、金属氮化物或金属氧化物(例如AlN、AlOx、AlON)等等所形成。
现参照方块104,将介电层210沉积于基板202上,如图2C中所绘示。例如,如所绘示,将介电层210沉积在介电阻挡层208上方。介电层210可以与第二介电层204实质类似。在一个实施方式中,介电层210可以由与第二介电层204相同的材料所形成。在另一个实施方式中,介电层210可以由与第二介电层204不同的材料所形成,同时维持相同的低k性质。在另一个示例中,介电层210可以由低k材料(例如具有小于氧化硅或小于约3.9的介电常数的材料)等等所形成。在实施方式中,介电层210是致密材料,例如可从应用材料有限公司取得的Black1牌低k材料。
现参照方块105,将硬质掩模211设置在可以是低k介电层的介电层210的顶部上,如图2D中所绘示。例如,如所绘示,将硬质掩模211沉积在介电层210上方。在一个实施方式中,硬质掩模211可以由任何合适的硬质掩模材料所形成。因此,硬质掩模211可以直接在介电层210的顶部上及导电层206上方形成均匀、不间断的层。在实施方式中,硬质掩模211是介电材料(例如SiO2、SiCO、SiON、或SiC)、金属间/金属材料(例如TiN或Ti)、或介电材料与金属间/金属材料的组合。在一些实施方式中,硬质掩模211是由氮化钛(TiN)或氮化钽(TaN)所形成的层。在实施方式中,硬质掩模211具有15到25纳米的厚度。
在方块106处,将一个或多个通孔212形成于互连结构200中以暴露导电层206,如图2E中所绘示。例如,可以将通孔212形成穿过硬质掩模211、介电层210、及可选的介电阻挡层(例如介电阻挡层208),以暴露下伏的导电层206。在实施方式中,本公开内容包括以下步骤:蚀刻穿过设置在低k介电层(例如介电层210)的顶部上的硬质掩模211以形成穿过低k介电层的通孔212及暴露导电表面(例如导电层206)。一般而言,通孔212具有宽度W1。在一些实施方式中,每个通孔212的宽度在通孔212的整个长度上是均匀的。在其他的实施方式中,每个通孔212的宽度均可以从通孔212的顶部向通孔212的底部逐渐改变。在实施方式中,通孔212具有高的深宽比。
在方块108处,将一个或多个沟槽214形成于互连结构200中,如图2F中所绘示。可以将该一个或多个沟槽214形成穿过硬质掩模211且形成到介电层210中。在实施方式中,该一个或多个沟槽214被配置为加宽通孔212的至少一部分。在一些实施方式中,可以在方块106之前执行方块108,即可以在通孔212之前形成沟槽214。在其他的实施方式中,在形成通孔212或一个或多个通孔之后形成该一个或多个沟槽214。
本公开内容的实施方式包括选择性填充方法(例如铜或钨填充方法),其展示较低的通孔电阻,同时满足集成及可靠度需求。开发了接口处理(在下文与至少方块110结合论述)及填充工艺(在下文与至少方块118结合论述)以在不损伤下伏的金属层(例如Cu、W、Co等等)及周围的电介质(例如低k电介质、氧化物等等)的情况下从通孔底部选择性地生长金属材料(例如Cu或W)。其结果是,以下的论述提供了一种或多种降低通孔电阻的技术。在实施方式中,在通孔填充之后,将接着进行镶嵌填充,该镶嵌填充有助于形成相等的线电阻。
在实施方式中,方法100包括以下步骤:在方块110处,在互连结构200上执行一个或多个预处理工艺,以准备互连结构200以接收选择性金属通孔(例如通孔212)填充。例如,方块110可以包括子方块112-116。
在子方块112处,互连结构200经历用于通孔212中的导电层206的导电表面的暴露部分213的第一处理工艺。例如,第一预处理工艺用来准备导电层206的暴露部分213以用于在用第一金属沉积通孔212时从下向上的生长。在实施方式中,通孔212中的导电层206的暴露部分213在适于移除污染物的条件下与稀释的氢氟酸(DHF)接触。例如,导电表面(例如暴露部分213)与稀释的氢氟酸接触以移除从该导电表面移除污染物。在实施方式中,采用稀释的氢氟酸(DHF)处理,将呈稀释缓冲的氧化物蚀刻剂(BOE)的形式的HF涂敷到导电表面。稀释的氢氟酸(DHF)处理可以通过以下步骤来完成:用稀释的氢氟酸(DHF)填充罐,然后将互连结构200浸入到该罐中。为了防止条纹,应快速将互连结构200浸入在HF浴中。在实施方式中,稀释的氢氟酸(DHF)用来剥离氧化物,从而移除负电性比硅小的金属。在实施方式中,在将溶液快速倾倒到排放罐或回收单元之前,处理包括膜堆叠的互连结构200达约30到60秒的持续时间。在实施方式中,稀释的氢氟酸具有2-4、约3、或3的pH值。在实施方式中,稀释的氢氟酸具有0.01-0.5M的摩尔浓度。在实施方式中,在室温下将稀释的氢氟酸涂敷到膜堆叠达10到30秒、或10到20秒的持续时间。
回到图1及图2G,在用于通孔中的导电层206的暴露部分213的第一处理工艺之后,在方块114处,移除硬质掩模。在实施方式中,通过湿蚀刻移除工艺来移除硬质掩模,例如,在该湿蚀刻移除工艺中,硬质掩模在移除硬质掩模材料的条件下与湿蚀刻溶液接触。在实施方式中,移除设置在低k介电层(例如介电层210)的顶部上的硬质掩模。在一些实施方式中,通过将硬质掩模与用于移除硬质掩模的移除组成接触来移除硬质掩模。在一个实施方式中,移除组成是湿蚀刻溶液,该湿蚀刻溶液移除介电层上的金属硬质掩模,而不会腐蚀通孔中的导电层206的暴露部分213且不会腐蚀介电层210。在一些实施方式中,通过在适合剥离硬质掩模的条件下将硬质掩模与含过氧化物(例如H2O2)的碱性化学物质(高pH值(例如pH9-11))接触来移除硬质掩模。在实施方式中,移除组成是移除氮化钛硬质掩模的湿蚀刻溶液。在实施方式中,移除组成是移除TaN硬质掩模的湿蚀刻溶液。在实施方式中,移除组成包括腐蚀抑制剂以防止朝向导电层206的暴露部分213的氧化活动。在一些实施方式中,提供金属腐蚀抑制剂以防止铜、钴、及/或适于用作导电层206的其他金属氧化。金属腐蚀抑制剂的非限制性示例包括5-氨基-1,3,4-噻二唑-2-硫醇(ATDT)、苯并三唑(BTA)、1,2,4-三唑(TAZ)、甲苯基三唑、5-甲基-苯并三唑(MBTA)等等。在实施方式中,在硬质掩模材料不残留在介电层210上的情况下,移除硬质掩模211(例如TiN或TaN)。在一些实施方式中,用于本文中的非限制性湿蚀刻溶液包括来自BASF的S系列牌溶液。
仍参照图1,在硬质掩模移除之后,在方块116处,将等离子体清洁工艺施用于通孔中的导电层的暴露部分。在实施方式中,可以在硬质掩模移除之后使用远程等离子体清洁工艺来处理互连结构。例如,可以将远程氢等离子体施用于导电表面以形成导电表面的暴露部分,例如其中从该暴露部分或暴露面移除其氧化物。在实施方式中,等离子体清洁包括例如适于从导电层206的暴露部分213移除金属氧化物(例如氧化铜)的条件下的低密度氢等离子体清洁。在一些实施方式中,可以将互连结构200传送到处理腔室,在该处理腔室处,互连结构200经历等离子体清洁工艺。例如,互连结构可以经历约1-10托的压力下、使用H2或氢自由基、约150-250℃之间的清洁工艺。在其他的实施方式中,可以施加微小的偏压能量以促进没有金属溅射的情况下的氧化物脱落。例如,可以向预处理腔室施加0-200W的能量。在一些实施方式中,也可以在适于从导电层206的暴露部分213移除金属氧化物(例如氧化铜)的条件下施用醇(例如甲醇和/或乙醇)。例如,与用来在硬质掩模移除之后处理互连结构的远程等离子体清洁工艺结合,互连结构可以在呈150-250℃的量的温度下的热浸液中与乙醇和/或甲醇接触。在实施方式中,施用热醇浸液达30秒到1小时。
在一个实施方式中,用于依据本公开内容的等离子体清洁工艺的合适腔室包括例如可从应用材料有限公司取得的CuBS(铜阻挡/种晶)系统的Preclean(“APC”)腔室。在实施方式中,适用于本文中的等离子体清洁工艺为用于28nm世代及以下的节点的金属低k互连结构工艺方案提供了无害且高效的清洁工艺以供移除聚合残余物和/或金属氧化物(例如氧化铜(“CuO”))的反应。在实施方式中,APC被设计为有效地移除聚合残余物及减少CuO沉积物,同时保留多孔的低k及超低k的水平间介电(“ILD”)膜的完整性。
回到图1,在方块110(其中在互连结构200上执行一个或多个预处理工艺以准备互连结构200以接收选择性金属通孔(例如通孔212)填充)处的方法100之后,将第一金属层沉积在该一个或多个通孔中,如方块118处所示。在方块118处,第一金属220选择性地填充通孔212,如图2H中所绘示。例如,将第一金属220材料沉积在通孔212中达到点222,在该点处,通孔212与沟槽214会合。所使用的第一金属220可以是任何合适的金属材料,例如钌(Ru)、钨(W)、钴(Co)、铝(Al)、铜(Cu)等等。在一些实施方式中,第一金属220是与沉积在沟槽214中的后续金属不同的材料。选择性地将第一金属220沉积在通孔中有助于减少通孔电阻及满足可靠度及线电阻需求。
可以使用化学气相沉积(CVD)工艺来沉积第一金属220。在实施方式中,用于本文中的合适CVD工艺可以包括高温(例如350-500℃)下的H2预浸泡。在一些实施方式中,可以在广大的H2周围环境中使用低流速(例如2-100sccm)的含金属前驱物(例如WF6)在约200-500℃的温度下执行CVD工艺。在实施方式中,含金属前驱物被预先选定为在通孔中形成钌(Ru)、钨(W)、钴(Co)、铝(Al)、铜(Cu)中的至少一者。流速、压力、与温度的组合有助于在沉积时减少第一金属220的形态。在沉积第一金属220材料之前,可以对于初始的1-3nm的成核施用常规的成核层。整体生长量由工艺时间、压力、及前驱物流量所控制以均匀地填充通孔212。
在一些实施方式中,方法100可以包括在沉积额外的层或第二金属224之前执行的可选的方块(例如方块119)。在方块119处,互连结构200可以在第二金属224之前经历预处理工艺。在一些实施方式中,本公开内容的工艺可以包括方块119处的工艺序列,其中金属填充的通孔的顶面经历可选的后沉积清洁。例如,在通孔212的顶面处(例如在暴露表面处,例如通孔212与沟槽214会合的点222处)有氧化或残余物生长的情况下,可以使用可选的清洁。在实施方式中,可选的预处理清洁使用具有碱性pH值调整的含过氧化物(H2O2)的化学物质来稍微剥离残余物。在一些实施方式中,可以在沉积额外的层或第二金属224之前执行等离子体清洁工艺。例如,等离子体清洁可以可选地包括使用可从应用材料有限公司取得的Preclean(“APC”)腔室来提供无害且高效的清洁工艺以供移除形成在填充在通孔212中的第一金属220(或其暴露部分)的顶部上的金属氧化物或原生氧化物。例如,若是用铜填充通孔,则可以应用等离子体清洁步骤来移除通孔212与沟槽214会合的点222处的氧化铜(“CuO”)。
参照方块120处的图1及图2I,可以用一个或多个阻挡层235覆盖沟槽214。例如,可以由阻挡层235覆盖沟槽的侧壁251、沟槽的底面252(包括通孔212的暴露的金属表面253)。阻挡层216可以用来防止随后沉积的金属扩散到下伏层(例如介电层210)中。阻挡层235可以包括适合充当阻挡的任何材料。例如,在一些实施方式中,阻挡层235可以包括金属,例如钛(Ti)、钽(Ta)、钴(Co)(例如CVD沉积的钴)、锰(Mn)、钨(W)、铪(Hf)、上述项目的合金等等,或在一些实施方式中可以包括金属氮化物,例如氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)等等。阻挡层235可以具有适于防止随后沉积的金属层材料扩散到下伏层中的任何厚度。例如,在一些实施方式中,阻挡层235层可以具有约10到约20埃、或10到15埃的厚度。阻挡层235可以由适于提供具有合适厚度的阻挡层235的任何工艺所形成。例如,在一些实施方式中,可以经由沉积工艺来形成阻挡层235,例如化学气相沉积、物理气相沉积、或循环沉积工艺,举例而言,例如原子层沉积等等。在实施方式中,阻挡层235包括由原子层沉积(ALD)工艺来沉积的更多TaN层中的一者。在实施方式中,ALD工艺可以沉积TaN以形成阻挡层235、或阻挡层235的一个或多个层达足以充当阻挡层的厚度。在实施方式中,阻挡层235包括共形地沉积在内沟槽表面的顶部上的材料层。
参照方块170处的图1及图2J,可以将阻挡层235覆盖在一个或多个衬垫层(例如衬垫层236)中。在一些实施方式中,互连结构200可以包括衬垫层236,该衬垫层包括设置在阻挡层235的顶部上的钴。在实施方式中,可以通过在处理腔室中执行的CVD或PVD工艺来形成衬垫层236以在沟槽内的阻挡层的表面上方提供具有预定厚度的衬垫层。在实施方式中,衬垫层236是在沟槽的侧壁及底面的顶部上经由物理气相沉积(PVD)工艺沉积的钴层。在实施方式中,衬垫层被沉积到20到40埃(例如30埃)的厚度。在实施方式中,衬垫层是沉积到20到40埃(例如30埃)的厚度的钴。在一些实施方式中,例如为钴层的衬垫层236被共形地沉积以覆盖阻挡层235。
回到方块180处的图1及图2K,将第二金属224沉积在每个沟槽214中。例如,将第二金属224沉积在衬垫层236的顶部上达沟槽214的顶部。所使用的第二金属224可以是任何合适的金属材料,例如钌(Ru)、钨(W)、钴(Co)、铝(Al)、铜(Cu)等等。在一些实施方式中,第二金属224是与沉积在通孔212中的第一金属220材料不同的材料。在一些实施方式中,第二金属224是与沉积在通孔212中的第一金属220材料相同的材料。在实施方式中,可以使用CVD工艺来沉积第二金属224。将单一金属材料的常规金属填充二分成多步骤工艺有助于减少通过通孔212的电阻,该多步骤工艺涉及沉积在通孔212中的第一金属220、沉积在沟槽214中的第二金属224、及设置在第一金属220与第二金属224之间的阻挡层/衬垫层。
仍参照图2K,可以将盖顶层271沉积在第二金属的顶部上,如可选的方块190中所示。在实施方式中,盖顶层包括钴、钌、或其他合适的盖顶材料。
图3将多腔室处理系统绘示为处理系统300。处理系统300可以包括装载锁定腔室302、304、机器人306、传送腔室308、处理腔室310、312、314、316、318、328、及控制器320。装载锁定腔室302、304允许将基板(未示出)传送进及出处理系统300。装载锁定腔室302、304可以对引入到处理系统300中的基板抽气以维持真空密封。机器人306可以在装载锁定腔室302、304与处理腔室310、312、314、316、318、及328之间传送基板。机器人306也可以在装载锁定腔室302、304与传送腔室308之间传送基板。
每个处理腔室310、312、314、316、318、及328均可以配备为执行多种基板操作,例如原子层沉积(ALD)、化学气相沉积(CVD)、PVD、蚀刻、预清洁、脱气、加热、定向、或其他基板工艺。此外,每个处理腔室310、312、314、316、318、及328也可以配备为沉积介电阻挡层、沉积介电层、在堆叠中形成一个或多个通孔及沟槽、执行一个或多个预清洁工艺、沉积第一金属材料层、沉积衬垫层、沉积阻挡层、沉积第二金属材料层、或沉积盖顶层。
可以将控制器320配置为操作处理系统300的一些或所有方面,包括图1中所公开的方法。例如,可以将控制器320配置为控制在基板上形成互连结构的方法。控制器320包括与存储器324及大容量存储器件可操作的可编程中央处理单元(CPU)322、输入控制单元、及显示单元(未示出),例如耦接到处理系统的各种部件以促进控制基板处理的电源、时钟、高速缓存、输入/输出(I/O)电路、及衬垫。控制器320也包括用于经由处理系统300中的传感器(包括监测前驱物、处理气体、及净化气体流的传感器)监测基板处理的硬件。测量系统参数(例如基板温度、腔室大气压力等等)的其他传感器也可以向控制器320提供信息。
为了促进控制上述的处理系统300,CPU 322可以是可以用在工业环境中的任何形式的通用计算机处理系统中的一者(例如可编程逻辑控制器(PLC))以供控制各种腔室及子处理器。存储器324耦接到CPU 322,且存储器324为非暂时性的,且可以是可容易取得的存储器中的一者或多者,例如随机存取存储器(RAM)、只读存储器(ROM)、软盘驱动器、硬盘、或任何其他形式的数字存储器(位于本地或远程)。支持电路326耦接到CPU 322以供用常规方式支持处理器。带电物种产生、加热、及其他工艺一般存储在存储器324中(一般作为软件例程)。也可以由第二CPU(未示出)存储和/或执行软件例程,该第二CPU相对于由CPU 322所控制的硬件位于远程。
存储器324呈包含指令的计算机可读存储介质的形式,所述指令在由CPU322执行时促进处理系统300的操作。存储器324中的指令呈程序产品的形式,例如实施本公开内容的方法的程序。程序代码可以符合多种不同程序语言中的任何一者。在一个示例中,可以将本公开内容实施为存储在计算机可读存储介质上以供与计算机系统一起使用的程序产品。程序产品的程序界定了实施方式的功能(包括本文中所述的方法)。说明性的计算机可读存储介质包括(但不限于):(i)非可写入式存储介质(例如计算机内的只读存储器件,例如由CD-ROM驱动器可读取的CD-ROM光盘、闪存、ROM芯片、或任何类型的固态非易失性半导体存储器),信息可以永久存储在其上;及(ii)可写入式存储介质(例如磁盘驱动器内的软盘、或硬盘驱动器、或任何类型的固态随机存取半导体存储器),可变更的信息存储在其上。在携带指导本文中所述的方法的功能的计算机可读指令时,此类计算机可读存储介质是本公开内容的实施方式。
上文所论述的方法可以不仅仅局限于处理系统300。例如,可以在处理系统300外部的处理腔室中执行一个或多个方块(例如方块120或方块114)。
在一些实施方式中,本公开内容包括一种非暂时性计算机可读介质,具有存储在其上的指令,所述指令在被执行时造成一种方法一种形成互连结构的方法,该方法包括以下步骤:蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过该低k介电层的通孔及暴露导电表面;将该导电表面与稀释的氢氟酸接触以从该导电表面移除污染物;移除设置在该低k介电层的顶部上的该硬质掩模;及向该导电表面施用远程氢等离子体以形成该导电表面的暴露部分。
现参照图4,在一些实施方式中,本公开内容包括形成互连结构的方法400。方法400包括以下步骤:在方块402处,蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过低k介电层的通孔及暴露导电表面。接下来,在方块404处,方法400包括以下步骤:将导电表面与稀释的氢氟酸接触以从该导电表面移除污染物。在方块406处,方法400包括以下步骤:移除设置在低k介电层的顶部上的硬质掩模。在方块406处,方法400包括及向导电表面施加远程氢等离子体以形成导电表面的暴露部分。在一些实施方式中,方块402、404、406、及408的工艺序列如图4中所示地依序进行。在一些实施方式中,将导电表面与稀释的氢氟酸接触以帮助从该导电表面移除污染物的步骤是在移除设置在低k介电层的顶部上的硬质掩模之前执行。在一些实施方式中,移除设置在低k介电层的顶部上的硬质掩模的步骤是在向导电表面施用远程氢等离子体以形成导电表面的暴露部分之前执行。在一些实施方式中,稀释的氢氟酸是100到1000:1的DHF溶液。在一些实施方式中,方法包括以下步骤:在通孔中沉积第一类型的第一金属。在实施方式中,第一类型的第一金属是钌、钨、钴、铝、或上述项目的组合中的一者。在实施方式中,方法包括以下步骤:形成与通孔连通的沟槽。在实施方式中,方法包括以下步骤:在沟槽内及在导电表面的暴露部分的顶部上沉积阻挡层。在实施方式中,方法包括以下步骤:将衬垫层沉积在阻挡层的顶部上。在实施方式中,方法包括以下步骤:用与第一类型的第一金属不同的第二金属填充沟槽。在实施方式中,方法包括以下步骤:将盖顶层添加在第二金属的顶部上。
现参照图5,在一些实施方式中,本公开内容包括形成互连结构的方法500,该方法包括以下步骤:在方块502处,在包括设置在基板上的硬质掩模及介电层的膜堆叠中形成通孔及沟槽以暴露导电表面。方块504处的方法500包括以下步骤:将导电表面与稀释的氢氟酸接触。方块506处的方法500包括以下步骤:移除硬质掩模。方块508处的方法500包括以下步骤:向导电表面施加远程等离子体以形成导电表面的暴露部分。方块510处的方法500包括以下步骤:在通孔中沉积第一类型的第一金属。方块512处的方法500包括以下步骤:在第一金属及沟槽的暴露表面上沉积阻挡层。方块514处的方法500包括以下步骤:在阻挡层上沉积衬垫层。方块516处的方法500包括以下步骤:用与第一金属不同的第二金属填充沟槽。在实施方式中,将导电表面与稀释的氢氟酸接触的步骤是在移除硬质掩模之前进行。在实施方式中,将导电表面与稀释的氢氟酸接触的步骤是在移除硬质掩模之前进行,其中移除硬质掩模的步骤是在向导电表面施加远程等离子体以形成导电表面的暴露部分之前进行。在实施方式中,第一类型的第一金属是钌、钨、钴、铝、或上述项目的组合中的一者。在实施方式中,阻挡层包括TiN或TaN。在实施方式中,衬垫层包括钴。在实施方式中,第二金属是铜。在实施方式中,盖顶层设置在第二金属的顶部上。
在实施方式中,本公开内容包括一种形成互连结构的方法,该方法依序包括以下步骤:(1)蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过该低k介电层的通孔及暴露导电表面;(2)将该导电表面与稀释的氢氟酸接触以从该导电表面移除污染物;(3)例如通过湿蚀刻,来移除设置在该低k介电层的顶部上的该硬质掩模;及(4)向该导电表面施用远程氢等离子体以形成该导电表面的暴露部分。
虽然上文是针对本公开内容的实施方式,但也可以设计本公开内容的其他及另外的实施方式而不脱离本公开内容的基本范围。
Claims (20)
1.一种形成互连结构的方法,包括以下步骤:
蚀刻穿过设置在低k介电层的顶部上的硬质掩模,以形成穿过所述低k介电层的通孔及暴露导电表面;
将所述导电表面与稀释的氢氟酸接触以从所述导电表面移除污染物;
移除设置在所述低k介电层的顶部上的所述硬质掩模;和
向所述导电表面施用远程氢等离子体以形成所述导电表面的暴露部分。
2.如权利要求1所述的方法,其中将所述导电表面与稀释的氢氟酸接触以从所述导电表面移除污染物的步骤是在移除设置在所述低k介电层的顶部上的所述硬质掩模之前执行。
3.如权利要求1或2中的任一者所述的方法,其中移除设置在所述低k介电层的顶部上的所述硬质掩模的步骤是在向所述导电表面施用远程氢等离子体以形成所述导电表面的暴露部分之前执行。
4.如权利要求1或2中的任一者所述的方法,其中所述稀释的氢氟酸是100到1000:1的DHF溶液。
5.如权利要求1或2中的任一者所述的方法,在所述通孔中沉积第一类型的第一金属。
6.如权利要求5所述的方法,其中第一类型的所述第一金属是钌、钨、钴、铝、或上述项目的组合中的一者。
7.如权利要求5所述的方法,进一步包括以下步骤:形成与所述通孔连通的沟槽。
8.如权利要求7所述的方法,进一步包括以下步骤:在所述沟槽内及在所述导电表面的所述暴露部分的顶部上沉积阻挡层。
9.如权利要求8所述的方法,进一步包括以下步骤:在所述阻挡层的顶部上沉积衬垫层。
10.如权利要求9所述的方法,进一步包括以下步骤:用与第一类型的所述第一金属不同的第二金属填充沟槽。
11.如权利要求10所述的方法,进一步包括以下步骤:在所述第二金属的顶部上添加盖顶层。
12.一种形成互连结构的方法,包括以下步骤:
在包括设置在基板上的硬质掩模及介电层的膜堆叠中形成通孔及沟槽以暴露导电表面;
将所述导电表面与稀释的氢氟酸接触;
移除所述硬质掩模;
向所述导电表面施用远程等离子体以形成所述导电表面的暴露部分;
在所述通孔中沉积第一类型的第一金属;
在所述第一金属及所述沟槽的暴露表面上沉积阻挡层;
在所述阻挡层上沉积衬垫层;和
用与所述第一金属不同的第二金属填充所述沟槽。
13.如权利要求12所述的方法,其中将所述导电表面与稀释的氢氟酸接触的步骤是在移除所述硬质掩模之前进行。
14.如权利要求12或13中的任一者所述的方法,其中将所述导电表面与稀释的氢氟酸接触的步骤是在移除所述硬质掩模之前进行,且其中移除所述硬质掩模的步骤是在向所述导电表面施加远程等离子体以形成所述导电表面的暴露部分之前进行。
15.如权利要求12或13中的任一者所述的方法,其中第一类型的所述第一金属是钌、钨、钴、铝、或上述项目的组合中的一者。
16.如权利要求12或13中的任一者所述的方法,其中所述阻挡层包括TiN或TaN。
17.如权利要求12或13中的任一者所述的方法,其中所述衬垫层包括钴。
18.如权利要求12或13中的任一者所述的方法,其中所述第二金属是铜。
19.如权利要求12或13中的任一者所述的方法,其中将盖顶层设置在所述第二金属的顶部上。
20.一种非暂时性计算机可读介质,具有存储在其上的指令,所述指令在被执行时造成执行形成互连结构的方法,所述方法如前述权利要求中的任一者所述。
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