CN114267758B - Light-emitting diode epitaxial wafer and preparation method thereof - Google Patents
Light-emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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Abstract
The application discloses a light-emitting diode epitaxial wafer and a preparation method thereof, wherein a first sub-layer for promoting the growth of a three-dimensional nucleation layer is arranged between a substrate and the three-dimensional nucleation layer, in the growth process of the three-dimensional nucleation layer, gaN crystal nuclei preferentially grow on microscopic holes, and because GaN preferentially grows along the GaN crystal nuclei during growth, the GaN crystal nuclei are equivalent to providing a vertical initial growth angle for the three-dimensional nucleation layer, and a three-dimensional growth structure is easier to form, so that the capability of combining the lateral epitaxy with the three-dimensional structure can be enhanced, dislocation is eliminated, and the crystal quality of the epitaxial wafer is further improved.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
Background
An AlN buffer layer is generally arranged on a substrate in the existing light-emitting diode epitaxial wafer, and the AlN buffer layer which is mature in industrial production at present is an AlN film with a certain thickness prepared by physical magnetron sputtering (PVD for short), so that the AlN buffer layer has the characteristics of easy formation of large-scale industrial mass production and higher crystal quality; but the AlN buffer layer prepared by physical magnetron sputtering has poor relaxation, a three-dimensional mode is difficult to form by growing the GaN layer, the lateral epitaxy is combined with a poor three-dimensional effect, dislocation is not sufficiently eliminated, and the stress release effect between the AlN buffer layer and the subsequent GaN layer cannot be better achieved, so that the crystal quality of each subsequent epitaxial layer can be reduced.
Therefore, how to promote three-dimensional growth of GaN on an AlN buffer layer and eliminate dislocation release stress, thereby improving crystal quality becomes a problem in the prior art that needs improvement.
Disclosure of Invention
The application aims to provide a light-emitting diode epitaxial wafer and a preparation method thereof, which are used for solving the problems of promoting three-dimensional growth of GaN on an AlN buffer layer, eliminating dislocation release stress and further improving crystal quality.
The application adopts the scheme for solving the technical problems that:
in a first aspect, the application provides a light-emitting diode epitaxial wafer, which comprises a substrate and a three-dimensional nucleation layer arranged on the substrate, wherein a first sub-layer is arranged between the substrate and the three-dimensional nucleation layer, and holes for promoting three-dimensional growth of the three-dimensional nucleation layer are arranged on the first sub-layer.
In some embodiments of the present application, the first sub-layer is In y Ga 1-y And the N layer, y is more than 0 and less than 0.5, and holes for separating In atoms are formed In one side of the first sub-layer, which is close to the three-dimensional nucleation layer.
In some embodiments of the application, a second sub-layer is disposed between the substrate and the first sub-layer, and a crack is disposed on the second sub-layer, the crack configured to relieve stress between the substrate and the three-dimensional nucleation layer.
In some embodiments of the present application, the second sub-layer is a low temperature AlN layer and has a thickness of
In some embodiments of the present application, a third sub-layer is further disposed between the second sub-layer and the first sub-layer, where the third sub-layer is Al x Ga 1-x And N layers, wherein 0 < x < 1, and the Al component of the third sub-layer gradually decreases from the second sub-layer to the first sub-layer.
In some embodiments of the application, a buffer layer is further provided between the substrate and the second sub-layer.
In some embodiments of the present application, a plurality of stacked units are disposed between a substrate and the three-dimensional nucleation layer, and each of the stacked units includes the second sub-layer, the third sub-layer, and the first sub-layer stacked in this order along a direction of the substrate toward the three-dimensional nucleation layer.
In some embodiments of the present application, the buffer layer is made of an AlN material and the three-dimensional nucleation layer is made of a GaN material.
In a second aspect, the application also provides a preparation method of the light-emitting diode epitaxial wafer,
comprises a substrate and a three-dimensional nucleation layer arranged on the substrate, wherein a first sub-layer is arranged between the substrate and the three-dimensional nucleation layer, and the preparation step of the first sub-layer further comprises
And preparing holes for promoting the three-dimensional growth of the three-dimensional nucleation layer on the first sub-layer.
In some embodiments of the present application, in the step of preparing the first sub-layer, the composition of the first sub-layer includes In y Ga 1-y N, y is more than 0 and less than 0.5, and the thickness isThe growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere; and the growth temperature of the grown three-dimensional nucleation layer is higher than the growth temperature of the first sub-layer.
In some embodiments of the present application, the method further comprises sequentially preparing a second sub-layer and a third sub-layer on the substrate, wherein in the step of preparing the second sub-layer, the composition of the second sub-layer comprises AlN and has a thickness ofThe growth temperature is 500-880 ℃, the growth pressure is 50-150 Torr, and the growth atmosphere is pure nitrogen atmosphere; in the step of preparing the third sub-layer, the composition of the third sub-layer is Al x Ga 1-x An N layer, and 0 < x < 1, along the second Al componentThe sub-layer gradually decreases to the first sub-layer with a thickness of +.>The growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere.
According to the LED epitaxial wafer and the preparation method thereof, the first sub-layer for promoting the growth of the three-dimensional nucleation layer is arranged between the substrate and the three-dimensional nucleation layer, in the growth process of the three-dimensional nucleation layer, the GaN crystal nucleus preferentially grows on the holes, and as GaN preferentially grows along the GaN crystal nucleus during growth, the GaN crystal nucleus is equivalent to providing a vertical initial growth angle for the three-dimensional nucleation layer, so that a three-dimensional growth structure is easier to form, the capability of combining the lateral epitaxy with the three-dimensional structure can be enhanced, dislocation is eliminated, and the crystal quality of the epitaxial wafer is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a diagram of an epitaxial wafer structure of the present application;
fig. 2 is a step diagram of the epitaxial wafer manufacturing method of the present application.
Element symbol description:
1-substrate, 2-buffer layer, 3-insertion layer, 4-three-dimensional nucleation layer, 5-u type GaN layer, 6-n type GaN layer, 7-multiple quantum well layer, 8-low temperature P-type layer, 9-electron blocking layer, 10-high temperature P-type layer, 11-P type contact layer, 31-second sub-layer, 32-third sub-layer, 33-first sub-layer.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and fully described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or the inclusion of a number of indicated features. Thus, a feature defining "a first" or "a second" may include, either explicitly or implicitly, one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more unless explicitly defined otherwise.
In the application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as exemplary in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles disclosed herein.
The conventional epitaxial wafer of the light-emitting diode comprises a patterned substrate 1, an AlN buffer layer 2, a three-dimensional nucleation layer 4, a u-type GaN layer 5, an n-type GaN layer 6, a multi-quantum well layer 7, a low-temperature p-type layer 8, an electron blocking layer 9, a high-temperature p-type layer 10 and a p-type contact layer 11. The AlN buffer layer 2 is prepared by physical magnetron sputtering, and the prepared AlN buffer layer 2 has good compactness, few defects and higher quality, but the AlN buffer layer 2 has poor stress release capability and relaxation; the three-dimensional nucleation layer 4 prepared later is difficult to form a three-dimensional growth mode, so that the lateral epitaxy is poor in merging three-dimensional effect, dislocation is not sufficiently eliminated, the stress release effect cannot be better achieved, and the crystal quality of each layer of the subsequent epitaxy is affected.
Example 1: referring to fig. 1, the main body of the embodiment is a light emitting diode epitaxial wafer, which comprises a substrate 1 and a laminated structure arranged on the substrate 1, wherein the laminated structure at least comprises a buffer layer 2, an insertion layer 3 and a three-dimensional nucleation layer 4 which are arranged from bottom to top; the interposed layer 3 comprises at least a second sub-layer 31, provided on the buffer layer 2 and provided with microcracks for releasing stresses; the first sublayer 33 is provided with microscopic holes for promoting the three-dimensional growth of said three-dimensional nucleation layer 4. The insertion layer 3 comprises a second sub-layer 31 arranged on the buffer layer 2, and the microcrack structure on the second sub-layer 31 has a good stress release effect, so that the quality of the epitaxial layer which grows subsequently can be improved by releasing the internal stress; meanwhile, the insert layer 3 further comprises a first sub-layer 33 for growing the three-dimensional nucleation layer 4, in the growth process of the three-dimensional nucleation layer 4, gaN crystal nuclei preferentially grow on microscopic holes, and since GaN can preferentially grow along the GaN crystal nuclei during growth, the GaN crystal nuclei are equivalent to providing a vertical initial growth angle for the three-dimensional nucleation layer 4, so that a three-dimensional growth structure is easier to form, the three-dimensional growth structure can strengthen the capability of combining three dimensions by lateral epitaxy, dislocation is eliminated, and the crystal quality of an epitaxial wafer is further improved.
In some embodiments of the present application, the second sub-layer 31 is a low temperature AlN layer and has a thickness ofBecause AIN lattice is easy to relax under low temperature condition, low temperature AlN layer with small thickness is prepared under low temperature condition and is easy to be formed by tensile stress stretch crackingA microcrack structure; in the embodiment, the number of microcracks is multiple, the crack structure is similar to that of a bridge and other building structures, the stability of the whole structure can be enhanced, and an AlN thin layer with microcracks is clamped between the three-dimensional nucleation layer 4 and the substrate 1, so that the stress releasing effect is good. More specifically, the thickness of the second sub-layer 31 is +.>
In some embodiments of the present application, the first sub-layer 33 is In y Ga 1-y And the N layer, y is more than 0 and less than 0.5, and microscopic holes for separating In atoms are formed In one side of the first sub-layer 33, which is close to the three-dimensional nucleation layer 4. The temperature of the first sub-layer 33 needs to be raised In the process of transition to the three-dimensional nucleation layer 4, the growth temperature of the first sub-layer 33 is low, the chemical bond of InGaN is not very firm, in atoms can easily form microscopic particles from the InGaN material to be separated out In the process of raising the temperature, microscopic holes are left, gaN crystal nuclei can be captured by utilizing the microscopic holes, and a three-dimensional mode can be easily formed by growing GaN on the GaN crystal nuclei.
In some embodiments of the present application, a third sub-layer 32 is further disposed between the second sub-layer 31 and the first sub-layer 33, and the third sub-layer 32 is Al x Ga 1-x N layers, and 0 < x < 1, wherein Al composition gradually decreases along the second sub-layer 31 to the first sub-layer 33. In some embodiments of the present application, the buffer layer 2 is made of an AlN material, and the three-dimensional nucleation layer 4 is made of a GaN material. The gradual decrease of the Al composition in the third sub-layer 32 is equivalent to providing an AlN-AlGaN-GaN gradual change structure, and the third sub-layer 32 is substantially an AlN composition near the second sub-layer 31 and is substantially a GaN composition near the first sub-layer 33, so that a smooth transition from an AlN material to a GaN material can be performed, and lattice mismatch between the AlN material and the GaN material can be reduced.
In some embodiments of the present application, the number of the insertion layers 3 is plural, and the plural insertion layers 3 are stacked between the buffer layer 2 and the three-dimensional nucleation layer 4. There may be only one or more intervening layers 3, more particularly 2-10 intervening layers 3, forming a superlattice structure.
Example 2: the embodiment also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises a substrate 1 and a laminated structure arranged on the substrate 1, wherein when the laminated structure is prepared, at least a buffer layer 2, an insertion layer 3 and a three-dimensional nucleation layer 4 are sequentially prepared on the substrate 1; in the step of preparing the interposer layer 3, further comprising preparing a second sub-layer 31 on the buffer layer 2, and providing microcracks for releasing stress on the second sub-layer 31; a first sub-layer 33 is prepared on the second sub-layer 31, and microscopic holes for promoting the three-dimensional growth of the three-dimensional nucleation layer 4 are prepared on the first sub-layer 33.
In some embodiments of the present application, in the step of preparing the second sub-layer 31, the composition of the second sub-layer 31 includes AlN and has a thickness ofThe growth temperature is 500-880 ℃, the growth pressure is 50-150 Torr, and the growth atmosphere is pure nitrogen atmosphere. The low temperature growth of thinner AlN is easy to form micro-crack structure.
In some embodiments of the present application, in the step of preparing the first sub-layer 33, the composition of the first sub-layer 33 includes In y Ga 1-y N, y is more than 0 and less than 0.5, and the thickness isThe growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere. And the growth temperature of the grown three-dimensional nucleation layer 4 is higher than that of the first sub-layer 33. In atoms of the first sub-layer 33 are separated out In the heating process to form microscopic holes, so that the three-dimensional nucleation layer 4 can be grown In a three-dimensional manner.
In some embodiments of the present application, after preparing the second sub-layer 31, further comprising preparing a third sub-layer 32 on the second sub-layer 31, preparing a first sub-layer 33 after the third sub-layer 32; and the composition of the third sub-layer 32 is Al x Ga 1-x N layer, and 0 < x < 1, al component gradually decreases along the second sub-layer 31 to the first sub-layer 33, and has a thickness ofThe growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere. The third sub-layer 32 can reduce lattice mismatch between the AlN material and the GaN material.
Example 3: the embodiment also provides a light emitting diode epitaxial wafer, which comprises a patterned substrate 1, an AlN buffer layer 2, an insertion layer 3, a three-dimensional nucleation layer 4, a u-type GaN layer 5, an n-type GaN layer 6, a multi-quantum well layer 7, a low-temperature p-type layer 8, an electron blocking layer 9, a high-temperature p-type layer 10 and a p-type contact layer 11. Wherein the interposer 3 comprises a first sub-layer, a second sub-layer and a third sub-layer; the first sub-layer is a low temperature AlN layer, the second sub-layer is an AlGaN third sub-layer 32, and the third sub-layer is an InGaN mask layer. Wherein the patterned substrate 1 can be patterned sapphire substrate 1, patterned SiO 2 A substrate 1 and a patterned SiC substrate 1.
Example 4: referring to fig. 2, the embodiment also provides a method for preparing an led epitaxial wafer, which includes the following steps: s1: providing a patterned substrate 1; s2: sputtering and depositing an AlN film on the substrate 1 as an AlN buffer layer 2; s3: growing an insertion layer 3 on the AlN buffer layer 2 by using an MOCVD system, wherein the insertion layer 3 comprises a second sub-layer 31, a third sub-layer 32 and a first sub-layer 33; s4: growing a three-dimensional nucleation layer 4 on the insertion layer 3; s5: growing a u-type GaN layer 5 on the three-dimensional nucleation layer 4; s6: growing an n-type GaN layer 6 on the u-type GaN layer 5; s7: growing multiple quantum well layers 7 on the n-type GaN layer 6 includes multiple In x Ga 1-x An N quantum well layer and a plurality of GaN quantum barrier layers; s8: growing a low-temperature p-type layer 8 on the multiple quantum well layer 7; s9: growing an electron blocking layer 9 on the low temperature p-type layer 8; s10: growing a high temperature p-type layer 10 on the electron blocking layer 9; s11: a p-type contact layer 11 is grown on the high temperature p-type layer 10.
Example 5: the embodiment also discloses a specific preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
step one, a patterned substrate 1 is provided. The substrate 1 may be a sapphire substrate 1, siO 2 Substrate 1, siC substrate 1, the present embodiment uses patterned SiO 2 A substrate 1.
And secondly, sputtering and depositing an AlN film on the PSS pattern by using PVD equipment to serve as an AlN buffer layer 2. Specifically, the substrate 1 and the tray are placed in a PVD (physical vapor deposition) reaction chamber, and the AlN buffer layer 2 is deposited by magnetron sputtering, where the sputtering power may be 3000W to 5000W. The growth pressure of the AlN buffer layer 2 may be 2mTorr-10mTorr, and the growth temperature of the AlN buffer layer 2 may be 400-800 ℃. The thickness of AlN buffer layer 2 may be controlled by the time of sputtering. In the embodiment of the present disclosure, the thickness of the AlN buffer layer 2 is 15nm.
And thirdly, growing an insertion layer 3 on the AlN buffer layer 2 by utilizing an MOCVD system, wherein the insertion layer is a low-temperature AlN second sub-layer, an AlGaN third sub-layer with gradually changed Al components and an InGaN first sub-layer in sequence. In an embodiment of the disclosure, the second sub-layer AlN has a thickness ofThe growth temperature is 820 ℃, the growth pressure is 100Torr, and the growth atmosphere is pure nitrogen; third sublayer Al x Ga 1-x N is +.>The growth temperature is 950 ℃, the growth pressure is 100Torr, and the growth atmosphere is pure nitrogen atmosphere; first sub-layer In y Ga 1-y N, y=0.3, thickness +.>The growth temperature was 800℃and the growth pressure was 200Torr, and the growth atmosphere was a pure nitrogen atmosphere.
And step four, growing a three-dimensional nucleation layer 4 on the insertion layer 3. Specifically, the substrate 1 may be placed in a MOCVD (Metal-organic chemical vapor deposition) reaction chamber, and the three-dimensional nucleation layer 4 may be grown under a mixed atmosphere of nitrogen, hydrogen and ammonia. The growth pressure of the three-dimensional nucleation layer 4 may be 300Torr to 500Torr, and the growth temperature of the three-dimensional nucleation layer 4 may be 950℃to 1080 ℃. The thickness of the three-dimensional nucleation layer 4 may be 0.3 μm to 0.5 μm, and in this embodiment, the thickness of the three-dimensional nucleation layer 4 is 0.4 μm, for example.
And step four, growing a u-type GaN layer 5 on the three-dimensional nucleation layer 4. Specifically, a u-type GaN layer 5 is grown on the three-dimensional nucleation layer 4. The thickness of the u-type GaN layer 5 may be 0.5 μm to 3 μm, and in this embodiment, the thickness of the u-type GaN layer 5 is 1 μm. The growth temperature of the u-type GaN layer 5 may be 1000-1100 deg.C and the growth pressure may be 100-300 Torr. By way of example, in the presently disclosed embodiment, the growth temperature of the u-type GaN layer 5 is 1050 degrees Celsius and the growth pressure is 200Torr.
And step five, growing an n-type GaN layer 6 on the u-type GaN layer 5. The thickness of the n-type GaN layer 6 may be, for example, 0.5 μm-3 μm. In the embodiment of the present disclosure, the thickness of the n-type GaN layer 6 is 2 μm. The doping concentration of Si in the n-type GaN layer 6 may be 10 18 cm -3 -10 19 cm -3 . The growth temperature of the n-type GaN layer 6 may be 1000-1100 deg.C and the growth pressure may be 100-300 Torr. In the embodiment of the present disclosure, the growth temperature of the n-type GaN layer 6 is 1050 ℃, and the growth pressure is 200Torr.
Step six, growing multiple quantum well layers 7 including multiple In on the n-type GaN layer 6 x Ga 1-x An N quantum well layer and a plurality of GaN quantum barrier layers. Specifically, the multiple quantum well layer 7 may include In of 8 to 15 periods alternately laminated x Ga 1-x An N quantum well layer and a GaN quantum barrier layer, and each adjacent In x Ga 1-x At least one composite structure is arranged between the N quantum well layer and the GaN quantum barrier layer. In the presently disclosed embodiments, in x Ga 1-x The growth temperature of the N quantum well layer may be 700-830 ℃ and the growth pressure may be 100Torr-300Torr. In (In) x Ga 1-x The N quantum well layer may be grown under a nitrogen atmosphere. In embodiments of the present disclosure, the growth temperature of the GaN quantum barrier layer may be 800-960 ℃, and the growth pressure may be 100Torr-300Torr. The GaN quantum barrier layer may be grown under a mixed atmosphere of nitrogen and hydrogen. Alternatively, in x Ga 1-x The thickness of the N quantum well layer can be 2nm-5nm, and the thickness of the GaN quantum barrier layer can be 8nm-20nm.
And step seven, growing a low-temperature p-type layer 8 on the quantum well layer. A low temperature p-type layer 8 is grown on the multiple quantum well layer 7. Illustratively, the low temperature p-type layer 8 is p-type Al z Ga 1-z N layer, 0.1<z<0.3. Can be used forAlternatively, the low temperature p-type layer 8 may have a thickness of 20nm to 100nm. In the presently disclosed embodiment, the low temperature p-type layer 8 has a thickness of 50nm. The doping concentration of Mg in the low temperature p-type layer 8 may be 5×10 19 cm -3 -10 21 cm -3 . The growth temperature of the low temperature p-type layer 8 may be 700-800 deg.c and the growth pressure may be 200-500 Torr. In the presently disclosed embodiment, the low temperature p-type layer 8 is grown at 750 ℃ and at a pressure of 200Torr.
And step eight, growing an electron blocking layer 9 on the low-temperature p-type layer 8. An electron blocking layer 9 is grown on the low temperature p-type layer 8. Illustratively, the electron blocking layer 9 is p-type Al m Ga 1-m N electron blocking layer 9, 0.2<m<0.5. Alternatively, the thickness of the electron blocking layer 9 may be 20nm to 100nm. In the presently disclosed embodiment, the thickness of the electron blocking layer 9 is 50nm. The growth temperature of the electron blocking layer 9 may be 800℃to 1000℃and the growth pressure may be 100Torr to 300Torr. In the embodiment of the present disclosure, the growth temperature of the electron blocking layer 9 is 750 ℃, and the growth pressure is 100Torr.
And step nine, growing a high-temperature p-type layer 10 on the electron blocking layer 9. A high temperature p-type layer 10 is grown on the electron blocking layer 9. Illustratively, the high temperature p-type layer 10 is a p-type GaN layer. Alternatively, the high temperature p-type layer 10 may have a thickness of 20nm to 200nm. In the presently disclosed embodiment, the high temperature p-type layer 10 has a thickness of 80nm. The growth temperature of the high temperature p-type layer 10 may be 800-1000 deg.c and the growth pressure may be 200-600 Torr. In the disclosed embodiment, the growth temperature of the high temperature p-type layer 10 is 950 ℃, and the growth pressure is 500Torr.
Step ten, a p-type contact layer 11 is grown on the high temperature p-type layer 10. A p-type contact layer 11 is grown on the high temperature p-type layer 10. The p-type contact layer 11 is illustratively a p-type GaN layer. Alternatively, the thickness of the p-type contact layer 11 may be 10nm to 50nm. In the presently disclosed embodiment, the thickness of the p-type contact layer 11 is 20nm. The growth temperature of the p-type contact layer 11 may be 850 ℃ to 1000 ℃ and the growth pressure may be 100Torr to 300Torr. In the embodiment of the present disclosure, the growth temperature of the p-type contact layer 11 is 850 ℃, and the growth pressure is 200Torr. The doping concentration of Mg in the p-type contact layer 11 may be 10 20 cm -3 -10 21 cm -3 . After the growth of the p-type contact layer 11 is completed, annealing treatment may be performed in a nitrogen atmosphere at 650-850 ℃ for 5-15 minutes, and then cooling to room temperature.
After the steps are finished, the epitaxial wafer can be subjected to subsequent processing so as to finish the manufacture of the epitaxial wafer. In particular implementations, embodiments of the present disclosure may employ high purity H 2 Or/and N 2 As a carrier gas, TEGa or TMGa as Ga source, TMIn as In source, siH 4 As n-type doping, TMAL is used as an aluminum source, cp 2 Mg acts as a p-type dopant.
The total thickness of the interposer 3 in this embodiment isThe first sublayer AlN of the insertion layer 3 has a thickness +.>The growth temperature is 500-880 ℃, the growth pressure is 50-150 Torr, and the growth atmosphere is pure nitrogen atmosphere. Insertion layer 3 second sublayer Al x Ga 1-x N (characterized by 0<X<1) Thickness of->The growth temperature is 600-1080 ℃, the growth pressure is 50-500 Torr, and the growth atmosphere is pure nitrogen atmosphere. Interposer 3 third sublayer In y Ga 1-y N (characterized in that 0 < y < 0.5) thickness is +.>The growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the portions of one embodiment that are not described in detail in the foregoing embodiments may be referred to in the foregoing detailed description of other embodiments, which are not described herein again.
While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing detailed disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements and adaptations of the application may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within the present disclosure, and therefore, such modifications, improvements, and adaptations are intended to be within the spirit and scope of the exemplary embodiments of the present disclosure.
Meanwhile, the present application uses specific words to describe embodiments of the present application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the application. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the application may be combined as suitable.
Similarly, it should be noted that in order to simplify the description of the present disclosure and thereby aid in understanding one or more inventive embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof. This method of disclosure, however, is not intended to imply that more features than are required by the subject application. Indeed, less than all of the features of a single embodiment disclosed above.
In some embodiments, numbers describing the components, number of attributes are used, it being understood that such numbers being used in the description of embodiments are modified in some examples by the modifier "about," approximately, "or" substantially. Unless otherwise indicated, "about," "approximately," or "substantially" indicate that the number allows for a 20% variation. Accordingly, in some embodiments, numerical parameters set forth in the specification and claims are approximations that may vary depending upon the desired properties sought to be obtained by the individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and employ a method for preserving the general number of digits. Although the numerical ranges and parameters set forth herein are approximations in some embodiments for use in determining the breadth of the range, in particular embodiments, the numerical values set forth herein are as precisely as possible.
Each patent, patent application publication, and other material, such as articles, books, specifications, publications, documents, etc., cited herein is hereby incorporated by reference in its entirety except for any application history file that is inconsistent or otherwise conflict with the present disclosure, which places the broadest scope of the claims in this application (whether presently or after it is attached to this application). It is noted that the description, definition, and/or use of the term in the appended claims controls the description, definition, and/or use of the term in this application if the description, definition, and/or use of the term in the appended claims does not conform to or conflict with the present disclosure.
The foregoing has outlined the detailed description of the embodiments of the present application, and the detailed description of the principles and embodiments of the present application is provided herein by way of example only to facilitate the understanding of the method and core concepts of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (6)
1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate and a three-dimensional nucleation layer arranged on the substrate, wherein a first sub-layer is arranged between the substrate and the three-dimensional nucleation layer, and holes for promoting the three-dimensional growth of the three-dimensional nucleation layer are arranged on the first sub-layer;
the first sub-layer is an InyGa1-yN layer, y is more than 0 and less than 0.5, and the hole formed by In atom precipitation is formed on one side of the first sub-layer, which is close to the three-dimensional nucleation layer;
a second sub-layer is arranged between the substrate and the first sub-layer, and a crack is arranged on the second sub-layer and used for releasing the stress between the substrate and the three-dimensional nucleation layer;
the second sub-layer is a low-temperature AlN layer and has the thickness of
2. The light-emitting diode epitaxial wafer of claim 1, wherein a third sub-layer is further provided between the second sub-layer and the first sub-layer, the third sub-layer is an AlxGa1-xN layer, and 0 < x < 1, wherein the Al composition of the third sub-layer gradually decreases along the second sub-layer to the first sub-layer.
3. The light emitting diode epitaxial wafer of claim 1, wherein a buffer layer is further disposed between the substrate and the second sub-layer.
4. The light-emitting diode epitaxial wafer according to claim 1, wherein a plurality of stacked units are provided between a substrate and the three-dimensional nucleation layer, each of the stacked units including the second sub-layer, the third sub-layer and the first sub-layer stacked in this order along a direction of the substrate toward the three-dimensional nucleation layer.
5. A preparation method of a light-emitting diode epitaxial wafer is characterized in that,
comprises a substrate and a three-dimensional nucleation layer arranged on the substrate, wherein a first sub-layer is arranged between the substrate and the three-dimensional nucleation layer, and the preparation step of the first sub-layer further comprises
Preparing holes for promoting the three-dimensional growth of the three-dimensional nucleation layer on the first sub-layer;
further comprises preparing a second sub-layer and a third sub-layer sequentially on the substrate, wherein in the step of preparing the second sub-layer, the component of the second sub-layer comprises AlN and has the thickness ofThe growth temperature is 500-880 ℃, the growth pressure is 50-150 Torr, and the growth atmosphere is pure nitrogen atmosphere; in the preparation ofIn the step of the third sub-layer, the composition of the third sub-layer is AlxGa1-xN layer, x is more than 0 and less than 1, al composition gradually decreases from the second sub-layer to the first sub-layer, and the thickness is thatThe growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere.
6. The method according to claim 5, wherein in the step of preparing the first sub-layer, the composition of the first sub-layer comprises InyGa1-yN,0 < y < 0.5, and the thickness isThe growth temperature is 600-1080 ℃, the growth pressure is 200-500 Torr, and the growth atmosphere is pure nitrogen atmosphere; and the growth temperature of the grown three-dimensional nucleation layer is higher than the growth temperature of the first sub-layer.
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