CN114267635A

CN114267635A - Array substrate, manufacturing method and display panel

Info

Publication number: CN114267635A
Application number: CN202111561973.9A
Authority: CN
Inventors: 蒲洋; 许哲豪; 康报虹
Original assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Priority date: 2021-12-20
Filing date: 2021-12-20
Publication date: 2022-04-01

Abstract

The application is suitable for the technical field of display, and provides an array substrate, a manufacturing method and a display panel, wherein the array substrate comprises: the grid electrode comprises a first transparent conductive block arranged on the substrate and a first metal block arranged on the first transparent conductive block, the pixel electrode comprises a second transparent conductive block arranged on the substrate, the first transparent conductive block and the second transparent conductive block are on the same layer, a first through hole penetrating to the pixel electrode is arranged on the grid electrode insulating layer, and the drain electrode is connected to the pixel electrode through the first through hole. The array substrate only needs three photomask processes, the number of the processes is small, the number of the required photomasks is small, the manufacturing cost can be obviously reduced, and the productivity is improved.

Description

Array substrate, manufacturing method and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel.

Background

With the development of the electro-optical Display technology and the semiconductor manufacturing technology, a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has become the mainstream of the Display device due to its advantages of lightness, thinness, energy saving, high Display quality, and mature and stable manufacturing process. The TFT-LCD mainly includes an Array (Array) substrate, a Color Filter (CF) substrate, and a Liquid Crystal (LC) layer disposed between the Array substrate and the Color Filter substrate.

At present, in the TFT manufacturing process of the array substrate, at least 4 photolithography processes are required, and four mask plates are correspondingly required for 4 processes. The yellow light process is often a more complex and costly process in the TFT process, and reducing one process and mask plate means reducing product cost and improving productivity, which is beneficial to improving product competitiveness.

Disclosure of Invention

An embodiment of the present invention provides an array substrate, which aims to solve the technical problems of a large number of yellow light processes and a high process cost in the conventional array substrate.

The embodiment of the present application is implemented as follows, an array substrate, including:

a substrate base plate;

the grid electrode and the pixel electrode are arranged on the substrate base plate, the grid electrode comprises a first transparent conductive block arranged on the substrate base plate and a first metal block arranged on the first transparent conductive block, and the pixel electrode comprises a second transparent conductive block arranged on the substrate base plate; the first transparent conductive block and the second transparent conductive block are on the same layer;

the grid insulation layer is arranged on the grid and the pixel electrode, and a first through hole penetrating to the pixel electrode is formed in the grid insulation layer;

an active layer disposed on the gate insulating layer; and

and the drain electrode is connected to the pixel electrode through the first via hole.

In one embodiment, the array substrate further includes:

the grid line is arranged on the substrate base plate and comprises a third transparent conductive block arranged on the substrate base plate and a third metal block arranged on the third transparent conductive block; the third transparent conductive block is connected with the first transparent conductive block at the same layer, and the third metal block is connected with the first metal block at the same layer.

In one embodiment, the array substrate further includes:

the common electrode wire is arranged on the substrate base plate and comprises a fourth transparent conductive block arranged on the substrate base plate and a fourth metal block arranged on the fourth transparent conductive block, the fourth transparent conductive block and the first transparent conductive block are on the same layer, and the fourth metal block and the first metal block are on the same layer; and

and the storage capacitor electrode is arranged on the grid insulating layer and is on the same layer as the source electrode and the drain electrode, a second through hole penetrating to the common electrode wire is also arranged on the grid insulating layer, the storage capacitor electrode is connected with the common electrode wire through the second through hole, and the storage capacitor electrode is partially overlapped with the pixel electrode.

In one embodiment, an active material layer is disposed between the storage capacitor electrode and the gate insulating layer, and the active material layer is the same as the active layer.

In one embodiment, the first via hole and the second via hole are respectively located at two opposite sides of the pixel electrode, and the storage capacitor electrode overlaps with the other side edge of the pixel electrode except for one side edge for connecting with the drain electrode.

In one embodiment, the array substrate further includes:

and the data line is connected with the source electrode on the same layer, an active material layer is arranged between the data line and the grid electrode insulating layer, and the active material layer is connected with the active layer on the same layer.

Another objective of the present application is to provide a method for manufacturing an array substrate, including:

forming a grid and a pixel electrode on a substrate through a first photomask, wherein the grid comprises a first transparent conductive block arranged on the substrate and a first metal block arranged on the first transparent conductive block, and the pixel electrode comprises a second transparent conductive block arranged on the substrate;

depositing a grid insulating material layer and an active material layer on the grid and the pixel electrode, and forming a first through hole communicated to the pixel electrode through a second photomask manufacturing process;

depositing a second metal layer on the active material layer, processing the second metal layer through a third photomask process to form a source electrode and a drain electrode, and processing the active material layer to form an active layer; the drain electrode is connected with the pixel electrode through the first via hole.

In one embodiment, in the first photo-masking process, a gate line is further formed on the substrate base plate, and the gate line includes a third transparent conductive block disposed on the substrate base plate and a third metal block disposed on the third transparent conductive block; the third transparent conductive block is connected with the first transparent conductive block at the same layer, and the third metal block is connected with the first metal block at the same layer; and/or

In the third photo-masking process, the second metal layer is further processed to form a data line, and the active material layer is processed to form a portion located under the data line.

In one embodiment, in the first photo-masking process, a common electrode line is further formed on the substrate base plate; in the second photomask manufacturing process, a second through hole penetrating to the common electrode line is further formed on the insulating material layer and the active material layer; in the third photomask manufacturing process, the second metal layer is further processed to form a storage capacitor electrode, and the storage capacitor electrode is connected with the common electrode line through the second via hole.

Another objective of the present application is to provide a display panel, which includes the array substrate, the color filter substrate, and a liquid crystal layer disposed between the color filter substrate and the array substrate according to the embodiments.

The array substrate, the manufacturing method and the display panel provided by the embodiment of the application have the beneficial effects that:

according to the array substrate and the manufacturing method thereof, the grid electrode and the pixel electrode are arranged on the substrate and can be formed through one photomask process, the active layer, the source electrode and the drain electrode can be formed through one photomask process, the first through hole in the grid insulating layer for connecting the drain electrode and the pixel electrode is formed through one photomask process, the manufacturing process only needs three photomask processes, the number of the processes is small, the number of required photomasks is small, therefore, the manufacturing cost of the array substrate can be obviously reduced, and the productivity is improved. The display panel with the array substrate has low manufacturing cost and short manufacturing period, and is beneficial to improving the productivity.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic plan view of an array substrate provided in an embodiment of the present application;

FIG. 2 is a cross-sectional view of the array substrate of FIG. 1 taken along line A-A;

fig. 3 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

FIG. 4 is a flow chart illustrating a substep of step S1 of the method of manufacture illustrated in FIG. 3;

FIG. 5 is a schematic diagram of the structure formed in step S11 of the method of FIG. 3;

FIG. 6 is a schematic diagram of the structure formed in step S12 of the method of FIG. 3;

FIG. 7 is a schematic diagram of the structure formed in step S13 of the method of manufacture of FIG. 3;

FIG. 8 is a schematic diagram of the structure formed in step S14 of the method of manufacture of FIG. 3;

FIG. 9 is a schematic diagram of the structure formed in step S15 of the method of manufacture of FIG. 3;

FIG. 10 is a schematic diagram of the structure formed in step S16 of the method of manufacture of FIG. 3;

FIG. 11 is a flow chart illustrating a substep of step S2 of the method of manufacture illustrated in FIG. 3;

FIG. 12 is a schematic diagram of the structure formed in step S21 of the method of manufacture of FIG. 3;

FIG. 13 is a schematic diagram of the structure formed in step S22 of the method of manufacture of FIG. 3;

FIG. 14 is a schematic diagram of the structure formed in step S23 of the method of manufacture of FIG. 3;

FIG. 15 is a schematic diagram of the structure formed in step S24 of the method of manufacture of FIG. 3;

FIG. 16 is a flow chart illustrating a substep of step S3 of the method of manufacture illustrated in FIG. 3;

FIG. 17 is a schematic diagram of the structure formed in step S31 of the method of manufacture of FIG. 3;

FIG. 18 is a schematic diagram of the structure formed in step S32 of the method of manufacture of FIG. 3;

FIG. 19 is a schematic diagram of the structure formed in step S33 of the method of manufacture of FIG. 3;

FIG. 20 is a schematic diagram of the structure formed in step S34 of the method of manufacture of FIG. 3;

FIG. 21 is a schematic diagram of the structure formed in step S35 of the method of manufacture of FIG. 3;

FIG. 22 is a schematic diagram of the structure formed in step S36 of the method of manufacture of FIG. 3;

FIG. 23 is a schematic diagram of the structure formed in step S4 of the method of manufacture of FIG. 3;

fig. 24 is a schematic structural diagram of a display panel according to an embodiment of the present application.

The designations in the figures mean:

400-a display panel, 300-a color film substrate and 200-a liquid crystal layer;

100-an array substrate;

10-a thin film transistor;

11-a substrate base plate;

12-gate, 120-first metal layer, 121-first metal block, 122-second metal block, 123-third metal block, 124-fourth metal block;

13-a gate line;

14-common electrode lines;

15-pixel electrode, 150-transparent conductive layer, 151-first transparent conductive block, 152-second transparent conductive block, 153-third transparent conductive block, 154-fourth transparent conductive block;

16-a gate insulating layer, 160-a gate insulating material layer, 161-a first via, 162-a second via;

17-active layer, 171-semiconductor layer, 172-ohmic contact layer, 170-active material layer, 1701-semiconductor material layer, 1702-doped layer;

18-source, 180-second metal layer, 181-source drain metal block;

19-a drain electrode;

20-storage capacitor electrodes;

21-a data line;

22-alignment layer;

31-a first photoresist pattern, 311-a first thin region, 312-a first thick region;

32-second photoresist pattern;

40-a third photoresist pattern;

51-fourth photoresist pattern, 511-second thin region, 512-second thick region;

52-fifth resist pattern, 521-pattern block.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to or disposed on the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the patent. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.

Referring to fig. 3, a method for fabricating an array substrate is first provided in the present embodiment.

It should be noted that, referring to fig. 1 and fig. 2, the basic structure of the array substrate 100 generally includes: the thin film transistor 10 comprises a gate line 13, a data line 21, a common electrode line 14, a thin film transistor 10, a pixel electrode 15, a storage capacitor electrode 20 and the like, wherein the thin film transistor 10 comprises a gate electrode 12, an active layer 17, a source electrode 18 and a drain electrode 19, the gate electrode 12 and the active layer 17 need to be separated by a gate insulating layer 16 (shown in fig. 2), the drain electrode 19 is connected with the pixel electrode 15, the source electrode 18 is connected with the data line 21, and the gate electrode 12 is connected with the gate line 13; the common electrode line 14 is connected to the storage capacitor electrode 20, the storage capacitor electrode 20 and the pixel electrode 15 are partially overlapped (in fig. 1, the pixel electrode 15 is indicated by a dashed line frame for clarity of illustration) and insulated, and a storage capacitor is formed between the overlapped portions of the two.

Referring to fig. 3, in the present embodiment, the method for manufacturing the array substrate includes the following steps.

In step S1, please refer to fig. 4, the first photo-masking process: the gate electrode 12 and the pixel electrode 15 are formed on the substrate 11 through a photomask.

As shown in fig. 10, the gate electrode 12 includes a first transparent conductive block 151 disposed on the substrate base 11 and a first metal block 121 disposed on the first transparent conductive block 151, and the pixel electrode 15 includes a second transparent conductive block 152 disposed on the substrate base 11.

In step S2, referring to fig. 11 to fig. 15, the second photo-masking process: a gate insulating material layer 160 and an active material layer 170 are deposited on the gate electrode 12 and the pixel electrode 15, and a first via hole 161 communicating with the pixel electrode 15 is formed through a photo-masking process.

In step S3, referring to fig. 16 to 22, the third mask process: a second metal layer 180 is deposited on the active material layer 170, and a portion of the second metal layer 180 that serves as the source electrode 18 and the drain electrode 19 (i.e., the source electrode 18 and the drain electrode 19) and a portion of the active material layer 170 that serves as the active layer 17 and is located below the source electrode 18 and the drain electrode 19 (i.e., the active layer 17) are formed through a photo-masking process, and the drain electrode 19 is connected to the pixel electrode 15 through the first via 161. Thus, the array substrate 100 is obtained.

In the manufacturing method of the array substrate provided by the embodiment of the application, the gate electrode 12 and the pixel electrode 15 are formed simultaneously by one photo-mask process, the gate insulating layer 16 and the first via hole 161 on the active material layer 170 are formed by one photo-mask process, the active layer 17, the source electrode 18 and the drain electrode 19 are formed simultaneously by one photo-mask process, only three photo-mask processes are needed in the manufacturing process, the number of processes is small, and the number of required photo-masks is small, so that the manufacturing cost of the array substrate 100 can be obviously reduced, and the productivity is improved.

The above-mentioned manufacturing method will be further described in detail with reference to the accompanying drawings.

Specifically, as shown in fig. 4, this step S1 specifically includes the following substeps.

In step S11, please refer to fig. 4 and 5, a substrate 11 is provided, and the transparent conductive layer 150 and the first metal layer 120 are sequentially formed on the substrate 11.

Specifically, in this step S11, the substrate 11 provided may be a transparent substrate such as a glass substrate, a plastic flexible substrate, a silicon substrate, or the like.

Specifically, in step S11, the transparent conductive layer 150 may be ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), or the like, or a combination of a plurality of these materials. The transparent conductive layer 150 may have a thickness of 200 to 2000 angstroms (1 angstrom ═ 0.1 nm). The transparent conductive layer 150 may be formed by means of physical vapor deposition.

Specifically, in step S11, the material of the first metal layer 120 may be copper, aluminum, or molybdenum, or a metal composite layer structure composed of a plurality of metals such as copper, aluminum, and molybdenum. The thickness of the first metal layer 120 is 3000 angstroms to 6000 angstroms, and may be 2500 angstroms to 5000 angstroms. The first metal layer 120 may be formed by physical vapor deposition.

In an alternative embodiment, the sum of the thicknesses of the first metal layer 120 and the transparent conductive layer 150 is 2700 to 8000 angstroms, and optionally 3000 to 6000 angstroms.

In step S12, please refer to fig. 4 and 6, a photoresist layer (defined as a first photoresist layer) is formed on the first metal layer 120, and the first photoresist layer is patterned to form a first photoresist pattern 31 having a first thin region 311 and a first thick region 312.

Specifically, in the step S12, a halftone mask (or gray-scale mask) is provided to expose the first photoresist layer; forming a fully exposed area, a semi-exposed area and an unexposed area on the first photoresist layer respectively; developing the exposed first photoresist layer; after the development, the fully exposed region is removed to expose a portion of the first metal layer 120, the half exposed region is partially removed to obtain a first thin region 311, and the unexposed region is remained to obtain a first thick region 312, thereby forming the first photoresist pattern 31.

The first thick region 312 corresponds to a region of the first metal layer 120 where the gate 12 is to be formed, and the first thin region 311 corresponds to a region of the transparent conductive layer 150 where the pixel electrode 15 is to be formed.

In step S13, referring to fig. 4 and 7, the first photoresist pattern 31 is used as a protection pattern to perform wet etching on the transparent conductive layer 150 and the first metal layer 120, respectively, so as to remove the portions of the transparent conductive layer 150 and the first metal layer 120 that are not protected by the first photoresist pattern 31.

The patterns of the remaining portions of the transparent conductive layer 150 and the remaining portions of the first metal layer 120 are consistent with the pattern of the first photoresist pattern 31. The remaining portion of the transparent conductive layer 150 includes a first transparent conductive block 151 and a second transparent conductive block 152, the remaining portion of the first metal layer 120 includes a first metal block 121 and a second metal block 122, the first metal block 121 is located on the first transparent conductive block 151, and the second metal block 122 is located on the second transparent conductive block 152. Also, the first thick region 312 is located on the first metal block 121, and the first thin region 311 is located on the second metal block 122.

Specifically, in this step S13, wet etching of the first metal layer 120 and wet etching of the transparent conductive layer 150 are performed in steps. The etching solutions of the two wet etches are different to maintain the optimal etching rates for the first metal layer 120 and the transparent conductive layer 150, respectively.

In step S14, please refer to fig. 4 and 8, the first photoresist pattern 31 is ashed to remove the thinner portion of the first photoresist pattern 31. That is, the first thin region 311 is removed, resulting in the second photoresist pattern 32.

Meanwhile, in the step S14, the thickness of the first thick region 312 is reduced, and the reduced thickness value of the first thick region 312 is substantially equal to the thickness value of the first thin region 311. Therefore, the second photoresist pattern 32 is identical to the first thick region 312.

Thus, in the step S14, the second photoresist pattern 32 is located above the first metal block 121.

In step S15, referring to fig. 4 and 9, the second photoresist pattern 32 is used as a protection pattern to perform wet etching on the exposed first metal layer 120, so as to remove a portion of the first metal layer 120 not covered by the second photoresist pattern 32. That is, the second metal block 122 is etched away.

In this step S15, the remaining second transparent conductive block 152 serves as the pixel electrode 15, and the first transparent conductive block 151 and the first metal block 121 provided on the first transparent conductive block 151 serve as the gate electrode 12.

In step S16, please refer to fig. 4 and 10, the second photoresist pattern 32 is removed. The gate electrode 12 and the pixel electrode 15 on the base substrate 11 are obtained.

Here, in one embodiment, in step S1, the gate lines 13 and the common electrode lines 14 of the double-layer structure are also formed at the same time.

Specifically, in step S13, as shown in fig. 7, the first thick region 312 also corresponds to an area on the first metal layer 120 where the gate line 13 and the common electrode line 14 are to be formed. In step S14, the remaining portion of first metal layer 120 further includes third metal block 123 and fourth metal block 124, and the remaining portion of transparent conductive layer 150 further includes third transparent conductive block 153 and fourth transparent conductive block 154; the third metal block 123 is positioned on the third transparent conductive block 153, the fourth metal block 124 is positioned on the fourth transparent conductive block 154, and the second photoresist pattern 32 is also positioned on the third metal block 123 and the fourth metal block 124. After steps S15 and S16, the third metal block 123 and the third transparent conductive block 153 serve as the gate line 13, and the fourth metal block 124 and the fourth transparent conductive block 154 serve as the common electrode line 14.

As shown in fig. 11, step S2 specifically includes the following substeps.

Step S21, please refer to fig. 11 and 12, in which a gate insulating material layer 160 and an active material layer 170 are sequentially deposited and formed on the gate 12 and the pixel electrode 15;

in step S21, the gate insulating material layer 160 may be silicon dioxide (SiO)₂) And silicon nitride (SiN)_X) At least one of (1). The gate insulating material layer 160 is formed by chemical vapor deposition, and may have a thickness of 2000 to 6000 angstroms.

In step S21, the active material layer 170 may be formed by cvd, and the thickness thereof may be 300 to 3000 angstroms.

The active material layer 170 may be an oxide semiconductor layer, or includes a semiconductor layer 171 disposed on the gate insulating material layer 160 and a doped layer 1702 disposed on the semiconductor layer 171, and the semiconductor layer 171 may be an amorphous silicon layer or a polysilicon layer. Doped layer 1702 can have a thickness of 100 angstroms to 500 angstroms.

In step S22, please refer to fig. 11 and 13, a second photoresist layer is formed on the active material layer 170, and the second photoresist layer is patterned to obtain a third photoresist pattern 40. The third photoresist pattern 40 exposes regions of the active material layer 170 corresponding to portions of the pixel electrodes 15 and portions of the common electrode lines 14.

Specifically, in step S22, a second mask is provided and the second photoresist layer is exposed to form a fully exposed region and an unexposed region; the fully exposed region corresponds to a portion of the pixel electrode 15 and a portion of the common electrode line 14. Developing the exposed second photoresist layer; after development, the fully exposed regions of the second photoresist layer are removed and the unexposed regions are retained to form a third photoresist pattern 40.

In step S23, referring to fig. 11 and 14, the active material layer 170 and the gate insulating material layer 160 are etched by using the third photoresist pattern 40 as a protection pattern, so as to form a first via 161 penetrating the pixel electrode 15 and a second via 162 penetrating the common electrode line 14.

In step S24, please refer to fig. 11 and 15, the third photoresist pattern 40 is removed.

Then, the gate insulating material layer 160 having the first and

second vias

161 and 162 forms the gate insulating layer 16.

Specifically, as shown in fig. 16, step S3 specifically includes the following substeps.

In step S31, please refer to fig. 16 and 17, a second metal layer 180 is deposited on the active material layer 170 having the first via 161 and the second via 162 and the gate insulating material layer 160 (i.e., the gate insulating layer 16).

As shown in fig. 17, the second metal layer 180 is connected to the pixel electrode 15 via the first via 161, and is connected to the common electrode line 14 via the second via 162.

Specifically, in step S31, a second metal layer 180 is deposited on the active material layer 170 and the gate insulating material layer 160 by physical vapor deposition, and the material of the second metal layer 180 may be copper, aluminum, or molybdenum, or a metal composite layer structure composed of multiple metals such as copper, aluminum, and molybdenum. The thickness of the second metal layer 180 is 3000 to 6000 angstroms.

In step S32, please refer to fig. 16 and 18, a third photoresist layer is formed on the second metal layer 180, and the third photoresist layer is patterned to obtain a fourth photoresist pattern 51 including a second thin region 511 and a second thick region 512.

Specifically, in the step S32, a third mask is provided, wherein the third mask is a gray-scale mask or a halftone mask; exposing the third photoresist layer to form a fully exposed region, a semi-exposed region and an unexposed region on the third photoresist layer, wherein the fully exposed region corresponds to the region of the pixel electrode 15 except the first via hole 161, and the semi-exposed region corresponds to the region of the active material layer 170 where a channel region is to be formed; developing the exposed third photoresist layer; after development, the fully exposed region is removed, the half exposed region is partially removed to form a second thin region 511, the unexposed region is retained to form a second thick region 512, and a fourth photoresist pattern 51 is obtained;

as shown in fig. 18, the fourth photoresist pattern 51 is formed such that the second thin region 511 is located above the gate electrode 12 and corresponds to the middle region of the gate electrode 12, and the second thick region 512 is connected to opposite sides of the second thin region 511 and is located above the gate electrode 12 and above the first via 161 and above the second via 162;

step S33, please refer to fig. 16 and 19, in which the fourth photoresist pattern 51 is used as a protection pattern, and the second metal layer 180 and the active material layer 170 are wet-etched to remove the portions of the second metal layer 180 and the active material layer 170 that are not protected by the fourth photoresist pattern 51;

as shown in fig. 19, a portion of the obtained second metal layer 180 remains below the second thin region 511 and the second thick region 512, wherein a portion of the second metal layer is located above the gate 12 and serves as a source/drain metal block 181, and a portion of the active material layer 170 also remains below the source/drain metal block 181; another portion of which is located above the second via 162 and serves as the storage capacitor electrode 20.

The source-drain metal block 181 is connected to the pixel electrode 15 through a first via 161, and the storage capacitor electrode 20 is connected to the common electrode line 14 through a second via 162. The storage capacitor electrode 20 partially overlaps the pixel electrode 15, and a storage capacitor is formed between the overlapping portions.

Step S34, please refer to fig. 16 and 20, in which the fourth photoresist pattern 51 is ashed to remove the thinner portion of the fourth photoresist pattern 51; that is, the second thin region 511 is removed, and the second thick region 512 is thinned (the reduced thickness value is substantially equal to the thickness value of the second thin region 511); a fifth photoresist pattern 52 is obtained. The fifth photoresist pattern 52 is identical to the second thick region 512.

As shown in fig. 20, the fifth photoresist pattern 52 includes a plurality of pattern blocks 521, wherein one pattern block 521 is located above the source/drain metal block 181, another pattern block 521 is located above the source/drain metal block 181 and above the first via 161, and the two pattern blocks 521 are spaced apart from each other to expose a middle region of the source/drain metal block 181; a further pattern block 521 is located above the storage capacitor electrode 20, i.e. above the second via 162, and covers and protects the storage capacitor electrode 20;

in step S35, please refer to fig. 16 and fig. 21, the fifth photoresist pattern 52 is used as a protection pattern to etch the source/drain metal block 181, and the middle portion of the source/drain metal block 181, that is, the portion of the source/drain metal block 181 that is not protected by the pattern block 521, is removed.

The source/drain metal blocks 181 at the lower parts of the two pattern blocks 521 are a source electrode 18 and a drain electrode 19, respectively, wherein the part connected to the pixel electrode 15 through the first via 161 is the drain electrode 19, and the other part is the source electrode 18.

In one embodiment, the active material layer 170 includes a semiconductor material layer 1701 and a doping layer 1702, and the active layer 17 formed by etching includes a semiconductor layer 171 and an ohmic contact layer 172.

Specifically, in step S35, the fifth photoresist pattern 52 is used as a protection pattern to etch a portion of the doped layer 1702 under the source/drain metal block 181, and the middle portion of the doped layer 1702, i.e., the portion not protected by the pattern block 521, is removed. In this way, the doped layer 1702 after etching forms two spaced ohmic contact layers 172, which are respectively located below the source 18 and the drain 19 for reducing the contact resistance between the source 18 and the drain 19 and the semiconductor layer 171, and the semiconductor material layer 1701 corresponding to the source-drain metal block 181 is used as the semiconductor 171.

In step S36, please refer to fig. 16 and 22, the fifth photoresist pattern 52 is removed. In this way, the active layer 17, the source electrode 18, and the drain electrode 19 are obtained, respectively, the drain electrode 19 is connected to the pixel electrode 15 through the first via 161, and the storage capacitor electrode 20 is connected to the common electrode line 14 through the second via 162.

In step S3, the data line 21 is also formed at the same time.

Specifically, in step S32, the second thick region 512 in the fifth photoresist pattern 52 further corresponds to the region on the second metal layer 180 where the data line 21 is to be formed; in step S33, after wet etching the second metal layer 180 and the active material layer 170 using the fifth photoresist pattern 52 as a protection pattern, a region of the second metal layer 180 corresponding to the data line 21 to be formed is retained, and thus, the portion is used as the data line 21; in step S35, after etching the source/drain metal block 181 with the fifth photoresist pattern 52 as a protection pattern, the data line 21 is protected and remains; in step S36, the data line 21 is obtained.

Thus, the data line 21 and the source 18 are in the same layer structure and are connected to each other.

As shown in fig. 22, a part of the active material layer 170 remains below the data line 21, and the part of the active material layer 170 is in the same layer as and connected to the active layer 17. A portion of the active material layer 170 also remains under the storage capacitor electrode 20, and the portion of the active material layer 170 is in the same layer as the active layer 17.

Referring to fig. 3 and 23, the method for manufacturing the array substrate further includes:

in step S4, an alignment layer 22 is formed on the source and drain

electrodes

18 and 19. Alignment grooves (not shown) are regularly arranged on the surface of the alignment layer 22 for keeping the liquid crystal molecules in the liquid crystal layer 200 (please refer to fig. 24) at a specific pretilt angle.

Specifically, in step S4, the material of the alignment layer 22 may be polyimide, which is formed by coating and has a relatively flat surface; then, the polyimide layer is imprinted or rubbed by a roller with regular grains to form a regular microstructure on the surface, and after the polyimide layer is cured, the alignment layer 22 with stable orientation grooves is obtained.

In other alternative embodiments, the alignment layer 22 may be fabricated by other methods, such as photo-alignment, and the like, and will not be described in detail.

The embodiment of the present application further provides an array substrate 100, which is manufactured by the manufacturing method of the array substrate. Specifically, referring to fig. 1 and fig. 2, the array substrate 100 includes: a substrate 11, a gate electrode 12 and a pixel electrode 15 provided on the substrate 11, a gate insulating layer 16 provided on the gate electrode 12 and the pixel electrode 15, an active layer 17 provided on the gate insulating layer 16, and a source electrode 18 and a drain electrode 19 provided on the active layer 17.

The gate 12 includes a first transparent conductive block 151 disposed on the substrate 11 and a first metal block 121 disposed on the first transparent conductive block 151, that is, the gate 12 has a double-layer conductive structure. The pixel electrode 15 includes a second transparent conductive block 152 provided on the substrate base 11. The second transparent conductive block 152 is the same as the first transparent conductive block 151 in material and thickness, and has the same layer structure. The first via hole 161 penetrates the gate insulating layer 16 and is connected to the pixel electrode 15, and the drain electrode 19 is connected to the pixel electrode 15 through the first via hole 161.

In the array substrate 100 provided in the embodiment of the present application, the gate 12 and the pixel electrode 15 are formed simultaneously by one photo-masking process, the first via hole 161 on the gate insulating layer 16 is formed by one photo-masking process, and the active layer 17, the source electrode 18, and the drain electrode 19 are formed simultaneously by one photo-masking process, so that the array substrate 100 only needs three photo-masking processes for manufacturing, the number of the processes is small, the number of the required photo-masks is small, and therefore, the array substrate 100 has a low manufacturing cost and a low manufacturing period.

As shown in fig. 1 and 2, the array substrate 100 further includes a gate line 13 and a common electrode line 14 disposed on the substrate 11, and a storage capacitor electrode 20 disposed on the gate insulating layer 16, wherein the gate line 13 and the common electrode line 14 are disposed at an interval, and the gate 12 is connected to the gate line 13. The gate insulating layer 16 is further provided with a second through hole 162, the storage capacitor electrode 20 is connected to the common electrode line 14 through the second through hole 162, the storage capacitor electrode 20 overlaps with the edge of the pixel electrode 15, and a storage capacitor is formed therebetween.

In one embodiment, the gate line 13, the common electrode line 14 and the gate electrode 12 are formed in the same mask process, so that the gate electrode 12 and the common electrode line 14 are also a double-layer structure. As shown in fig. 2, the gate line 13 includes a third transparent conductive block 153 disposed on the substrate 11 and a third metal block 123 disposed on the third transparent conductive block 153, and the third transparent conductive block 153 and the third metal block 123 have the same size and shape; the common electrode line 14 includes a fourth transparent conductive block 154 disposed on the substrate 11 and a fourth metal block 124 disposed on the fourth transparent conductive block 154, and the fourth transparent conductive block 154 and the fourth metal block 124 have the same size and shape.

Specifically, the first to fourth transparent conductive blocks 151 to 154 are made of the same layer and thickness, such as ITO, IZO, ZnO, or the like, or a combination of multiple materials. The thicknesses of the first to fourth transparent conductive blocks 151 to 154 may be all 200 to 2000 angstroms.

The first metal block 121, the third metal block 123 and the fourth metal block 124 are made of the same layer and thickness, such as copper, aluminum or molybdenum, or a metal composite layer structure made of multiple metals of copper, aluminum, molybdenum and the like. The thicknesses of the first metal block 121, the third metal block 123 and the fourth metal block 124 are all 3000 angstroms to 6000 angstroms, and may be 2500 angstroms to 5000 angstroms.

In an alternative embodiment, the thickness of the gate line 13, the common electrode line 14 and the gate electrode 12 may range from 2700 to 8000 angstroms, and optionally from 3000 to 6000 angstroms.

In this embodiment, the gate lines 13, the gate electrodes 12, and the common electrode lines 14 all adopt a double-layer conductive structure, and therefore, the thicknesses thereof are appropriately increased, so that the respective resistances are correspondingly reduced.

Gate insulationThe material of layer 16 may be SiO₂And SiN_XMay have a thickness of 2000 to 6000 angstroms.

The thickness of the active layer 17 may be 300 to 3000 angstroms.

The active layer 17 may be an oxide semiconductor layer. Alternatively, the active layer 17 includes a semiconductor layer 171 disposed on the gate insulating layer 16 and an ohmic contact layer 172 disposed on the semiconductor layer 171, and the semiconductor layer 171 may be an amorphous silicon layer or a polysilicon layer, wherein the ohmic contact layer 172 may have a thickness of 100 to 500 angstroms.

Referring to fig. 1, the common electrode lines 14 and the gate lines 13 are parallel to each other and spaced apart from each other, and the thin film transistor 10, the pixel electrode 15, and the storage capacitor electrode 20 are disposed between two adjacent common electrode lines 14 and gate lines 13.

Wherein, optionally, as shown in fig. 1, the storage capacitor electrode 20 is a frame shape enclosed on three sides, which is enclosed on the other three sides of the pixel electrode 15 except for one side edge for connecting with the drain electrode 19. The purpose of this arrangement is, on one hand, that the storage capacitor electrode 20 is far away from the drain electrode 19, which is beneficial to the implementation of the process and avoids the short circuit between the two; on the other hand, the storage capacitor electrode 20 has a sufficiently large area to ensure that the capacitance of the storage capacitor is sufficiently large for maintaining the voltage on the pixel electrode 15.

The storage capacitor electrode 20, the source electrode 18 and the drain electrode 19 are made of the same layer and the same thickness material and are manufactured by the same photo-mask process. As shown in fig. 2, a portion of the active material layer 170 is sandwiched between the storage capacitor electrode 20 and the gate insulating layer 16 (referring to fig. 19 to 20, the material of the active material layer 170 and the material of the active layer 17 are the same layer and the same thickness).

The data line 21, the source electrode 18, the drain electrode 19 and the active layer 17 are formed by the same photo-masking process.

In one embodiment, as shown in fig. 1 and 2, the array substrate 100 further includes a data line 21 disposed on the same layer as the source electrode 18 and the drain electrode 19, the data line 21 is connected to the source electrode 18, and a portion of an active material layer 170 is sandwiched between the data line 21 and the gate insulating layer 16 (referring to fig. 19 to 20, the material of the active material layer 170 is the same layer and the same thickness as the material of the active layer 17), and the active material layer 170 is connected to the active layer 17.

As shown in fig. 2, in one embodiment, the array substrate 100 further includes an alignment layer 22 formed over the source electrode 18 and the drain electrode 19. Alignment grooves (not shown) are regularly arranged on the surface of the alignment layer 22 for keeping the liquid crystal molecules in the liquid crystal layer 200 (please refer to fig. 24) at a specific pretilt angle. The material of the alignment layer 22 may be a polyimide layer.

Referring to fig. 24, an embodiment of the present invention further provides a display panel 400, which includes the array substrate 100, the color filter substrate 300 opposite to the array substrate 100, and the liquid crystal layer 200 interposed between the array substrate 100 and the display panel 400. The features of the array substrate 100 can be referred to the description of the above embodiments, and are not repeated herein.

In the display panel 400 provided in the embodiment of the application, in the array substrate 100, the gate 12 and the pixel electrode 15 are formed simultaneously by one photo-mask process, the first via hole 161 on the gate insulating layer 16 is formed by one photo-mask process, the active layer 17, the source electrode 18 and the drain electrode 19 are formed simultaneously by one photo-mask process, the array substrate 100 is manufactured by only three photo-mask processes, the number of processes is small, the number of required photo-masks is small, the manufacturing cost of the array substrate 100 is low, the manufacturing period is low, therefore, the manufacturing cost of the display panel 400 is low, the manufacturing period is low, and the productivity is greatly improved in the actual production.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. An array substrate, comprising:

a substrate base plate;

an active layer disposed on the gate insulating layer; and

2. The array substrate of claim 1, wherein the array substrate further comprises:

3. The array substrate of claim 1, wherein the array substrate further comprises:

4. The array substrate of claim 3, wherein an active material layer is disposed between the storage capacitor electrode and the gate insulating layer, and the active material layer is the same as the active layer.

5. The array substrate of claim 3, wherein the first via and the second via are respectively located at opposite sides of the pixel electrode, and the storage capacitor electrode overlaps with other side edges of the pixel electrode except for one side edge for connection with the drain electrode.

6. The array substrate of any one of claims 1 to 5, wherein the array substrate further comprises:

7. A manufacturing method of an array substrate is characterized by comprising the following steps:

8. The method for manufacturing an array substrate according to claim 7, wherein in the first photo-masking process, a gate line is further formed on the substrate, the gate line including a third transparent conductive block disposed on the substrate and a third metal block disposed on the third transparent conductive block; the third transparent conductive block is connected with the first transparent conductive block at the same layer, and the third metal block is connected with the first metal block at the same layer; and/or

9. The method for manufacturing an array substrate according to claim 7, wherein in the first photo-masking process, a common electrode line is further formed on the substrate; in the second photomask manufacturing process, a second through hole penetrating to the common electrode line is further formed on the insulating material layer and the active material layer; in the third photomask manufacturing process, the second metal layer is further processed to form a storage capacitor electrode, and the storage capacitor electrode is connected with the common electrode line through the second via hole.

10. A display panel, comprising the array substrate according to any one of claims 1 to 6, a color filter substrate, and a liquid crystal layer disposed between the color filter substrate and the array substrate.