CN114258536B - 联网输入/输出存储器管理单元 - Google Patents

联网输入/输出存储器管理单元 Download PDF

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Publication number
CN114258536B
CN114258536B CN202080058329.7A CN202080058329A CN114258536B CN 114258536 B CN114258536 B CN 114258536B CN 202080058329 A CN202080058329 A CN 202080058329A CN 114258536 B CN114258536 B CN 114258536B
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China
Prior art keywords
iommu
memory access
access request
memory
gpu
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CN202080058329.7A
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Chinese (zh)
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CN114258536A (zh
Inventor
索努·阿罗拉
保罗·布林策
菲利普·恩杰
尼蓬·哈沙德克·拉瓦尔
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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Publication of CN114258536A publication Critical patent/CN114258536A/zh
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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68Details of translation look-aside buffer [TLB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
CN202080058329.7A 2019-08-22 2020-08-21 联网输入/输出存储器管理单元 Active CN114258536B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/548,692 US11003588B2 (en) 2019-08-22 2019-08-22 Networked input/output memory management unit
US16/548,692 2019-08-22
PCT/US2020/047376 WO2021035134A1 (en) 2019-08-22 2020-08-21 A networked input/output memory management unit

Publications (2)

Publication Number Publication Date
CN114258536A CN114258536A (zh) 2022-03-29
CN114258536B true CN114258536B (zh) 2023-08-15

Family

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CN202080058329.7A Active CN114258536B (zh) 2019-08-22 2020-08-21 联网输入/输出存储器管理单元

Country Status (6)

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US (1) US11003588B2 (enExample)
EP (1) EP4018320B1 (enExample)
JP (1) JP7387873B2 (enExample)
KR (1) KR102693394B1 (enExample)
CN (1) CN114258536B (enExample)
WO (1) WO2021035134A1 (enExample)

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Publication number Priority date Publication date Assignee Title
US11874768B1 (en) * 2019-11-14 2024-01-16 Xilinx, Inc. Flash memory emulation
US11720401B2 (en) * 2020-03-27 2023-08-08 Intel Corporation Reclaiming and reusing pre-boot reserved memory post-boot
US11698860B2 (en) * 2020-12-28 2023-07-11 Ati Technologies Ulc Method, system, and apparatus for supporting multiple address spaces to facilitate data movement
US11550722B2 (en) * 2021-03-02 2023-01-10 Ati Technologies Ulc Method, system, and apparatus for supporting multiple address spaces to facilitate data movement
US12204461B2 (en) * 2021-06-25 2025-01-21 Intel Corporation Apparatus, system, and method for secure memory access control
JP7762041B2 (ja) * 2021-11-10 2025-10-29 ルネサスエレクトロニクス株式会社 半導体装置
CN118035134A (zh) * 2022-11-14 2024-05-14 华为技术有限公司 一种地址翻译方法及设备

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CN109154907A (zh) * 2016-05-27 2019-01-04 超威半导体公司 在输入-输出存储器管理单元中使用多个存储器元件来执行虚拟地址到物理地址转译
CN109844751A (zh) * 2016-10-19 2019-06-04 超威半导体公司 处理系统中的直接存储器访问授权
CN110046106A (zh) * 2019-03-29 2019-07-23 海光信息技术有限公司 一种地址转换方法、地址转换模块及系统

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US7548999B2 (en) * 2006-01-17 2009-06-16 Advanced Micro Devices, Inc. Chained hybrid input/output memory management unit
US8635385B2 (en) 2010-07-16 2014-01-21 Advanced Micro Devices, Inc. Mechanism to handle peripheral page faults
US9218310B2 (en) * 2013-03-15 2015-12-22 Google Inc. Shared input/output (I/O) unit
US20160062911A1 (en) * 2014-08-27 2016-03-03 Advanced Micro Devices, Inc. Routing direct memory access requests in a virtualized computing environment
US9594521B2 (en) 2015-02-23 2017-03-14 Advanced Micro Devices, Inc. Scheduling of data migration
MA41915A (fr) * 2015-04-07 2018-02-13 Benjamin Gittins Unités de requête de transfert de mémoire programmable
US10671419B2 (en) * 2016-02-29 2020-06-02 Red Hat Israel, Ltd. Multiple input-output memory management units with fine grained device scopes for virtual machines
US10514943B2 (en) * 2016-11-17 2019-12-24 Qualcomm Incorporated Method and apparatus for establishing system-on-chip (SOC) security through memory management unit (MMU) virtualization
US10380039B2 (en) 2017-04-07 2019-08-13 Intel Corporation Apparatus and method for memory management in a graphics processing environment
US11599621B2 (en) 2019-03-30 2023-03-07 Intel Corporation Apparatuses, methods, and systems for verification of input-output memory management unit to device attachment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109154907A (zh) * 2016-05-27 2019-01-04 超威半导体公司 在输入-输出存储器管理单元中使用多个存储器元件来执行虚拟地址到物理地址转译
CN109844751A (zh) * 2016-10-19 2019-06-04 超威半导体公司 处理系统中的直接存储器访问授权
CN110046106A (zh) * 2019-03-29 2019-07-23 海光信息技术有限公司 一种地址转换方法、地址转换模块及系统

Also Published As

Publication number Publication date
WO2021035134A1 (en) 2021-02-25
JP2022544791A (ja) 2022-10-21
EP4018320A1 (en) 2022-06-29
US20210056042A1 (en) 2021-02-25
CN114258536A (zh) 2022-03-29
EP4018320A4 (en) 2023-10-11
KR20220050171A (ko) 2022-04-22
US11003588B2 (en) 2021-05-11
KR102693394B1 (ko) 2024-08-09
EP4018320B1 (en) 2024-11-27
JP7387873B2 (ja) 2023-11-28

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