JP7387873B2 - ネットワーク化された入出力メモリ管理ユニット - Google Patents

ネットワーク化された入出力メモリ管理ユニット Download PDF

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JP7387873B2
JP7387873B2 JP2022509631A JP2022509631A JP7387873B2 JP 7387873 B2 JP7387873 B2 JP 7387873B2 JP 2022509631 A JP2022509631 A JP 2022509631A JP 2022509631 A JP2022509631 A JP 2022509631A JP 7387873 B2 JP7387873 B2 JP 7387873B2
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iommu
memory access
access request
primary
memory
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Japanese (ja)
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JP2022544791A (ja
JP2022544791A5 (enExample
Inventor
アローラ ソヌ
ブリンザー ポール
ン フィリップ
ハルシャダク ラヴァル ニッポン
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
JP2022509631A 2019-08-22 2020-08-21 ネットワーク化された入出力メモリ管理ユニット Active JP7387873B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/548,692 US11003588B2 (en) 2019-08-22 2019-08-22 Networked input/output memory management unit
US16/548,692 2019-08-22
PCT/US2020/047376 WO2021035134A1 (en) 2019-08-22 2020-08-21 A networked input/output memory management unit

Publications (3)

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JP2022544791A JP2022544791A (ja) 2022-10-21
JP2022544791A5 JP2022544791A5 (enExample) 2023-08-30
JP7387873B2 true JP7387873B2 (ja) 2023-11-28

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JP2022509631A Active JP7387873B2 (ja) 2019-08-22 2020-08-21 ネットワーク化された入出力メモリ管理ユニット

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US (1) US11003588B2 (enExample)
EP (1) EP4018320B1 (enExample)
JP (1) JP7387873B2 (enExample)
KR (1) KR102693394B1 (enExample)
CN (1) CN114258536B (enExample)
WO (1) WO2021035134A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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US11874768B1 (en) * 2019-11-14 2024-01-16 Xilinx, Inc. Flash memory emulation
US11720401B2 (en) * 2020-03-27 2023-08-08 Intel Corporation Reclaiming and reusing pre-boot reserved memory post-boot
US11698860B2 (en) * 2020-12-28 2023-07-11 Ati Technologies Ulc Method, system, and apparatus for supporting multiple address spaces to facilitate data movement
US11550722B2 (en) * 2021-03-02 2023-01-10 Ati Technologies Ulc Method, system, and apparatus for supporting multiple address spaces to facilitate data movement
US12204461B2 (en) * 2021-06-25 2025-01-21 Intel Corporation Apparatus, system, and method for secure memory access control
JP7762041B2 (ja) * 2021-11-10 2025-10-29 ルネサスエレクトロニクス株式会社 半導体装置
CN118035134A (zh) * 2022-11-14 2024-05-14 华为技术有限公司 一种地址翻译方法及设备

Citations (3)

* Cited by examiner, † Cited by third party
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US20170249106A1 (en) 2016-02-29 2017-08-31 Red Hat Israel, Ltd. Multiple input-output memory management units with fine grained device scopes for virtual machines
JP2017529606A (ja) 2014-08-27 2017-10-05 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 仮想化されたコンピューティング環境におけるダイレクトメモリアクセス要求のルーティング
JP2018523247A (ja) 2015-04-07 2018-08-16 ベンジャミン・アーロン・ジッティンズ プログラム可能なメモリ転送リクエストユニット

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US7548999B2 (en) * 2006-01-17 2009-06-16 Advanced Micro Devices, Inc. Chained hybrid input/output memory management unit
US8635385B2 (en) 2010-07-16 2014-01-21 Advanced Micro Devices, Inc. Mechanism to handle peripheral page faults
US9218310B2 (en) * 2013-03-15 2015-12-22 Google Inc. Shared input/output (I/O) unit
US9594521B2 (en) 2015-02-23 2017-03-14 Advanced Micro Devices, Inc. Scheduling of data migration
US10678702B2 (en) * 2016-05-27 2020-06-09 Advanced Micro Devices, Inc. Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations
US10176122B2 (en) * 2016-10-19 2019-01-08 Advanced Micro Devices, Inc. Direct memory access authorization in a processing system
US10514943B2 (en) * 2016-11-17 2019-12-24 Qualcomm Incorporated Method and apparatus for establishing system-on-chip (SOC) security through memory management unit (MMU) virtualization
US10380039B2 (en) 2017-04-07 2019-08-13 Intel Corporation Apparatus and method for memory management in a graphics processing environment
CN110046106B (zh) * 2019-03-29 2021-06-29 海光信息技术股份有限公司 一种地址转换方法、地址转换模块及系统
US11599621B2 (en) 2019-03-30 2023-03-07 Intel Corporation Apparatuses, methods, and systems for verification of input-output memory management unit to device attachment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017529606A (ja) 2014-08-27 2017-10-05 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 仮想化されたコンピューティング環境におけるダイレクトメモリアクセス要求のルーティング
JP2018523247A (ja) 2015-04-07 2018-08-16 ベンジャミン・アーロン・ジッティンズ プログラム可能なメモリ転送リクエストユニット
US20170249106A1 (en) 2016-02-29 2017-08-31 Red Hat Israel, Ltd. Multiple input-output memory management units with fine grained device scopes for virtual machines

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Publication number Publication date
WO2021035134A1 (en) 2021-02-25
JP2022544791A (ja) 2022-10-21
EP4018320A1 (en) 2022-06-29
US20210056042A1 (en) 2021-02-25
CN114258536B (zh) 2023-08-15
CN114258536A (zh) 2022-03-29
EP4018320A4 (en) 2023-10-11
KR20220050171A (ko) 2022-04-22
US11003588B2 (en) 2021-05-11
KR102693394B1 (ko) 2024-08-09
EP4018320B1 (en) 2024-11-27

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