CN114256349A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114256349A
CN114256349A CN202011017468.3A CN202011017468A CN114256349A CN 114256349 A CN114256349 A CN 114256349A CN 202011017468 A CN202011017468 A CN 202011017468A CN 114256349 A CN114256349 A CN 114256349A
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layer
forming
effective
material layer
fin
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肖芳元
徐娟
郑二虎
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Computer Hardware Design (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first device area used for forming a first type transistor and a second device area used for forming a second type transistor, and a bottom fin material layer and a channel material layer located on the bottom fin material layer are formed on the substrate; etching the channel material layer and the bottom fin material layer to form a bottom fin portion protruding out of the substrate and a first effective fin portion located on the bottom fin portion; forming a filling layer on the substrate, covering the side wall of the first effective fin part and exposing the top of the first effective fin part; removing the first effective fin part of the first device area to form a groove; forming a second effective fin portion in the groove; and forming an isolation layer on the substrate, covering the side wall of the bottom fin part, and exposing partial side wall or the whole side wall of any one of the first effective fin part and the second effective fin part. The invention improves the appearance quality of the first effective fin part and the second effective fin part, thereby improving the performance of the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which improves the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, channel conduction types of the first type transistor and the second type transistor are different, a bottom fin material layer and a channel material layer located on the bottom fin material layer are formed on the substrate, the channel material layer is used for forming a first effective fin, and the first effective fin is used for providing a channel of the second type transistor; etching the channel material layer and the bottom fin material layer in the first device region and the second device region to form a bottom fin portion protruding out of the substrate and a first effective fin portion located on the bottom fin portion; forming a filling layer on the substrate exposed out of the first effective fin part and the bottom fin part, wherein the filling layer covers the side wall of the first effective fin part and exposes out of the top of the first effective fin part; removing the first effective fin part in the first device region to form a groove surrounded by the filling layer and the bottom fin part; forming a second effective fin part in the groove, wherein the second effective fin part is used for providing a channel of the first-type transistor; and forming an isolation layer on the substrate, wherein the isolation layer covers the side wall of the bottom fin part and exposes a part of or the whole side wall of any one of the first effective fin part and the second effective fin part.
Optionally, the step of forming the filling layer includes: forming an initial filling layer on the substrate with the exposed first effective fin part and the exposed bottom fin part, wherein the initial filling layer covers the top of the first effective fin part; and carrying out planarization treatment on the initial filling layer to expose the top of the first effective fin part, wherein the rest initial filling layer is used as a filling layer.
Optionally, the material of the filling layer is a dielectric material.
Optionally, the dielectric material comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide and boron nitride.
Optionally, the step of forming an isolation layer on the substrate includes: and etching back the filling layer with partial thickness, wherein the rest filling layer is used as an isolation layer.
Optionally, in the step of providing the substrate, a hard mask layer is formed on the channel material layer; in the step of forming the bottom fin portion and the first effective fin portion, the hard mask layer is used as a mask, and the channel material layer and the bottom fin portion material layer are etched; the step of performing planarization treatment on the initial filling layer comprises the following steps: taking the top of the hard mask layer as a stop position, and grinding the initial filling layer; after the grinding treatment, removing the hard mask layer; and after removing the hard mask layer, performing back etching treatment on the residual initial filling layer by taking the top of the first effective fin part as a stop position.
Optionally, the forming process of the hard mask layer includes a multiple patterning process.
Optionally, after forming a filling layer on the substrate where the first effective fin portion and the bottom fin portion are exposed, before removing the first effective fin portion in the first device region, the forming method further includes: forming a protective layer covering the first effective fin part in the second device area; after forming the second effective fin portion in the trench and before forming an isolation layer on the substrate, the forming method further includes: and removing the protective layer.
Optionally, the step of forming the protective layer includes: forming a protective material layer covering the filling layer and the first effective fin portion; and etching the protective material layer in the first device area to expose the first effective fin part in the first device area, wherein the residual protective material layer is used as a protective layer.
Optionally, the material of the protective layer includes silicon nitride or silicon oxynitride.
Optionally, the thickness of the protective layer is
Figure BDA0002699548040000031
To
Figure BDA0002699548040000032
Optionally, the step of removing the first effective fin portion in the first device region includes: forming a shielding layer on the filling layer, wherein an opening is formed in the shielding layer, and the opening exposes the first effective fin portions in the first device region and the filling layer between the adjacent first effective fin portions; removing the first effective fin part exposed from the opening by taking the shielding layer as a mask; and removing the shielding layer.
Optionally, an epitaxial process is used to form the channel material layer on the bottom fin material layer.
Optionally, the channel material layer and the bottom fin material layer are etched by using an anisotropic dry etching process.
Optionally, an epitaxial process is used to form the second effective fin portion in the trench.
Optionally, a wet etching process is used to remove the first effective fin portion.
Optionally, the etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid, hydrogen peroxide and acetic acid.
Optionally, the first effective fin portion is removed by using an etching process, and an etching selection ratio between the first effective fin portion and the bottom fin portion is greater than or equal to 10.
Optionally, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; the material of the bottom fin material layer is Si, and the material of the channel material layer is SiGe.
Optionally, the bottom fin material layer and the substrate are of an integrated structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, a channel material layer is formed on a bottom fin material layer, the channel material layer is used for forming a first effective fin part, the first effective fin part is used for providing a channel of a second-type transistor, the channel material layer and the bottom fin material layer are etched subsequently, after a bottom fin part protruding out of a substrate and a first effective fin part positioned on the bottom fin part are formed, the first effective fin part in a first device area is removed, a groove surrounded by a filling layer and the bottom fin part is formed, and then a second effective fin part is formed in the groove and used for providing a channel of the first-type transistor; the method comprises the steps that a channel material layer is formed on a substrate, wherein the channel material layer covers the surface of a bottom fin material layer completely, and at the moment, a pattern is not formed in the substrate, so that a load effect caused by pattern density can be avoided, and the forming quality and the thickness uniformity of the channel material layer are improved; in summary, by forming the channel material layer on the bottom fin material layer and then replacing the first effective fin portion in the first device region with the second effective fin portion, the appearance quality of the first effective fin portion and the second effective fin portion is improved, so that the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, which includes a first device region i for forming a first type transistor and a second device region ii for forming a second type transistor, wherein channel conductivity types of the first type transistor and the second type transistor are different, a first channel material layer 15 is formed on the substrate 10, the first channel material layer 15 is used for forming a first effective fin, and the first effective fin is used for providing a channel of the first type transistor.
As an example, the first type transistor is a PMOS transistor and the second type transistor is an NMOS transistor.
Referring to fig. 2, in the second device region ii, a groove 11 is formed through the first channel material layer 15.
Referring to fig. 3, a second channel material layer 12 is formed in the recess 11 using an epitaxial process.
Referring to fig. 4, the second channel material layer 12 is planarized such that the top surface of the remaining second channel material layer 12 is flush with the top surface of the first channel material layer 15.
Referring to fig. 5, after the second channel material layer 12 is planarized, a hard mask material layer 14 covering the second channel material layer 12 and the first channel material layer 15 is formed; and forming a mask side wall 16 on the hard mask material layer 14 of the first device area I and the second device area II.
Referring to fig. 6, the hard mask material layer 14 is etched by using the mask sidewall 16 as a mask to form a hard mask layer 24; and etching the first channel material layer 15, the second channel material layer 12 and the substrate 10 with partial thickness by taking the hard mask layer 24 as a mask, and patterning the substrate 10 into a substrate 20 and a bottom fin portion 25 protruding out of the substrate 20, wherein the residual first channel material layer 15 on the bottom fin portion 25 of the first device region I is used as a first effective fin portion 21, and the residual second channel material layer 12 on the bottom fin portion 25 of the second device region II is used as a second effective fin portion 22.
The second channel material layer 12 is formed in the recess 11, and is grown on the basis of the bottom surface and the side surface of the recess 11 during the epitaxial process, which easily reduces the uniformity of the epitaxial process, and also easily causes a problem of lattice dislocation of the second channel material layer 12, thereby easily reducing the formation quality of the second channel material layer 12. In particular, the recesses 11 generally have different opening sizes according to the requirements of the pattern design, thereby easily further reducing the uniformity of the epitaxial process and the quality uniformity of the second channel material layer 12.
Moreover, after the second channel material layer 12 is formed in the recess 11, the second channel material layer 12 is also subjected to a planarization process, so that the top surface of the remaining second channel material layer 12 is flush with the top surface of the first channel material layer 15, which puts high requirements on the ratio of the removal rates of the second channel material layer 12 and the first channel material layer 15 and the top surface topography of the remaining second channel material layer 12. For example, during the planarization process, it is difficult for the top surface of the first channel material layer 15 to define the stop position of the planarization process, so that the flatness of the top surfaces of the remaining second channel material layer 12 and the first channel material layer 15 is easily lowered, and also the thickness of the first channel material layer 15 is easily caused to be smaller than a target value.
In addition, in the process of forming the first effective fin portion 21 and the second effective fin portion 22, the hard mask layer 24 is used as a mask to etch the first channel material layer 15, the second channel material layer 12 and the substrate 10 with a partial thickness, that is, the first channel material layer 15 and the second channel material layer 12 are etched in the same etching step, that is, two different materials are etched simultaneously in the same etching step, which provides a higher requirement for an etching process and easily reduces etching uniformity, thereby causing adverse effects on the appearance quality of the first effective fin portion 21 and the second effective fin portion 22.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, channel conduction types of the first type transistor and the second type transistor are different, a bottom fin material layer and a channel material layer located on the bottom fin material layer are formed on the substrate, the channel material layer is used for forming a first effective fin, and the first effective fin is used for providing a channel of the second type transistor; etching the channel material layer and the bottom fin material layer in the first device region and the second device region to form a bottom fin portion protruding out of the substrate and a first effective fin portion located on the bottom fin portion; forming a filling layer on the substrate exposed out of the first effective fin part and the bottom fin part, wherein the filling layer covers the side wall of the first effective fin part and exposes out of the top of the first effective fin part; removing the first effective fin part in the first device region to form a groove surrounded by the filling layer and the bottom fin part; forming a second effective fin part in the groove, wherein the second effective fin part is used for providing a channel of the first-type transistor; and forming an isolation layer on the substrate, wherein the isolation layer covers the side wall of the bottom fin part and exposes a part of or the whole side wall of any one of the first effective fin part and the second effective fin part.
In the forming method provided by the embodiment of the invention, a channel material layer is formed on a bottom fin material layer, the channel material layer is used for forming a first effective fin part, the first effective fin part is used for providing a channel of a second-type transistor, the channel material layer and the bottom fin material layer are etched subsequently, after a bottom fin part protruding out of a substrate and a first effective fin part positioned on the bottom fin part are formed, the first effective fin part in a first device area is removed, a groove surrounded by a filling layer and the bottom fin part is formed, and then a second effective fin part is formed in the groove and used for providing a channel of the first-type transistor; the method comprises the steps that a channel material layer is formed on a substrate, wherein the channel material layer covers the surface of a bottom fin material layer completely, and at the moment, a pattern is not formed in the substrate, so that a load effect caused by pattern density can be avoided, and the forming quality and the thickness uniformity of the channel material layer are improved; in summary, by forming the channel material layer on the bottom fin material layer and then replacing the first effective fin portion in the first device region with the second effective fin portion, the appearance quality of the first effective fin portion and the second effective fin portion is improved, so that the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 7 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, a substrate 100 is provided, which includes a first device region i for forming a first type transistor and a second device region ii for forming a second type transistor, the first type transistor and the second type transistor have different channel conductivity types, a bottom fin material layer 110 and a channel material layer 120 on the bottom fin material layer 110 are formed on the substrate 100, the channel material layer 120 is used for forming a first effective fin, and the first effective fin is used for providing a channel of the second type transistor.
The substrate 100 is used to provide a process platform for subsequent processes.
In this embodiment, the substrate 100 is a bulk substrate (bulk substrate).
Specifically, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
The substrate 100 includes a first device region i for forming a first type transistor and a second device region ii for forming a second type transistor, the first type transistor and the second type transistor having different channel conductivity types.
In this embodiment, the first type transistor is an NMOS transistor, and the second type transistor is a PMOS transistor.
In other embodiments, the first type transistor is a PMOS transistor and the second type transistor is an NMOS transistor.
The subsequent process further comprises: etching the channel material layer 120 and the bottom fin material layer 110, patterning the bottom fin material layer 110 into a bottom fin portion protruding out of the substrate 100, and patterning the channel material layer 120 into a first effective fin portion located on the bottom fin portion; forming a filling layer on the substrate 100 with the first effective fin portion and the bottom fin portion exposed, wherein the filling layer exposes the top of the first effective fin portion; removing the first effective fin part in the first device area I to form a groove surrounded by the filling layer and the bottom fin part; and forming a second effective fin part in the groove, wherein the second effective fin part is used for providing a channel of the first-type transistor.
The layer of channel material 120 is used in preparation for forming the first active fin. Wherein the first active fin is configured to provide a channel for a transistor of a second type.
In this embodiment, the second type transistor is a PMOS transistor, and thus, the channel material layer 120 is SiGe. By adopting the SiGe material, the problem of Negative Bias Temperature Instability (NBTI) of the PMOS transistor is favorably improved, so that the performance of the PMOS transistor is improved.
In this embodiment, the channel material layer 120 is formed on the bottom fin material layer 110 by an epitaxial process.
The channel material layer 120 is epitaxially grown on the basis of the bottom fin material layer 110, at this time, the bottom fin material layer 110 is also patterned, the surface area of the bottom fin material layer 110 is large, epitaxial growth is easily performed on the surface of the bottom fin material layer 110, controllability and reliability of an epitaxial process are high, and accordingly improvement of formation quality and thickness uniformity of the channel material layer 120 is facilitated; further, a load effect caused by a difference in pattern density can be avoided.
The bottom fin material layer 110 is used to prepare for forming the bottom fin, thereby providing support for the first active fin and the second active fin.
The material of the bottom fin material layer 110 is selected as follows: in the step of removing the first effective fin portion in the first device region I, the etching selection ratio between the first effective fin portion and the bottom fin portion is larger than or equal to 10, so that the influence of a subsequent etching process for removing the first effective fin portion on the bottom fin portion is effectively reduced, and correspondingly, in the process of removing the first effective fin portion in the first device region I, the bottom fin portion is favorably passed through, and the stop position of the etching process is favorably controlled.
In this embodiment, the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor, and therefore, the material of the bottom fin material layer 110 is Si.
The etching selectivity of SiGe and Si is relatively high, and by setting the material of the bottom fin material layer 110 to Si, the influence of the subsequent etching process for removing the first effective fin on the bottom fin can be effectively reduced. Moreover, Si is a commonly used semiconductor material, and the process compatibility is high.
In this embodiment, the bottom fin material layer 110 and the substrate 100 are integrated, so as to simplify the process steps, i.e., the step of epitaxially growing the bottom fin material layer 110 on the substrate 100 is omitted.
In other embodiments, the bottom fin material layer may also be epitaxially grown on the substrate, depending on device performance requirements. In other embodiments, the substrate and the bottom fin material layer may also constitute other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
It should be noted that, when the channel material layer 120 is formed by an epitaxial process, the closer to the interface between the channel material layer 120 and the bottom fin material layer 110, the more lattice defects of the channel material layer 120 are, and as the epitaxial material grows continuously, the fewer lattice defects in the channel material layer 120 are, and the quality of the channel material layer 120 is correspondingly improved, so if the thickness of the channel material layer 120 is too small, the more lattice defects of the channel material layer 120 are easily caused, and the quality and performance of the channel material layer 120 cannot meet the performance requirements of the transistor. In this embodiment, the thickness of the channel material layer 120 is at least
Figure BDA0002699548040000091
The channel material layer 120 is subsequently patterned into a first effective fin portion located on a bottom fin portion, and the first effective fin portion in the first device region i is also removed, if the thickness of the channel material layer 120 is too large, the height of the first effective fin portion is correspondingly too large, and accordingly, the process time and cost required for subsequently removing the first effective fin portion in the first device region i are relatively high.
To this end, as an example, the channel material layer 120 has a thickness of
Figure BDA0002699548040000092
To
Figure BDA0002699548040000093
Specifically, the thickness of the channel material layer 120 and the bottom fin material layer 110 may be set according to the fin effective height. Wherein, fin effective height means: the height of the fin covered by the gate structure.
As an example, the thickness of the channel material layer 120 is equal to the fin effective height.
By making the thickness of the channel material layer 120 equal to the effective height of the fin portion, correspondingly, after an isolation layer is subsequently formed on the substrate, the isolation layer covers the entire sidewall of the bottom fin portion and exposes the entire sidewall of the first effective fin portion, thereby reducing time and cost required for subsequently removing the first effective fin portion in the first device region i and time and cost required for forming the second effective fin portion as much as possible. The channel material layer 120 is formed by an epitaxial process, which is beneficial to accurately controlling the thickness of the channel material layer 120.
Referring to fig. 7 and 8 in combination, in the first device region i and the second device region ii, the channel material layer 120 (shown in fig. 7) and the bottom fin material layer 110 (shown in fig. 7) are etched, so as to form a bottom fin 210 protruding from the substrate 100 and a first effective fin 220 located on the bottom fin 210.
In the first device region i, the first effective fin 220 is configured to occupy a spatial position for a subsequent formation of a second effective fin; in the second device region ii, the first active fin 220 is used to provide a channel for a transistor of a second type.
In the subsequent process of removing the first active fin portion 220 in the first device region i, the top surface of the bottom fin portion 210 is used to define a stop position of the etching process.
In this embodiment, the channel material layer 120 and the bottom fin material layer 110 are etched by an anisotropic dry etching process.
The anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate of the etching process is greater than the transverse etching rate thereof, which is beneficial to improving the sidewall morphology quality and the dimensional accuracy of the bottom fin portion 210 and the first effective fin portion 220. Moreover, by adopting the dry etching process, the channel material layer 120 and the bottom fin material layer 110 can be etched in the same etching chamber in sequence by changing the etching gas, and the etching process is simple.
It should be noted that the forming quality and the thickness uniformity of the channel material layer 120 are high, and in the process of etching the channel material layer 120 and the bottom fin material layer 110, the channel material layer 110 and the bottom fin material layer 120 are sequentially etched, so that the problem of etching two materials at the same time is avoided, and the uniformity of the etching effect is improved. In summary, in the present embodiment, the channel material layer 120 is formed on the bottom fin material layer 110, which is beneficial to improve the topography quality of the first effective fin 220, so as to improve the performance of the semiconductor structure.
As shown in fig. 8, in the present embodiment, a hard mask layer 240 is formed on the channel material layer 120.
The hard mask layer 240 is used as a mask when etching the channel material layer 120 and the bottom fin material layer 110.
The design patterns corresponding to the bottom fin portion 210 and the first effective fin portion 220 are transferred to the hard mask layer 240, and then the patterns are transferred to the channel material layer 120 and the bottom fin portion material layer 110 through the hard mask layer 240, so that the pattern transfer precision is improved.
Moreover, the top surface of the hard mask layer 240 is also used to define a stop location for the polishing process during subsequent processes.
The hard mask layer 240 is made of a nitrogen-containing material, so that the hard mask layer 240 has high hardness and density. In this embodiment, the material of the hard mask layer 240 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. These materials have a high degree of compactness and hardness, and the etching selectivity of both Si and SiGe to the above materials is high during the etching of the channel material layer 120 and the bottom fin material layer 110.
As an example, the hard mask layer 240 is made of silicon nitride.
In this embodiment, the hard mask layer 240 is formed by a multi-patterning process. By using the multiple patterning process, the density of the patterns formed on the substrate 100 is increased, and the pitch (pitch) between two adjacent patterns is further reduced, so that the limit of the photolithography resolution is overcome by the photolithography process.
Specifically, the multiple patterning process includes a self-aligned double patterning (SADP) process, a self-aligned quadruple patterning (SAQP) process, or a double exposure process. The double exposure process is called a LELE (lithography-etch-lithography-etch) process.
As an example, the hard mask layer 240 is formed using a self-aligned double patterning process.
Specifically, the step of forming the hard mask layer 240 includes: as shown in fig. 7, a hard mask material layer 140 is formed on the channel material layer 120; forming a core layer (not shown) on the hard mask material layer 140; forming a mask side wall 150 on the side wall of the core layer; removing the core layer; as shown in fig. 8, after removing the core layer, the hard mask material layer 140 is etched by using the mask sidewall 150 as a mask, so as to form a hard mask layer 240.
The material of the mask sidewall spacers 150 may include one or more of silicon oxide, silicon nitride, silicon, titanium oxide, titanium nitride, and tungsten carbide. In this embodiment, the mask sidewall spacers 150 are made of silicon nitride.
Correspondingly, in the step of forming the bottom fin portion 210 and the first effective fin portion 220, the channel material layer 120 and the bottom fin portion material layer 110 are etched by using the hard mask layer 240 as a mask.
Before forming the hard mask material layer 140 on the channel material layer 120, the forming method further includes: a buffer material layer 130 is formed overlying the channel material layer 120.
The buffer material layer 130 adheres well to the hard mask material layer 140, and the buffer material layer 130 adheres well to the channel material layer 120. Furthermore, the buffer material layer 130 is used to provide a stress buffer effect when forming the hard mask material layer 140, so as to improve the problem of dislocation generated when forming the hard mask material layer 140.
In this embodiment, the material of the buffer material layer 130 is silicon oxide.
Correspondingly, before etching the channel material layer 120 and the bottom fin material layer 110, the method further includes: and etching the buffer material layer 130 by using the hard mask layer 240 as a mask to form a buffer layer 230.
With reference to fig. 9 and 10, a filling layer 260 is formed on the substrate 100 where the first effective fins 220 and the bottom fins 210 are exposed, and the filling layer 260 covers sidewalls of the first effective fins 220 and exposes the top of the first effective fins 220.
The filling layer 260 is used for protecting the substrate 100, and the top of the filling layer 260 is higher than the top of the bottom fin portion 210, so that after the first effective fin portion 220 in the first device region i is subsequently removed, a trench surrounded by the filling layer 260 and the bottom fin portion 210 can be formed, and a spatial position is provided for subsequently forming a second effective fin portion.
Thus, the thickness of the fill layer 260 affects the height of the subsequent second active fins.
In this embodiment, the top of the filling layer 260 is flush with the top of the first effective fin portion 220, so that the top of the second effective fin portion formed subsequently is flush with the top of the first effective fin portion 220, thereby facilitating the subsequent processes, for example, improving the top surface flatness of the subsequent gate structure.
Specifically, the step of forming the filling layer 260 includes: as shown in fig. 9, an initial filling layer 250 is formed on the substrate 100 where the first effective fins 220 and the bottom fins 210 are exposed, and the initial filling layer 250 covers the top of the first effective fins 220; as shown in fig. 10, the initial fill layer 250 is planarized to expose the top of the first active fins 220, and the remaining initial fill layer 250 serves as a fill layer 260.
In this embodiment, the material of the filling layer 260 is a dielectric material.
The compatibility of the dielectric material with front end of line (FEOL) processing is high; moreover, an epitaxial process is subsequently adopted to form a second effective fin portion located in the groove, and the dielectric material is adopted, so that the dielectric material can be prevented from polluting a machine table for the epitaxial process; in addition, by selecting a dielectric material, the forming process of the filling layer 260 can be compatible with the forming process of the subsequent isolation layer, that is, the isolation layer can be formed by using the filling layer 260 subsequently, thereby simplifying the process steps.
In particular, the dielectric material comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide and boron nitride.
In this embodiment, the dielectric material is silicon oxide.
Accordingly, in this embodiment, the initial filling layer 250 is formed by a deposition process. Specifically, the deposition process is a Fluid Chemical Vapor Deposition (FCVD) process. The FCVD process has good gap filling capability, and the initial filling layer 250 is easily filled between the first effective fins 220 and between the bottom fins 210, so that the probability of forming defects such as voids in the initial filling layer 250 is reduced, and the formation quality of the filling layer 260 is correspondingly improved.
In other embodiments, the initial filling layer may also be formed by a High Aspect Ratio (HARP) chemical vapor deposition process. The high aspect ratio chemical vapor deposition process can meet the filling requirement of the opening with a higher aspect ratio, so that the gap filling effect of the initial filling layer can be improved by adopting the high aspect ratio chemical vapor deposition process.
In this embodiment, after the initial filling layer 250 is formed, the initial filling layer 250 covers the hard mask layer 240.
For this purpose, the step of performing the planarization process on the initial filling layer 250 includes: taking the top of the hard mask layer 240 as a stop position, and grinding the initial filling layer 250; after the grinding process, removing the hard mask layer 240; after removing the hard mask layer 240, the remaining initial filling layer 250 is etched back with the top of the first effective fin portion 220 as a stop position.
Compared with the initial filling layer 250, the hard mask layer 240 has higher density and hardness, and therefore, by performing the grinding process first, a stop position of the grinding process can be defined by the top of the hard mask layer 240, thereby facilitating to improve the flatness of the top surface of the remaining initial filling layer 250. By removing the hard mask layer 240 first, it is convenient to be able to perform an etch-back process on the remaining initial filling layer 250.
Furthermore, the initial thickness of the initial filling layer 250 is generally large, and the initial filling layer 250 above the top of the hard mask layer 240 can be removed quickly by performing a grinding process on the initial filling layer 250. The thickness of the hard mask layer 240 is generally smaller, that is, after the hard mask layer 240 is removed, the distance from the top of the remaining initial filling layer 250 to the top of the first effective fin 220 is smaller, so that the removal amount of the remaining initial filling layer 250 is favorably and precisely controlled by performing the back etching process on the remaining initial filling layer 250.
It should be noted that the material of the initial filling layer 250 and the buffer layer 230 are the same, so that the buffer layer 230 is also removed during the etch-back process.
In this embodiment, the polishing process is performed by a chemical mechanical polishing process, and the etch-back process is performed by an anisotropic dry etching process.
With combined reference to fig. 11 to 13, the first effective fins 220 in the first device region i are removed, and a trench 265 (shown in fig. 13) surrounded by the filling layer 260 and the bottom fin 210 is formed.
The trench 265 is used to provide a spatial location for the subsequent formation of a second active fin.
Trenches 265 are enclosed by the fill layer 260 and bottom fins 210, which facilitates precise control of the second active fin topography and line width dimensions.
In this embodiment, a wet etching process is used to remove the first effective fin portion 220.
The wet etching process has the characteristic of isotropic etching, so that the first effective fin portion 220 can be removed cleanly and the removal rate is high.
Specifically, the first effective fin 220 is made of SiGe, and therefore, an etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid, hydrogen peroxide and acetic acid.
With the continuous decrease of the feature size, the line width of the first effective fin portion 220 gradually decreases, and correspondingly, the aspect ratio of the trench 265 gradually increases, and the first effective fin portion 220 located in the trench 265 with the larger aspect ratio is easily etched by the mixed solution of hydrofluoric acid, hydrogen peroxide and acetic acid, and the uniformity of the etching rate is higher.
In this embodiment, in the step of removing the first effective fin portion 220, an etching selection ratio between the first effective fin portion 220 and the bottom fin portion 210 is greater than or equal to 10, so as to reduce damage to the bottom fin portion 210.
Specifically, the step of removing the first effective fin 220 in the first device region i includes: forming a shielding layer 270 on the filling layer 260, wherein an opening 280 is formed in the shielding layer 270, and the opening 280 exposes the first effective fin portions 220 in the first device region i and the filling layer 260 between the adjacent first effective fin portions 220; removing the first effective fin portions 220 exposed by the openings 280 by using the shielding layer 270 as a mask; the masking layer 270 is removed.
The shielding layer 270 is used for protecting the first effective fin portion 220 of the second device region ii.
In this embodiment, the material of the shielding layer 270 is a Si-ARC (silicon-based anti-reflective coating) material.
The shape of the opening 280 is generally defined by a pattern in a photoresist layer, the Si-ARC layer is advantageous for increasing the depth of field (DOF) of exposure during a photolithography process, and for improving the uniformity of exposure, and the Si-ARC layer is rich in silicon, thereby being advantageous for improving the hardness of the barrier layer 270, and thus further improving the pattern transfer accuracy.
Thus, by using a Si-ARC material, compatibility with photolithographic processes is facilitated.
In other embodiments, the material of the blocking layer may also be a bottom-antireflective coating (BARC) material or a dielectric-antireflective coating (DARC) material.
Moreover, the opening 280 exposes the first effective fin portion 220 in the first device region i and the filling layer 260 between the adjacent first effective fin portions 220, and the line width of the opening 280 is large, so that a process window for forming the opening 280 is increased, and an etching solution adopted in a wet etching process is easily contacted with the first effective fin portion 220.
In this embodiment, after the trench 265 is formed, the shielding layer 270 is removed, so as to prepare for a subsequent epitaxial process, and prevent the shielding layer 270 from contaminating a machine for performing the epitaxial process.
As shown in fig. 12, in the present embodiment, before removing the first effective fins 220 in the first device region i, the forming method further includes: in the second device region ii, a protection layer 290 is formed covering the first active fin 220.
On one hand, the protection layer 290 can protect the first effective fin portion 220 of the second device region ii in the process of removing the first effective fin portion 220 in the first device region i; on the other hand, when the second effective fin portion is formed in the trench 265 by an epitaxial process, the surface of the first effective fin portion 220 in the second device region ii can be prevented from being epitaxially grown under the protection of the protection layer 290.
The material of the protection layer 290 is selected from: when the protection layer 290 is removed subsequently, the protection layer 290 has a higher etching selectivity with respect to the filling layer 260, the first active fin portion 220, and the bottom fin portion 210.
Accordingly, the material of the protection layer 290 includes silicon nitride or silicon oxynitride.
As an example, the material of the protection layer 290 is silicon nitride. The compactness of the silicon nitride is higher, and the protection effect is correspondingly higher. Moreover, the silicon nitride has a high etching selection ratio with silicon, silicon germanium and silicon oxide.
Note that the thickness of the protective layer 290 should not be too small, and should not be too large. If the thickness of the protection layer 290 is too small, the thickness uniformity of the protection layer 290 is poor, so that the probability that the first effective fin portion 220 of the second device region ii is exposed is increased, and the probability that the epitaxial growth is performed on the surface of the first effective fin portion 220 of the second device region ii subsequently is increased; if the thickness of the protective layer 290 is too large, a corresponding increase in process costs and time required for forming the protective layer 290 and for subsequently removing the protective layer 290 may result. For this purpose, in this embodiment, the thickness of the protection layer 290 is
Figure BDA0002699548040000151
To
Figure BDA0002699548040000152
For example, the protective layer 290 has a thickness of
Figure BDA0002699548040000153
Specifically, the step of forming the protective layer 290 includes: as shown in fig. 11, a protective material layer 295 covering the filling layer 260 and the first active fins 220 is formed; as shown in fig. 12, in the first device region i, the protective material layer 295 is etched to expose the first effective fin portion 220 in the first device region i, and the remaining protective material layer 295 serves as a protective layer 290.
In this embodiment, the protective material layer 295 is formed after the protective material layer 295 is formed and before the protective material layer 295 is etched. Accordingly, the shielding layer 270 is formed on the protective material layer 295.
By forming the blocking layer 270 on the protective material layer 295 before etching the protective material layer 295, the protective material layer 295 can be etched using the blocking layer 270 as a mask, thereby simplifying the process steps.
Referring to fig. 14, second active fins 310 are formed in the trenches 265 (shown in fig. 13), the second active fins 310 being for providing channels for transistors of the first type.
The trench 265 is formed by removing the first effective fin portion 220, the first effective fin portion 220 has a high profile quality, and the trench 265 has a correspondingly high profile quality, so that the profile quality of the second effective fin portion 310 is improved, and the performance of the semiconductor structure is improved.
In this embodiment, the first type transistor is an NMOS transistor, and thus the material of the second active fin 310 is Si.
The second effective fin portion 310 and the bottom fin portion 210 are made of the same material, which is beneficial to improving the bonding strength between the second effective fin portion 310 and the bottom fin portion 210.
In this embodiment, an epitaxial process is used to form the second effective fin portion 310 in the trench 265.
The second effective fins 310 are epitaxially grown on the basis of the bottom fins 210, which results in a better formation quality of the second effective fins 310.
Moreover, in the present embodiment, in the process of forming the second effective fin portion 310, epitaxial growth is performed on the basis that the bottom fin portion 210 is exposed at the bottom of the trench 265, so that it is beneficial to control the epitaxial growth direction of the material of the second effective fin portion 310, and further the second effective fin portion 310 is limited in the trench 265, so that the shape and quality of the second effective fin portion 310 are guaranteed.
Under the protection of the protection layer 290, the epitaxial growth on the surface of the first effective fin portion 220 in the second device region ii can be prevented.
In this embodiment, the top of the second effective fin 310 is flush with the top of the first effective fin 220.
In this embodiment, an isolation layer needs to be formed on the substrate 100 subsequently, so that after the second effective fin 310 is formed in the trench 265, the forming method further includes: the protective layer 290 is removed.
Specifically, the protective layer 290 is wet-etched using a phosphoric acid solution, so that the protective layer 290 is removed. The phosphoric acid solution has a low etching rate for silicon, silicon germanium and silicon oxide.
It should be noted that, according to actual conditions, when the top of the second effective fin portion 310 is higher than the top of the first effective fin portion 220 after the second effective fin portion 310 is formed, a planarization process (for example, a chemical mechanical polishing process) may be further performed on the second effective fin portion 310, so that the top of the remaining second effective fin portion 310 is flush with the top of the first effective fin portion 220.
The line width of the trench 265 is smaller, so that the removal amount of the second effective fin portion 310 is smaller in the planarization process, which is beneficial to reducing the requirement of the planarization process on the ratio of the removal rate of the second effective fin portion 310 to the removal rate of the first effective fin portion 220, after the planarization process, the top surfaces of the second effective fin portion 310 and the first effective fin portion 220 have higher flatness, and the thicknesses of the second effective fin portion 310 and the first effective fin portion 220 are easy to meet the actual requirement.
Referring to fig. 15, an isolation layer 101 is formed on the substrate 100, the isolation layer 101 covers sidewalls of the bottom fins 210, and the isolation layer 101 exposes a portion of sidewalls or entire sidewalls of any of the first and second effective fins 220 and 310.
The isolation layer 101 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent devices.
In this embodiment, the isolation layer 101 covers the sidewalls of the bottom fin portion 210, so as to prevent the sidewalls of the bottom fin portion 210 from being exposed, and further prevent the bottom fin portion 210 from affecting the channel of the transistor.
The isolation layer 101 may expose the entire sidewall or a portion of the sidewall of the first effective fin 220 according to the height of the first effective fin 220 and a preset height of a portion of the first effective fin 220 covered by the gate structure.
Similarly, the isolation layer 101 may expose the entire sidewall or a portion of the sidewall of the second active fin 310.
As an example, the heights of the first effective fin portion 220 and the second effective fin portion 310 are equal, the tops of the first effective fin portion 220 and the second effective fin portion 310 are flush, and the isolation layer 101 exposes the entire sidewall of the first effective fin portion 220 and also exposes the entire sidewall of the second effective fin portion 310. That is, the top of the isolation layer 101 and the top of the bottom fin 210 are flush.
Specifically, the material of the filling layer 260 (as shown in fig. 13) is a dielectric material, and therefore, the step of forming the isolation layer 101 on the substrate 100 includes: and etching back part of the thickness of the filling layer 260, wherein the rest of the filling layer 260 serves as an isolation layer 101.
In this embodiment, the dielectric material is silicon oxide, and correspondingly, the isolation layer 101 is made of silicon oxide. In other embodiments, the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
In this embodiment, the filling layer 260 is formed by using the process of forming the isolation layer 101. In other embodiments, the filling layer with material characteristics meeting the process requirements can be formed separately; correspondingly, after the second effective fin portion is formed in the groove, the filling layer is removed, and then an isolation layer is formed on the substrate.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, channel conduction types of the first type transistor and the second type transistor are different, a bottom fin material layer and a channel material layer located on the bottom fin material layer are formed on the substrate, the channel material layer is used for forming a first effective fin, and the first effective fin is used for providing a channel of the second type transistor;
etching the channel material layer and the bottom fin material layer in the first device region and the second device region to form a bottom fin portion protruding out of the substrate and a first effective fin portion located on the bottom fin portion;
forming a filling layer on the substrate exposed out of the first effective fin part and the bottom fin part, wherein the filling layer covers the side wall of the first effective fin part and exposes out of the top of the first effective fin part;
removing the first effective fin part in the first device region to form a groove surrounded by the filling layer and the bottom fin part;
forming a second effective fin part in the groove, wherein the second effective fin part is used for providing a channel of the first-type transistor;
and forming an isolation layer on the substrate, wherein the isolation layer covers the side wall of the bottom fin part and exposes a part of or the whole side wall of any one of the first effective fin part and the second effective fin part.
2. The method of forming a semiconductor structure of claim 1, wherein forming the fill layer comprises: forming an initial filling layer on the substrate with the exposed first effective fin part and the exposed bottom fin part, wherein the initial filling layer covers the top of the first effective fin part;
and carrying out planarization treatment on the initial filling layer to expose the top of the first effective fin part, wherein the rest initial filling layer is used as a filling layer.
3. The method of claim 1, wherein the material of the fill layer is a dielectric material.
4. The method of forming a semiconductor structure of claim 3, wherein the dielectric material comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, and boron nitride.
5. The method of forming a semiconductor structure of claim 1 or 3, wherein the step of forming an isolation layer on the substrate comprises: and etching back the filling layer with partial thickness, wherein the rest filling layer is used as an isolation layer.
6. The method of forming a semiconductor structure of claim 2, wherein in the step of providing a substrate, a hard mask layer is formed on the channel material layer;
in the step of forming the bottom fin portion and the first effective fin portion, the hard mask layer is used as a mask, and the channel material layer and the bottom fin portion material layer are etched;
the step of performing planarization treatment on the initial filling layer comprises the following steps: taking the top of the hard mask layer as a stop position, and grinding the initial filling layer; after the grinding treatment, removing the hard mask layer; and after removing the hard mask layer, performing back etching treatment on the residual initial filling layer by taking the top of the first effective fin part as a stop position.
7. The method of claim 6, wherein the hard mask layer formation process comprises a multiple patterning process.
8. The method of forming a semiconductor structure of claim 1, wherein after forming a fill layer on the substrate with the first active fin and bottom fin exposed, and before removing the first active fin in the first device region, the method further comprises: forming a protective layer covering the first effective fin part in the second device area;
after forming the second effective fin portion in the trench and before forming an isolation layer on the substrate, the forming method further includes: and removing the protective layer.
9. The method of forming a semiconductor structure of claim 8, wherein forming the protective layer comprises: forming a protective material layer covering the filling layer and the first effective fin portion;
and etching the protective material layer in the first device area to expose the first effective fin part in the first device area, wherein the residual protective material layer is used as a protective layer.
10. The method of forming a semiconductor structure of claim 8, wherein a material of the protective layer comprises silicon nitride or silicon oxynitride.
11. The method of forming a semiconductor structure of claim 8, wherein the protective layer has a thickness of
Figure FDA0002699548030000031
To
Figure FDA0002699548030000032
12. The method of forming a semiconductor structure of claim 1, wherein removing the first active fin in the first device region comprises: forming a shielding layer on the filling layer, wherein an opening is formed in the shielding layer, and the opening exposes the first effective fin portions in the first device region and the filling layer between the adjacent first effective fin portions;
removing the first effective fin part exposed from the opening by taking the shielding layer as a mask;
and removing the shielding layer.
13. The method of claim 1, wherein the channel material layer is formed on the bottom fin material layer using an epitaxial process.
14. The method of claim 1, wherein the channel material layer and the bottom fin material layer are etched using an anisotropic dry etch process.
15. The method of claim 1, wherein the second active fin is formed in the trench using an epitaxial process.
16. The method of claim 1, wherein the first active fin portion is removed using a wet etch process.
17. The method of claim 16, wherein the wet etching process uses an etching solution comprising a mixture of hydrofluoric acid, hydrogen peroxide, and acetic acid.
18. The method of claim 1, wherein the first active fin portion is removed by an etching process, and an etch selectivity between the first active fin portion and the bottom fin portion is greater than or equal to 10.
19. The method of claim 1, wherein the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor;
the material of the bottom fin material layer is Si, the material of the channel material layer is SiGe, and the material of the second effective fin portion is Si.
20. The method of claim 1, wherein the bottom fin material layer and the substrate are a unitary structure.
CN202011017468.3A 2020-09-24 2020-09-24 Method for forming semiconductor structure Pending CN114256349A (en)

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